intel_scu_watchdog.h 1.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Intel_SCU 0.2: An Intel SCU IOH Based Watchdog Device
  4. * for Intel part #(s):
  5. * - AF82MP20 PCH
  6. *
  7. * Copyright (C) 2009-2010 Intel Corporation. All rights reserved.
  8. */
  9. #ifndef __INTEL_SCU_WATCHDOG_H
  10. #define __INTEL_SCU_WATCHDOG_H
  11. #define WDT_VER "0.3"
  12. /* minimum time between interrupts */
  13. #define MIN_TIME_CYCLE 1
  14. /* Time from warning to reboot is 2 seconds */
  15. #define DEFAULT_SOFT_TO_HARD_MARGIN 2
  16. #define MAX_TIME 170
  17. #define DEFAULT_TIME 5
  18. #define MAX_SOFT_TO_HARD_MARGIN (MAX_TIME-MIN_TIME_CYCLE)
  19. /* Ajustment to clock tick frequency to make timing come out right */
  20. #define FREQ_ADJUSTMENT 8
  21. struct intel_scu_watchdog_dev {
  22. ulong driver_open;
  23. ulong driver_closed;
  24. u32 timer_started;
  25. u32 timer_set;
  26. u32 threshold;
  27. u32 soft_threshold;
  28. u32 __iomem *timer_load_count_addr;
  29. u32 __iomem *timer_current_value_addr;
  30. u32 __iomem *timer_control_addr;
  31. u32 __iomem *timer_clear_interrupt_addr;
  32. u32 __iomem *timer_interrupt_status_addr;
  33. struct sfi_timer_table_entry *timer_tbl_ptr;
  34. struct notifier_block intel_scu_notifier;
  35. struct miscdevice miscdev;
  36. };
  37. extern int sfi_mtimer_num;
  38. /* extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint); */
  39. #endif /* __INTEL_SCU_WATCHDOG_H */