intel_scu_watchdog.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Intel_SCU 0.2: An Intel SCU IOH Based Watchdog Device
  4. * for Intel part #(s):
  5. * - AF82MP20 PCH
  6. *
  7. * Copyright (C) 2009-2010 Intel Corporation. All rights reserved.
  8. */
  9. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10. #include <linux/compiler.h>
  11. #include <linux/kernel.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/types.h>
  14. #include <linux/miscdevice.h>
  15. #include <linux/watchdog.h>
  16. #include <linux/fs.h>
  17. #include <linux/notifier.h>
  18. #include <linux/reboot.h>
  19. #include <linux/init.h>
  20. #include <linux/jiffies.h>
  21. #include <linux/uaccess.h>
  22. #include <linux/slab.h>
  23. #include <linux/io.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/delay.h>
  26. #include <linux/sched.h>
  27. #include <linux/signal.h>
  28. #include <linux/sfi.h>
  29. #include <asm/irq.h>
  30. #include <linux/atomic.h>
  31. #include <asm/intel_scu_ipc.h>
  32. #include <asm/apb_timer.h>
  33. #include <asm/intel-mid.h>
  34. #include "intel_scu_watchdog.h"
  35. /* Bounds number of times we will retry loading time count */
  36. /* This retry is a work around for a silicon bug. */
  37. #define MAX_RETRY 16
  38. #define IPC_SET_WATCHDOG_TIMER 0xF8
  39. static int timer_margin = DEFAULT_SOFT_TO_HARD_MARGIN;
  40. module_param(timer_margin, int, 0);
  41. MODULE_PARM_DESC(timer_margin,
  42. "Watchdog timer margin"
  43. "Time between interrupt and resetting the system"
  44. "The range is from 1 to 160"
  45. "This is the time for all keep alives to arrive");
  46. static int timer_set = DEFAULT_TIME;
  47. module_param(timer_set, int, 0);
  48. MODULE_PARM_DESC(timer_set,
  49. "Default Watchdog timer setting"
  50. "Complete cycle time"
  51. "The range is from 1 to 170"
  52. "This is the time for all keep alives to arrive");
  53. /* After watchdog device is closed, check force_boot. If:
  54. * force_boot == 0, then force boot on next watchdog interrupt after close,
  55. * force_boot == 1, then force boot immediately when device is closed.
  56. */
  57. static int force_boot;
  58. module_param(force_boot, int, 0);
  59. MODULE_PARM_DESC(force_boot,
  60. "A value of 1 means that the driver will reboot"
  61. "the system immediately if the /dev/watchdog device is closed"
  62. "A value of 0 means that when /dev/watchdog device is closed"
  63. "the watchdog timer will be refreshed for one more interval"
  64. "of length: timer_set. At the end of this interval, the"
  65. "watchdog timer will reset the system."
  66. );
  67. /* there is only one device in the system now; this can be made into
  68. * an array in the future if we have more than one device */
  69. static struct intel_scu_watchdog_dev watchdog_device;
  70. /* Forces restart, if force_reboot is set */
  71. static void watchdog_fire(void)
  72. {
  73. if (force_boot) {
  74. pr_crit("Initiating system reboot\n");
  75. emergency_restart();
  76. pr_crit("Reboot didn't ?????\n");
  77. }
  78. else {
  79. pr_crit("Immediate Reboot Disabled\n");
  80. pr_crit("System will reset when watchdog timer times out!\n");
  81. }
  82. }
  83. static int check_timer_margin(int new_margin)
  84. {
  85. if ((new_margin < MIN_TIME_CYCLE) ||
  86. (new_margin > MAX_TIME - timer_set)) {
  87. pr_debug("value of new_margin %d is out of the range %d to %d\n",
  88. new_margin, MIN_TIME_CYCLE, MAX_TIME - timer_set);
  89. return -EINVAL;
  90. }
  91. return 0;
  92. }
  93. /*
  94. * IPC operations
  95. */
  96. static int watchdog_set_ipc(int soft_threshold, int threshold)
  97. {
  98. u32 *ipc_wbuf;
  99. u8 cbuf[16] = { '\0' };
  100. int ipc_ret = 0;
  101. ipc_wbuf = (u32 *)&cbuf;
  102. ipc_wbuf[0] = soft_threshold;
  103. ipc_wbuf[1] = threshold;
  104. ipc_ret = intel_scu_ipc_command(
  105. IPC_SET_WATCHDOG_TIMER,
  106. 0,
  107. ipc_wbuf,
  108. 2,
  109. NULL,
  110. 0);
  111. if (ipc_ret != 0)
  112. pr_err("Error setting SCU watchdog timer: %x\n", ipc_ret);
  113. return ipc_ret;
  114. };
  115. /*
  116. * Intel_SCU operations
  117. */
  118. /* timer interrupt handler */
  119. static irqreturn_t watchdog_timer_interrupt(int irq, void *dev_id)
  120. {
  121. int int_status;
  122. int_status = ioread32(watchdog_device.timer_interrupt_status_addr);
  123. pr_debug("irq, int_status: %x\n", int_status);
  124. if (int_status != 0)
  125. return IRQ_NONE;
  126. /* has the timer been started? If not, then this is spurious */
  127. if (watchdog_device.timer_started == 0) {
  128. pr_debug("spurious interrupt received\n");
  129. return IRQ_HANDLED;
  130. }
  131. /* temporarily disable the timer */
  132. iowrite32(0x00000002, watchdog_device.timer_control_addr);
  133. /* set the timer to the threshold */
  134. iowrite32(watchdog_device.threshold,
  135. watchdog_device.timer_load_count_addr);
  136. /* allow the timer to run */
  137. iowrite32(0x00000003, watchdog_device.timer_control_addr);
  138. return IRQ_HANDLED;
  139. }
  140. static int intel_scu_keepalive(void)
  141. {
  142. /* read eoi register - clears interrupt */
  143. ioread32(watchdog_device.timer_clear_interrupt_addr);
  144. /* temporarily disable the timer */
  145. iowrite32(0x00000002, watchdog_device.timer_control_addr);
  146. /* set the timer to the soft_threshold */
  147. iowrite32(watchdog_device.soft_threshold,
  148. watchdog_device.timer_load_count_addr);
  149. /* allow the timer to run */
  150. iowrite32(0x00000003, watchdog_device.timer_control_addr);
  151. return 0;
  152. }
  153. static int intel_scu_stop(void)
  154. {
  155. iowrite32(0, watchdog_device.timer_control_addr);
  156. return 0;
  157. }
  158. static int intel_scu_set_heartbeat(u32 t)
  159. {
  160. int ipc_ret;
  161. int retry_count;
  162. u32 soft_value;
  163. u32 hw_value;
  164. watchdog_device.timer_set = t;
  165. watchdog_device.threshold =
  166. timer_margin * watchdog_device.timer_tbl_ptr->freq_hz;
  167. watchdog_device.soft_threshold =
  168. (watchdog_device.timer_set - timer_margin)
  169. * watchdog_device.timer_tbl_ptr->freq_hz;
  170. pr_debug("set_heartbeat: timer freq is %d\n",
  171. watchdog_device.timer_tbl_ptr->freq_hz);
  172. pr_debug("set_heartbeat: timer_set is %x (hex)\n",
  173. watchdog_device.timer_set);
  174. pr_debug("set_heartbeat: timer_margin is %x (hex)\n", timer_margin);
  175. pr_debug("set_heartbeat: threshold is %x (hex)\n",
  176. watchdog_device.threshold);
  177. pr_debug("set_heartbeat: soft_threshold is %x (hex)\n",
  178. watchdog_device.soft_threshold);
  179. /* Adjust thresholds by FREQ_ADJUSTMENT factor, to make the */
  180. /* watchdog timing come out right. */
  181. watchdog_device.threshold =
  182. watchdog_device.threshold / FREQ_ADJUSTMENT;
  183. watchdog_device.soft_threshold =
  184. watchdog_device.soft_threshold / FREQ_ADJUSTMENT;
  185. /* temporarily disable the timer */
  186. iowrite32(0x00000002, watchdog_device.timer_control_addr);
  187. /* send the threshold and soft_threshold via IPC to the processor */
  188. ipc_ret = watchdog_set_ipc(watchdog_device.soft_threshold,
  189. watchdog_device.threshold);
  190. if (ipc_ret != 0) {
  191. /* Make sure the watchdog timer is stopped */
  192. intel_scu_stop();
  193. return ipc_ret;
  194. }
  195. /* Soft Threshold set loop. Early versions of silicon did */
  196. /* not always set this count correctly. This loop checks */
  197. /* the value and retries if it was not set correctly. */
  198. retry_count = 0;
  199. soft_value = watchdog_device.soft_threshold & 0xFFFF0000;
  200. do {
  201. /* Make sure timer is stopped */
  202. intel_scu_stop();
  203. if (MAX_RETRY < retry_count++) {
  204. /* Unable to set timer value */
  205. pr_err("Unable to set timer\n");
  206. return -ENODEV;
  207. }
  208. /* set the timer to the soft threshold */
  209. iowrite32(watchdog_device.soft_threshold,
  210. watchdog_device.timer_load_count_addr);
  211. /* read count value before starting timer */
  212. ioread32(watchdog_device.timer_load_count_addr);
  213. /* Start the timer */
  214. iowrite32(0x00000003, watchdog_device.timer_control_addr);
  215. /* read the value the time loaded into its count reg */
  216. hw_value = ioread32(watchdog_device.timer_load_count_addr);
  217. hw_value = hw_value & 0xFFFF0000;
  218. } while (soft_value != hw_value);
  219. watchdog_device.timer_started = 1;
  220. return 0;
  221. }
  222. /*
  223. * /dev/watchdog handling
  224. */
  225. static int intel_scu_open(struct inode *inode, struct file *file)
  226. {
  227. /* Set flag to indicate that watchdog device is open */
  228. if (test_and_set_bit(0, &watchdog_device.driver_open))
  229. return -EBUSY;
  230. /* Check for reopen of driver. Reopens are not allowed */
  231. if (watchdog_device.driver_closed)
  232. return -EPERM;
  233. return stream_open(inode, file);
  234. }
  235. static int intel_scu_release(struct inode *inode, struct file *file)
  236. {
  237. /*
  238. * This watchdog should not be closed, after the timer
  239. * is started with the WDIPC_SETTIMEOUT ioctl
  240. * If force_boot is set watchdog_fire() will cause an
  241. * immediate reset. If force_boot is not set, the watchdog
  242. * timer is refreshed for one more interval. At the end
  243. * of that interval, the watchdog timer will reset the system.
  244. */
  245. if (!test_and_clear_bit(0, &watchdog_device.driver_open)) {
  246. pr_debug("intel_scu_release, without open\n");
  247. return -ENOTTY;
  248. }
  249. if (!watchdog_device.timer_started) {
  250. /* Just close, since timer has not been started */
  251. pr_debug("closed, without starting timer\n");
  252. return 0;
  253. }
  254. pr_crit("Unexpected close of /dev/watchdog!\n");
  255. /* Since the timer was started, prevent future reopens */
  256. watchdog_device.driver_closed = 1;
  257. /* Refresh the timer for one more interval */
  258. intel_scu_keepalive();
  259. /* Reboot system (if force_boot is set) */
  260. watchdog_fire();
  261. /* We should only reach this point if force_boot is not set */
  262. return 0;
  263. }
  264. static ssize_t intel_scu_write(struct file *file,
  265. char const *data,
  266. size_t len,
  267. loff_t *ppos)
  268. {
  269. if (watchdog_device.timer_started)
  270. /* Watchdog already started, keep it alive */
  271. intel_scu_keepalive();
  272. else
  273. /* Start watchdog with timer value set by init */
  274. intel_scu_set_heartbeat(watchdog_device.timer_set);
  275. return len;
  276. }
  277. static long intel_scu_ioctl(struct file *file,
  278. unsigned int cmd,
  279. unsigned long arg)
  280. {
  281. void __user *argp = (void __user *)arg;
  282. u32 __user *p = argp;
  283. u32 new_margin;
  284. static const struct watchdog_info ident = {
  285. .options = WDIOF_SETTIMEOUT
  286. | WDIOF_KEEPALIVEPING,
  287. .firmware_version = 0, /* @todo Get from SCU via
  288. ipc_get_scu_fw_version()? */
  289. .identity = "Intel_SCU IOH Watchdog" /* len < 32 */
  290. };
  291. switch (cmd) {
  292. case WDIOC_GETSUPPORT:
  293. return copy_to_user(argp,
  294. &ident,
  295. sizeof(ident)) ? -EFAULT : 0;
  296. case WDIOC_GETSTATUS:
  297. case WDIOC_GETBOOTSTATUS:
  298. return put_user(0, p);
  299. case WDIOC_KEEPALIVE:
  300. intel_scu_keepalive();
  301. return 0;
  302. case WDIOC_SETTIMEOUT:
  303. if (get_user(new_margin, p))
  304. return -EFAULT;
  305. if (check_timer_margin(new_margin))
  306. return -EINVAL;
  307. if (intel_scu_set_heartbeat(new_margin))
  308. return -EINVAL;
  309. return 0;
  310. case WDIOC_GETTIMEOUT:
  311. return put_user(watchdog_device.soft_threshold, p);
  312. default:
  313. return -ENOTTY;
  314. }
  315. }
  316. /*
  317. * Notifier for system down
  318. */
  319. static int intel_scu_notify_sys(struct notifier_block *this,
  320. unsigned long code,
  321. void *another_unused)
  322. {
  323. if (code == SYS_DOWN || code == SYS_HALT)
  324. /* Turn off the watchdog timer. */
  325. intel_scu_stop();
  326. return NOTIFY_DONE;
  327. }
  328. /*
  329. * Kernel Interfaces
  330. */
  331. static const struct file_operations intel_scu_fops = {
  332. .owner = THIS_MODULE,
  333. .llseek = no_llseek,
  334. .write = intel_scu_write,
  335. .unlocked_ioctl = intel_scu_ioctl,
  336. .compat_ioctl = compat_ptr_ioctl,
  337. .open = intel_scu_open,
  338. .release = intel_scu_release,
  339. };
  340. static int __init intel_scu_watchdog_init(void)
  341. {
  342. int ret;
  343. u32 __iomem *tmp_addr;
  344. /*
  345. * We don't really need to check this as the SFI timer get will fail
  346. * but if we do so we can exit with a clearer reason and no noise.
  347. *
  348. * If it isn't an intel MID device then it doesn't have this watchdog
  349. */
  350. if (!intel_mid_identify_cpu())
  351. return -ENODEV;
  352. /* Check boot parameters to verify that their initial values */
  353. /* are in range. */
  354. /* Check value of timer_set boot parameter */
  355. if ((timer_set < MIN_TIME_CYCLE) ||
  356. (timer_set > MAX_TIME - MIN_TIME_CYCLE)) {
  357. pr_err("value of timer_set %x (hex) is out of range from %x to %x (hex)\n",
  358. timer_set, MIN_TIME_CYCLE, MAX_TIME - MIN_TIME_CYCLE);
  359. return -EINVAL;
  360. }
  361. /* Check value of timer_margin boot parameter */
  362. if (check_timer_margin(timer_margin))
  363. return -EINVAL;
  364. watchdog_device.timer_tbl_ptr = sfi_get_mtmr(sfi_mtimer_num-1);
  365. if (watchdog_device.timer_tbl_ptr == NULL) {
  366. pr_debug("timer is not available\n");
  367. return -ENODEV;
  368. }
  369. /* make sure the timer exists */
  370. if (watchdog_device.timer_tbl_ptr->phys_addr == 0) {
  371. pr_debug("timer %d does not have valid physical memory\n",
  372. sfi_mtimer_num);
  373. return -ENODEV;
  374. }
  375. if (watchdog_device.timer_tbl_ptr->irq == 0) {
  376. pr_debug("timer %d invalid irq\n", sfi_mtimer_num);
  377. return -ENODEV;
  378. }
  379. tmp_addr = ioremap(watchdog_device.timer_tbl_ptr->phys_addr,
  380. 20);
  381. if (tmp_addr == NULL) {
  382. pr_debug("timer unable to ioremap\n");
  383. return -ENOMEM;
  384. }
  385. watchdog_device.timer_load_count_addr = tmp_addr++;
  386. watchdog_device.timer_current_value_addr = tmp_addr++;
  387. watchdog_device.timer_control_addr = tmp_addr++;
  388. watchdog_device.timer_clear_interrupt_addr = tmp_addr++;
  389. watchdog_device.timer_interrupt_status_addr = tmp_addr++;
  390. /* Set the default time values in device structure */
  391. watchdog_device.timer_set = timer_set;
  392. watchdog_device.threshold =
  393. timer_margin * watchdog_device.timer_tbl_ptr->freq_hz;
  394. watchdog_device.soft_threshold =
  395. (watchdog_device.timer_set - timer_margin)
  396. * watchdog_device.timer_tbl_ptr->freq_hz;
  397. watchdog_device.intel_scu_notifier.notifier_call =
  398. intel_scu_notify_sys;
  399. ret = register_reboot_notifier(&watchdog_device.intel_scu_notifier);
  400. if (ret) {
  401. pr_err("cannot register notifier %d)\n", ret);
  402. goto register_reboot_error;
  403. }
  404. watchdog_device.miscdev.minor = WATCHDOG_MINOR;
  405. watchdog_device.miscdev.name = "watchdog";
  406. watchdog_device.miscdev.fops = &intel_scu_fops;
  407. ret = misc_register(&watchdog_device.miscdev);
  408. if (ret) {
  409. pr_err("cannot register miscdev %d err =%d\n",
  410. WATCHDOG_MINOR, ret);
  411. goto misc_register_error;
  412. }
  413. ret = request_irq((unsigned int)watchdog_device.timer_tbl_ptr->irq,
  414. watchdog_timer_interrupt,
  415. IRQF_SHARED, "watchdog",
  416. &watchdog_device.timer_load_count_addr);
  417. if (ret) {
  418. pr_err("error requesting irq %d\n", ret);
  419. goto request_irq_error;
  420. }
  421. /* Make sure timer is disabled before returning */
  422. intel_scu_stop();
  423. return 0;
  424. /* error cleanup */
  425. request_irq_error:
  426. misc_deregister(&watchdog_device.miscdev);
  427. misc_register_error:
  428. unregister_reboot_notifier(&watchdog_device.intel_scu_notifier);
  429. register_reboot_error:
  430. intel_scu_stop();
  431. iounmap(watchdog_device.timer_load_count_addr);
  432. return ret;
  433. }
  434. late_initcall(intel_scu_watchdog_init);