imgpdc_wdt.c 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Imagination Technologies PowerDown Controller Watchdog Timer.
  4. *
  5. * Copyright (c) 2014 Imagination Technologies Ltd.
  6. *
  7. * Based on drivers/watchdog/sunxi_wdt.c Copyright (c) 2013 Carlo Caione
  8. * 2012 Henrik Nordstrom
  9. *
  10. * Notes
  11. * -----
  12. * The timeout value is rounded to the next power of two clock cycles.
  13. * This is configured using the PDC_WDT_CONFIG register, according to this
  14. * formula:
  15. *
  16. * timeout = 2^(delay + 1) clock cycles
  17. *
  18. * Where 'delay' is the value written in PDC_WDT_CONFIG register.
  19. *
  20. * Therefore, the hardware only allows to program watchdog timeouts, expressed
  21. * as a power of two number of watchdog clock cycles. The current implementation
  22. * guarantees that the actual watchdog timeout will be _at least_ the value
  23. * programmed in the imgpdg_wdt driver.
  24. *
  25. * The following table shows how the user-configured timeout relates
  26. * to the actual hardware timeout (watchdog clock @ 40000 Hz):
  27. *
  28. * input timeout | WD_DELAY | actual timeout
  29. * -----------------------------------
  30. * 10 | 18 | 13 seconds
  31. * 20 | 19 | 26 seconds
  32. * 30 | 20 | 52 seconds
  33. * 60 | 21 | 104 seconds
  34. *
  35. * Albeit coarse, this granularity would suffice most watchdog uses.
  36. * If the platform allows it, the user should be able to change the watchdog
  37. * clock rate and achieve a finer timeout granularity.
  38. */
  39. #include <linux/clk.h>
  40. #include <linux/io.h>
  41. #include <linux/log2.h>
  42. #include <linux/module.h>
  43. #include <linux/mod_devicetable.h>
  44. #include <linux/platform_device.h>
  45. #include <linux/slab.h>
  46. #include <linux/watchdog.h>
  47. /* registers */
  48. #define PDC_WDT_SOFT_RESET 0x00
  49. #define PDC_WDT_CONFIG 0x04
  50. #define PDC_WDT_CONFIG_ENABLE BIT(31)
  51. #define PDC_WDT_CONFIG_DELAY_MASK 0x1f
  52. #define PDC_WDT_TICKLE1 0x08
  53. #define PDC_WDT_TICKLE1_MAGIC 0xabcd1234
  54. #define PDC_WDT_TICKLE2 0x0c
  55. #define PDC_WDT_TICKLE2_MAGIC 0x4321dcba
  56. #define PDC_WDT_TICKLE_STATUS_MASK 0x7
  57. #define PDC_WDT_TICKLE_STATUS_SHIFT 0
  58. #define PDC_WDT_TICKLE_STATUS_HRESET 0x0 /* Hard reset */
  59. #define PDC_WDT_TICKLE_STATUS_TIMEOUT 0x1 /* Timeout */
  60. #define PDC_WDT_TICKLE_STATUS_TICKLE 0x2 /* Tickled incorrectly */
  61. #define PDC_WDT_TICKLE_STATUS_SRESET 0x3 /* Soft reset */
  62. #define PDC_WDT_TICKLE_STATUS_USER 0x4 /* User reset */
  63. /* Timeout values are in seconds */
  64. #define PDC_WDT_MIN_TIMEOUT 1
  65. #define PDC_WDT_DEF_TIMEOUT 64
  66. static int heartbeat;
  67. module_param(heartbeat, int, 0);
  68. MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds "
  69. "(default=" __MODULE_STRING(PDC_WDT_DEF_TIMEOUT) ")");
  70. static bool nowayout = WATCHDOG_NOWAYOUT;
  71. module_param(nowayout, bool, 0);
  72. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
  73. "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  74. struct pdc_wdt_dev {
  75. struct watchdog_device wdt_dev;
  76. struct clk *wdt_clk;
  77. struct clk *sys_clk;
  78. void __iomem *base;
  79. };
  80. static int pdc_wdt_keepalive(struct watchdog_device *wdt_dev)
  81. {
  82. struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
  83. writel(PDC_WDT_TICKLE1_MAGIC, wdt->base + PDC_WDT_TICKLE1);
  84. writel(PDC_WDT_TICKLE2_MAGIC, wdt->base + PDC_WDT_TICKLE2);
  85. return 0;
  86. }
  87. static int pdc_wdt_stop(struct watchdog_device *wdt_dev)
  88. {
  89. unsigned int val;
  90. struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
  91. val = readl(wdt->base + PDC_WDT_CONFIG);
  92. val &= ~PDC_WDT_CONFIG_ENABLE;
  93. writel(val, wdt->base + PDC_WDT_CONFIG);
  94. /* Must tickle to finish the stop */
  95. pdc_wdt_keepalive(wdt_dev);
  96. return 0;
  97. }
  98. static void __pdc_wdt_set_timeout(struct pdc_wdt_dev *wdt)
  99. {
  100. unsigned long clk_rate = clk_get_rate(wdt->wdt_clk);
  101. unsigned int val;
  102. val = readl(wdt->base + PDC_WDT_CONFIG) & ~PDC_WDT_CONFIG_DELAY_MASK;
  103. val |= order_base_2(wdt->wdt_dev.timeout * clk_rate) - 1;
  104. writel(val, wdt->base + PDC_WDT_CONFIG);
  105. }
  106. static int pdc_wdt_set_timeout(struct watchdog_device *wdt_dev,
  107. unsigned int new_timeout)
  108. {
  109. struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
  110. wdt->wdt_dev.timeout = new_timeout;
  111. __pdc_wdt_set_timeout(wdt);
  112. return 0;
  113. }
  114. /* Start the watchdog timer (delay should already be set) */
  115. static int pdc_wdt_start(struct watchdog_device *wdt_dev)
  116. {
  117. unsigned int val;
  118. struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
  119. __pdc_wdt_set_timeout(wdt);
  120. val = readl(wdt->base + PDC_WDT_CONFIG);
  121. val |= PDC_WDT_CONFIG_ENABLE;
  122. writel(val, wdt->base + PDC_WDT_CONFIG);
  123. return 0;
  124. }
  125. static int pdc_wdt_restart(struct watchdog_device *wdt_dev,
  126. unsigned long action, void *data)
  127. {
  128. struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
  129. /* Assert SOFT_RESET */
  130. writel(0x1, wdt->base + PDC_WDT_SOFT_RESET);
  131. return 0;
  132. }
  133. static const struct watchdog_info pdc_wdt_info = {
  134. .identity = "IMG PDC Watchdog",
  135. .options = WDIOF_SETTIMEOUT |
  136. WDIOF_KEEPALIVEPING |
  137. WDIOF_MAGICCLOSE,
  138. };
  139. static const struct watchdog_ops pdc_wdt_ops = {
  140. .owner = THIS_MODULE,
  141. .start = pdc_wdt_start,
  142. .stop = pdc_wdt_stop,
  143. .ping = pdc_wdt_keepalive,
  144. .set_timeout = pdc_wdt_set_timeout,
  145. .restart = pdc_wdt_restart,
  146. };
  147. static void pdc_clk_disable_unprepare(void *data)
  148. {
  149. clk_disable_unprepare(data);
  150. }
  151. static int pdc_wdt_probe(struct platform_device *pdev)
  152. {
  153. struct device *dev = &pdev->dev;
  154. u64 div;
  155. int ret, val;
  156. unsigned long clk_rate;
  157. struct pdc_wdt_dev *pdc_wdt;
  158. pdc_wdt = devm_kzalloc(dev, sizeof(*pdc_wdt), GFP_KERNEL);
  159. if (!pdc_wdt)
  160. return -ENOMEM;
  161. pdc_wdt->base = devm_platform_ioremap_resource(pdev, 0);
  162. if (IS_ERR(pdc_wdt->base))
  163. return PTR_ERR(pdc_wdt->base);
  164. pdc_wdt->sys_clk = devm_clk_get(dev, "sys");
  165. if (IS_ERR(pdc_wdt->sys_clk)) {
  166. dev_err(dev, "failed to get the sys clock\n");
  167. return PTR_ERR(pdc_wdt->sys_clk);
  168. }
  169. pdc_wdt->wdt_clk = devm_clk_get(dev, "wdt");
  170. if (IS_ERR(pdc_wdt->wdt_clk)) {
  171. dev_err(dev, "failed to get the wdt clock\n");
  172. return PTR_ERR(pdc_wdt->wdt_clk);
  173. }
  174. ret = clk_prepare_enable(pdc_wdt->sys_clk);
  175. if (ret) {
  176. dev_err(dev, "could not prepare or enable sys clock\n");
  177. return ret;
  178. }
  179. ret = devm_add_action_or_reset(dev, pdc_clk_disable_unprepare,
  180. pdc_wdt->sys_clk);
  181. if (ret)
  182. return ret;
  183. ret = clk_prepare_enable(pdc_wdt->wdt_clk);
  184. if (ret) {
  185. dev_err(dev, "could not prepare or enable wdt clock\n");
  186. return ret;
  187. }
  188. ret = devm_add_action_or_reset(dev, pdc_clk_disable_unprepare,
  189. pdc_wdt->wdt_clk);
  190. if (ret)
  191. return ret;
  192. /* We use the clock rate to calculate the max timeout */
  193. clk_rate = clk_get_rate(pdc_wdt->wdt_clk);
  194. if (clk_rate == 0) {
  195. dev_err(dev, "failed to get clock rate\n");
  196. return -EINVAL;
  197. }
  198. if (order_base_2(clk_rate) > PDC_WDT_CONFIG_DELAY_MASK + 1) {
  199. dev_err(dev, "invalid clock rate\n");
  200. return -EINVAL;
  201. }
  202. if (order_base_2(clk_rate) == 0)
  203. pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT + 1;
  204. else
  205. pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT;
  206. pdc_wdt->wdt_dev.info = &pdc_wdt_info;
  207. pdc_wdt->wdt_dev.ops = &pdc_wdt_ops;
  208. div = 1ULL << (PDC_WDT_CONFIG_DELAY_MASK + 1);
  209. do_div(div, clk_rate);
  210. pdc_wdt->wdt_dev.max_timeout = div;
  211. pdc_wdt->wdt_dev.timeout = PDC_WDT_DEF_TIMEOUT;
  212. pdc_wdt->wdt_dev.parent = dev;
  213. watchdog_set_drvdata(&pdc_wdt->wdt_dev, pdc_wdt);
  214. watchdog_init_timeout(&pdc_wdt->wdt_dev, heartbeat, dev);
  215. pdc_wdt_stop(&pdc_wdt->wdt_dev);
  216. /* Find what caused the last reset */
  217. val = readl(pdc_wdt->base + PDC_WDT_TICKLE1);
  218. val = (val & PDC_WDT_TICKLE_STATUS_MASK) >> PDC_WDT_TICKLE_STATUS_SHIFT;
  219. switch (val) {
  220. case PDC_WDT_TICKLE_STATUS_TICKLE:
  221. case PDC_WDT_TICKLE_STATUS_TIMEOUT:
  222. pdc_wdt->wdt_dev.bootstatus |= WDIOF_CARDRESET;
  223. dev_info(dev, "watchdog module last reset due to timeout\n");
  224. break;
  225. case PDC_WDT_TICKLE_STATUS_HRESET:
  226. dev_info(dev,
  227. "watchdog module last reset due to hard reset\n");
  228. break;
  229. case PDC_WDT_TICKLE_STATUS_SRESET:
  230. dev_info(dev,
  231. "watchdog module last reset due to soft reset\n");
  232. break;
  233. case PDC_WDT_TICKLE_STATUS_USER:
  234. dev_info(dev,
  235. "watchdog module last reset due to user reset\n");
  236. break;
  237. default:
  238. dev_info(dev, "contains an illegal status code (%08x)\n", val);
  239. break;
  240. }
  241. watchdog_set_nowayout(&pdc_wdt->wdt_dev, nowayout);
  242. watchdog_set_restart_priority(&pdc_wdt->wdt_dev, 128);
  243. platform_set_drvdata(pdev, pdc_wdt);
  244. watchdog_stop_on_reboot(&pdc_wdt->wdt_dev);
  245. watchdog_stop_on_unregister(&pdc_wdt->wdt_dev);
  246. return devm_watchdog_register_device(dev, &pdc_wdt->wdt_dev);
  247. }
  248. static const struct of_device_id pdc_wdt_match[] = {
  249. { .compatible = "img,pdc-wdt" },
  250. {}
  251. };
  252. MODULE_DEVICE_TABLE(of, pdc_wdt_match);
  253. static struct platform_driver pdc_wdt_driver = {
  254. .driver = {
  255. .name = "imgpdc-wdt",
  256. .of_match_table = pdc_wdt_match,
  257. },
  258. .probe = pdc_wdt_probe,
  259. };
  260. module_platform_driver(pdc_wdt_driver);
  261. MODULE_AUTHOR("Jude Abraham <Jude.Abraham@imgtec.com>");
  262. MODULE_AUTHOR("Naidu Tellapati <Naidu.Tellapati@imgtec.com>");
  263. MODULE_DESCRIPTION("Imagination Technologies PDC Watchdog Timer Driver");
  264. MODULE_LICENSE("GPL v2");