f71808e_wdt.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /***************************************************************************
  3. * Copyright (C) 2006 by Hans Edgington <hans@edgington.nl> *
  4. * Copyright (C) 2007-2009 Hans de Goede <hdegoede@redhat.com> *
  5. * Copyright (C) 2010 Giel van Schijndel <me@mortis.eu> *
  6. * *
  7. ***************************************************************************/
  8. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  9. #include <linux/err.h>
  10. #include <linux/fs.h>
  11. #include <linux/init.h>
  12. #include <linux/io.h>
  13. #include <linux/ioport.h>
  14. #include <linux/miscdevice.h>
  15. #include <linux/module.h>
  16. #include <linux/mutex.h>
  17. #include <linux/notifier.h>
  18. #include <linux/reboot.h>
  19. #include <linux/uaccess.h>
  20. #include <linux/watchdog.h>
  21. #define DRVNAME "f71808e_wdt"
  22. #define SIO_F71808FG_LD_WDT 0x07 /* Watchdog timer logical device */
  23. #define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
  24. #define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
  25. #define SIO_REG_LDSEL 0x07 /* Logical device select */
  26. #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
  27. #define SIO_REG_DEVREV 0x22 /* Device revision */
  28. #define SIO_REG_MANID 0x23 /* Fintek ID (2 bytes) */
  29. #define SIO_REG_CLOCK_SEL 0x26 /* Clock select */
  30. #define SIO_REG_ROM_ADDR_SEL 0x27 /* ROM address select */
  31. #define SIO_F81866_REG_PORT_SEL 0x27 /* F81866 Multi-Function Register */
  32. #define SIO_REG_TSI_LEVEL_SEL 0x28 /* TSI Level select */
  33. #define SIO_REG_MFUNCT1 0x29 /* Multi function select 1 */
  34. #define SIO_REG_MFUNCT2 0x2a /* Multi function select 2 */
  35. #define SIO_REG_MFUNCT3 0x2b /* Multi function select 3 */
  36. #define SIO_F81866_REG_GPIO1 0x2c /* F81866 GPIO1 Enable Register */
  37. #define SIO_REG_ENABLE 0x30 /* Logical device enable */
  38. #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
  39. #define SIO_FINTEK_ID 0x1934 /* Manufacturers ID */
  40. #define SIO_F71808_ID 0x0901 /* Chipset ID */
  41. #define SIO_F71858_ID 0x0507 /* Chipset ID */
  42. #define SIO_F71862_ID 0x0601 /* Chipset ID */
  43. #define SIO_F71868_ID 0x1106 /* Chipset ID */
  44. #define SIO_F71869_ID 0x0814 /* Chipset ID */
  45. #define SIO_F71869A_ID 0x1007 /* Chipset ID */
  46. #define SIO_F71882_ID 0x0541 /* Chipset ID */
  47. #define SIO_F71889_ID 0x0723 /* Chipset ID */
  48. #define SIO_F81803_ID 0x1210 /* Chipset ID */
  49. #define SIO_F81865_ID 0x0704 /* Chipset ID */
  50. #define SIO_F81866_ID 0x1010 /* Chipset ID */
  51. #define F71808FG_REG_WDO_CONF 0xf0
  52. #define F71808FG_REG_WDT_CONF 0xf5
  53. #define F71808FG_REG_WD_TIME 0xf6
  54. #define F71808FG_FLAG_WDOUT_EN 7
  55. #define F71808FG_FLAG_WDTMOUT_STS 6
  56. #define F71808FG_FLAG_WD_EN 5
  57. #define F71808FG_FLAG_WD_PULSE 4
  58. #define F71808FG_FLAG_WD_UNIT 3
  59. #define F81865_REG_WDO_CONF 0xfa
  60. #define F81865_FLAG_WDOUT_EN 0
  61. /* Default values */
  62. #define WATCHDOG_TIMEOUT 60 /* 1 minute default timeout */
  63. #define WATCHDOG_MAX_TIMEOUT (60 * 255)
  64. #define WATCHDOG_PULSE_WIDTH 125 /* 125 ms, default pulse width for
  65. watchdog signal */
  66. #define WATCHDOG_F71862FG_PIN 63 /* default watchdog reset output
  67. pin number 63 */
  68. static unsigned short force_id;
  69. module_param(force_id, ushort, 0);
  70. MODULE_PARM_DESC(force_id, "Override the detected device ID");
  71. static const int max_timeout = WATCHDOG_MAX_TIMEOUT;
  72. static int timeout = WATCHDOG_TIMEOUT; /* default timeout in seconds */
  73. module_param(timeout, int, 0);
  74. MODULE_PARM_DESC(timeout,
  75. "Watchdog timeout in seconds. 1<= timeout <="
  76. __MODULE_STRING(WATCHDOG_MAX_TIMEOUT) " (default="
  77. __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
  78. static unsigned int pulse_width = WATCHDOG_PULSE_WIDTH;
  79. module_param(pulse_width, uint, 0);
  80. MODULE_PARM_DESC(pulse_width,
  81. "Watchdog signal pulse width. 0(=level), 1, 25, 30, 125, 150, 5000 or 6000 ms"
  82. " (default=" __MODULE_STRING(WATCHDOG_PULSE_WIDTH) ")");
  83. static unsigned int f71862fg_pin = WATCHDOG_F71862FG_PIN;
  84. module_param(f71862fg_pin, uint, 0);
  85. MODULE_PARM_DESC(f71862fg_pin,
  86. "Watchdog f71862fg reset output pin configuration. Choose pin 56 or 63"
  87. " (default=" __MODULE_STRING(WATCHDOG_F71862FG_PIN)")");
  88. static bool nowayout = WATCHDOG_NOWAYOUT;
  89. module_param(nowayout, bool, 0444);
  90. MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close");
  91. static unsigned int start_withtimeout;
  92. module_param(start_withtimeout, uint, 0);
  93. MODULE_PARM_DESC(start_withtimeout, "Start watchdog timer on module load with"
  94. " given initial timeout. Zero (default) disables this feature.");
  95. enum chips { f71808fg, f71858fg, f71862fg, f71868, f71869, f71882fg, f71889fg,
  96. f81803, f81865, f81866};
  97. static const char *f71808e_names[] = {
  98. "f71808fg",
  99. "f71858fg",
  100. "f71862fg",
  101. "f71868",
  102. "f71869",
  103. "f71882fg",
  104. "f71889fg",
  105. "f81803",
  106. "f81865",
  107. "f81866",
  108. };
  109. /* Super-I/O Function prototypes */
  110. static inline int superio_inb(int base, int reg);
  111. static inline int superio_inw(int base, int reg);
  112. static inline void superio_outb(int base, int reg, u8 val);
  113. static inline void superio_set_bit(int base, int reg, int bit);
  114. static inline void superio_clear_bit(int base, int reg, int bit);
  115. static inline int superio_enter(int base);
  116. static inline void superio_select(int base, int ld);
  117. static inline void superio_exit(int base);
  118. struct watchdog_data {
  119. unsigned short sioaddr;
  120. enum chips type;
  121. unsigned long opened;
  122. struct mutex lock;
  123. char expect_close;
  124. struct watchdog_info ident;
  125. unsigned short timeout;
  126. u8 timer_val; /* content for the wd_time register */
  127. char minutes_mode;
  128. u8 pulse_val; /* pulse width flag */
  129. char pulse_mode; /* enable pulse output mode? */
  130. char caused_reboot; /* last reboot was by the watchdog */
  131. };
  132. static struct watchdog_data watchdog = {
  133. .lock = __MUTEX_INITIALIZER(watchdog.lock),
  134. };
  135. /* Super I/O functions */
  136. static inline int superio_inb(int base, int reg)
  137. {
  138. outb(reg, base);
  139. return inb(base + 1);
  140. }
  141. static int superio_inw(int base, int reg)
  142. {
  143. int val;
  144. val = superio_inb(base, reg) << 8;
  145. val |= superio_inb(base, reg + 1);
  146. return val;
  147. }
  148. static inline void superio_outb(int base, int reg, u8 val)
  149. {
  150. outb(reg, base);
  151. outb(val, base + 1);
  152. }
  153. static inline void superio_set_bit(int base, int reg, int bit)
  154. {
  155. unsigned long val = superio_inb(base, reg);
  156. __set_bit(bit, &val);
  157. superio_outb(base, reg, val);
  158. }
  159. static inline void superio_clear_bit(int base, int reg, int bit)
  160. {
  161. unsigned long val = superio_inb(base, reg);
  162. __clear_bit(bit, &val);
  163. superio_outb(base, reg, val);
  164. }
  165. static inline int superio_enter(int base)
  166. {
  167. /* Don't step on other drivers' I/O space by accident */
  168. if (!request_muxed_region(base, 2, DRVNAME)) {
  169. pr_err("I/O address 0x%04x already in use\n", (int)base);
  170. return -EBUSY;
  171. }
  172. /* according to the datasheet the key must be sent twice! */
  173. outb(SIO_UNLOCK_KEY, base);
  174. outb(SIO_UNLOCK_KEY, base);
  175. return 0;
  176. }
  177. static inline void superio_select(int base, int ld)
  178. {
  179. outb(SIO_REG_LDSEL, base);
  180. outb(ld, base + 1);
  181. }
  182. static inline void superio_exit(int base)
  183. {
  184. outb(SIO_LOCK_KEY, base);
  185. release_region(base, 2);
  186. }
  187. static int watchdog_set_timeout(int timeout)
  188. {
  189. if (timeout <= 0
  190. || timeout > max_timeout) {
  191. pr_err("watchdog timeout out of range\n");
  192. return -EINVAL;
  193. }
  194. mutex_lock(&watchdog.lock);
  195. if (timeout > 0xff) {
  196. watchdog.timer_val = DIV_ROUND_UP(timeout, 60);
  197. watchdog.minutes_mode = true;
  198. timeout = watchdog.timer_val * 60;
  199. } else {
  200. watchdog.timer_val = timeout;
  201. watchdog.minutes_mode = false;
  202. }
  203. watchdog.timeout = timeout;
  204. mutex_unlock(&watchdog.lock);
  205. return 0;
  206. }
  207. static int watchdog_set_pulse_width(unsigned int pw)
  208. {
  209. int err = 0;
  210. unsigned int t1 = 25, t2 = 125, t3 = 5000;
  211. if (watchdog.type == f71868) {
  212. t1 = 30;
  213. t2 = 150;
  214. t3 = 6000;
  215. }
  216. mutex_lock(&watchdog.lock);
  217. if (pw <= 1) {
  218. watchdog.pulse_val = 0;
  219. } else if (pw <= t1) {
  220. watchdog.pulse_val = 1;
  221. } else if (pw <= t2) {
  222. watchdog.pulse_val = 2;
  223. } else if (pw <= t3) {
  224. watchdog.pulse_val = 3;
  225. } else {
  226. pr_err("pulse width out of range\n");
  227. err = -EINVAL;
  228. goto exit_unlock;
  229. }
  230. watchdog.pulse_mode = pw;
  231. exit_unlock:
  232. mutex_unlock(&watchdog.lock);
  233. return err;
  234. }
  235. static int watchdog_keepalive(void)
  236. {
  237. int err = 0;
  238. mutex_lock(&watchdog.lock);
  239. err = superio_enter(watchdog.sioaddr);
  240. if (err)
  241. goto exit_unlock;
  242. superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
  243. if (watchdog.minutes_mode)
  244. /* select minutes for timer units */
  245. superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
  246. F71808FG_FLAG_WD_UNIT);
  247. else
  248. /* select seconds for timer units */
  249. superio_clear_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
  250. F71808FG_FLAG_WD_UNIT);
  251. /* Set timer value */
  252. superio_outb(watchdog.sioaddr, F71808FG_REG_WD_TIME,
  253. watchdog.timer_val);
  254. superio_exit(watchdog.sioaddr);
  255. exit_unlock:
  256. mutex_unlock(&watchdog.lock);
  257. return err;
  258. }
  259. static int watchdog_start(void)
  260. {
  261. int err;
  262. u8 tmp;
  263. /* Make sure we don't die as soon as the watchdog is enabled below */
  264. err = watchdog_keepalive();
  265. if (err)
  266. return err;
  267. mutex_lock(&watchdog.lock);
  268. err = superio_enter(watchdog.sioaddr);
  269. if (err)
  270. goto exit_unlock;
  271. superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
  272. /* Watchdog pin configuration */
  273. switch (watchdog.type) {
  274. case f71808fg:
  275. /* Set pin 21 to GPIO23/WDTRST#, then to WDTRST# */
  276. superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT2, 3);
  277. superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT3, 3);
  278. break;
  279. case f71862fg:
  280. if (f71862fg_pin == 63) {
  281. /* SPI must be disabled first to use this pin! */
  282. superio_clear_bit(watchdog.sioaddr, SIO_REG_ROM_ADDR_SEL, 6);
  283. superio_set_bit(watchdog.sioaddr, SIO_REG_MFUNCT3, 4);
  284. } else if (f71862fg_pin == 56) {
  285. superio_set_bit(watchdog.sioaddr, SIO_REG_MFUNCT1, 1);
  286. }
  287. break;
  288. case f71868:
  289. case f71869:
  290. /* GPIO14 --> WDTRST# */
  291. superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT1, 4);
  292. break;
  293. case f71882fg:
  294. /* Set pin 56 to WDTRST# */
  295. superio_set_bit(watchdog.sioaddr, SIO_REG_MFUNCT1, 1);
  296. break;
  297. case f71889fg:
  298. /* set pin 40 to WDTRST# */
  299. superio_outb(watchdog.sioaddr, SIO_REG_MFUNCT3,
  300. superio_inb(watchdog.sioaddr, SIO_REG_MFUNCT3) & 0xcf);
  301. break;
  302. case f81803:
  303. /* Enable TSI Level register bank */
  304. superio_clear_bit(watchdog.sioaddr, SIO_REG_CLOCK_SEL, 3);
  305. /* Set pin 27 to WDTRST# */
  306. superio_outb(watchdog.sioaddr, SIO_REG_TSI_LEVEL_SEL, 0x5f &
  307. superio_inb(watchdog.sioaddr, SIO_REG_TSI_LEVEL_SEL));
  308. break;
  309. case f81865:
  310. /* Set pin 70 to WDTRST# */
  311. superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT3, 5);
  312. break;
  313. case f81866:
  314. /*
  315. * GPIO1 Control Register when 27h BIT3:2 = 01 & BIT0 = 0.
  316. * The PIN 70(GPIO15/WDTRST) is controlled by 2Ch:
  317. * BIT5: 0 -> WDTRST#
  318. * 1 -> GPIO15
  319. */
  320. tmp = superio_inb(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL);
  321. tmp &= ~(BIT(3) | BIT(0));
  322. tmp |= BIT(2);
  323. superio_outb(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL, tmp);
  324. superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_GPIO1, 5);
  325. break;
  326. default:
  327. /*
  328. * 'default' label to shut up the compiler and catch
  329. * programmer errors
  330. */
  331. err = -ENODEV;
  332. goto exit_superio;
  333. }
  334. superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
  335. superio_set_bit(watchdog.sioaddr, SIO_REG_ENABLE, 0);
  336. if (watchdog.type == f81865 || watchdog.type == f81866)
  337. superio_set_bit(watchdog.sioaddr, F81865_REG_WDO_CONF,
  338. F81865_FLAG_WDOUT_EN);
  339. else
  340. superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDO_CONF,
  341. F71808FG_FLAG_WDOUT_EN);
  342. superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
  343. F71808FG_FLAG_WD_EN);
  344. if (watchdog.pulse_mode) {
  345. /* Select "pulse" output mode with given duration */
  346. u8 wdt_conf = superio_inb(watchdog.sioaddr,
  347. F71808FG_REG_WDT_CONF);
  348. /* Set WD_PSWIDTH bits (1:0) */
  349. wdt_conf = (wdt_conf & 0xfc) | (watchdog.pulse_val & 0x03);
  350. /* Set WD_PULSE to "pulse" mode */
  351. wdt_conf |= BIT(F71808FG_FLAG_WD_PULSE);
  352. superio_outb(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
  353. wdt_conf);
  354. } else {
  355. /* Select "level" output mode */
  356. superio_clear_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
  357. F71808FG_FLAG_WD_PULSE);
  358. }
  359. exit_superio:
  360. superio_exit(watchdog.sioaddr);
  361. exit_unlock:
  362. mutex_unlock(&watchdog.lock);
  363. return err;
  364. }
  365. static int watchdog_stop(void)
  366. {
  367. int err = 0;
  368. mutex_lock(&watchdog.lock);
  369. err = superio_enter(watchdog.sioaddr);
  370. if (err)
  371. goto exit_unlock;
  372. superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
  373. superio_clear_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
  374. F71808FG_FLAG_WD_EN);
  375. superio_exit(watchdog.sioaddr);
  376. exit_unlock:
  377. mutex_unlock(&watchdog.lock);
  378. return err;
  379. }
  380. static int watchdog_get_status(void)
  381. {
  382. int status = 0;
  383. mutex_lock(&watchdog.lock);
  384. status = (watchdog.caused_reboot) ? WDIOF_CARDRESET : 0;
  385. mutex_unlock(&watchdog.lock);
  386. return status;
  387. }
  388. static bool watchdog_is_running(void)
  389. {
  390. /*
  391. * if we fail to determine the watchdog's status assume it to be
  392. * running to be on the safe side
  393. */
  394. bool is_running = true;
  395. mutex_lock(&watchdog.lock);
  396. if (superio_enter(watchdog.sioaddr))
  397. goto exit_unlock;
  398. superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
  399. is_running = (superio_inb(watchdog.sioaddr, SIO_REG_ENABLE) & BIT(0))
  400. && (superio_inb(watchdog.sioaddr, F71808FG_REG_WDT_CONF)
  401. & BIT(F71808FG_FLAG_WD_EN));
  402. superio_exit(watchdog.sioaddr);
  403. exit_unlock:
  404. mutex_unlock(&watchdog.lock);
  405. return is_running;
  406. }
  407. /* /dev/watchdog api */
  408. static int watchdog_open(struct inode *inode, struct file *file)
  409. {
  410. int err;
  411. /* If the watchdog is alive we don't need to start it again */
  412. if (test_and_set_bit(0, &watchdog.opened))
  413. return -EBUSY;
  414. err = watchdog_start();
  415. if (err) {
  416. clear_bit(0, &watchdog.opened);
  417. return err;
  418. }
  419. if (nowayout)
  420. __module_get(THIS_MODULE);
  421. watchdog.expect_close = 0;
  422. return stream_open(inode, file);
  423. }
  424. static int watchdog_release(struct inode *inode, struct file *file)
  425. {
  426. clear_bit(0, &watchdog.opened);
  427. if (!watchdog.expect_close) {
  428. watchdog_keepalive();
  429. pr_crit("Unexpected close, not stopping watchdog!\n");
  430. } else if (!nowayout) {
  431. watchdog_stop();
  432. }
  433. return 0;
  434. }
  435. /*
  436. * watchdog_write:
  437. * @file: file handle to the watchdog
  438. * @buf: buffer to write
  439. * @count: count of bytes
  440. * @ppos: pointer to the position to write. No seeks allowed
  441. *
  442. * A write to a watchdog device is defined as a keepalive signal. Any
  443. * write of data will do, as we we don't define content meaning.
  444. */
  445. static ssize_t watchdog_write(struct file *file, const char __user *buf,
  446. size_t count, loff_t *ppos)
  447. {
  448. if (count) {
  449. if (!nowayout) {
  450. size_t i;
  451. /* In case it was set long ago */
  452. bool expect_close = false;
  453. for (i = 0; i != count; i++) {
  454. char c;
  455. if (get_user(c, buf + i))
  456. return -EFAULT;
  457. if (c == 'V')
  458. expect_close = true;
  459. }
  460. /* Properly order writes across fork()ed processes */
  461. mutex_lock(&watchdog.lock);
  462. watchdog.expect_close = expect_close;
  463. mutex_unlock(&watchdog.lock);
  464. }
  465. /* someone wrote to us, we should restart timer */
  466. watchdog_keepalive();
  467. }
  468. return count;
  469. }
  470. /*
  471. * watchdog_ioctl:
  472. * @inode: inode of the device
  473. * @file: file handle to the device
  474. * @cmd: watchdog command
  475. * @arg: argument pointer
  476. *
  477. * The watchdog API defines a common set of functions for all watchdogs
  478. * according to their available features.
  479. */
  480. static long watchdog_ioctl(struct file *file, unsigned int cmd,
  481. unsigned long arg)
  482. {
  483. int status;
  484. int new_options;
  485. int new_timeout;
  486. union {
  487. struct watchdog_info __user *ident;
  488. int __user *i;
  489. } uarg;
  490. uarg.i = (int __user *)arg;
  491. switch (cmd) {
  492. case WDIOC_GETSUPPORT:
  493. return copy_to_user(uarg.ident, &watchdog.ident,
  494. sizeof(watchdog.ident)) ? -EFAULT : 0;
  495. case WDIOC_GETSTATUS:
  496. status = watchdog_get_status();
  497. if (status < 0)
  498. return status;
  499. return put_user(status, uarg.i);
  500. case WDIOC_GETBOOTSTATUS:
  501. return put_user(0, uarg.i);
  502. case WDIOC_SETOPTIONS:
  503. if (get_user(new_options, uarg.i))
  504. return -EFAULT;
  505. if (new_options & WDIOS_DISABLECARD)
  506. watchdog_stop();
  507. if (new_options & WDIOS_ENABLECARD)
  508. return watchdog_start();
  509. fallthrough;
  510. case WDIOC_KEEPALIVE:
  511. watchdog_keepalive();
  512. return 0;
  513. case WDIOC_SETTIMEOUT:
  514. if (get_user(new_timeout, uarg.i))
  515. return -EFAULT;
  516. if (watchdog_set_timeout(new_timeout))
  517. return -EINVAL;
  518. watchdog_keepalive();
  519. fallthrough;
  520. case WDIOC_GETTIMEOUT:
  521. return put_user(watchdog.timeout, uarg.i);
  522. default:
  523. return -ENOTTY;
  524. }
  525. }
  526. static int watchdog_notify_sys(struct notifier_block *this, unsigned long code,
  527. void *unused)
  528. {
  529. if (code == SYS_DOWN || code == SYS_HALT)
  530. watchdog_stop();
  531. return NOTIFY_DONE;
  532. }
  533. static const struct file_operations watchdog_fops = {
  534. .owner = THIS_MODULE,
  535. .llseek = no_llseek,
  536. .open = watchdog_open,
  537. .release = watchdog_release,
  538. .write = watchdog_write,
  539. .unlocked_ioctl = watchdog_ioctl,
  540. .compat_ioctl = compat_ptr_ioctl,
  541. };
  542. static struct miscdevice watchdog_miscdev = {
  543. .minor = WATCHDOG_MINOR,
  544. .name = "watchdog",
  545. .fops = &watchdog_fops,
  546. };
  547. static struct notifier_block watchdog_notifier = {
  548. .notifier_call = watchdog_notify_sys,
  549. };
  550. static int __init watchdog_init(int sioaddr)
  551. {
  552. int wdt_conf, err = 0;
  553. /* No need to lock watchdog.lock here because no entry points
  554. * into the module have been registered yet.
  555. */
  556. watchdog.sioaddr = sioaddr;
  557. watchdog.ident.options = WDIOF_MAGICCLOSE
  558. | WDIOF_KEEPALIVEPING
  559. | WDIOF_CARDRESET;
  560. snprintf(watchdog.ident.identity,
  561. sizeof(watchdog.ident.identity), "%s watchdog",
  562. f71808e_names[watchdog.type]);
  563. err = superio_enter(sioaddr);
  564. if (err)
  565. return err;
  566. superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
  567. wdt_conf = superio_inb(sioaddr, F71808FG_REG_WDT_CONF);
  568. watchdog.caused_reboot = wdt_conf & BIT(F71808FG_FLAG_WDTMOUT_STS);
  569. /*
  570. * We don't want WDTMOUT_STS to stick around till regular reboot.
  571. * Write 1 to the bit to clear it to zero.
  572. */
  573. superio_outb(sioaddr, F71808FG_REG_WDT_CONF,
  574. wdt_conf | BIT(F71808FG_FLAG_WDTMOUT_STS));
  575. superio_exit(sioaddr);
  576. err = watchdog_set_timeout(timeout);
  577. if (err)
  578. return err;
  579. err = watchdog_set_pulse_width(pulse_width);
  580. if (err)
  581. return err;
  582. err = register_reboot_notifier(&watchdog_notifier);
  583. if (err)
  584. return err;
  585. err = misc_register(&watchdog_miscdev);
  586. if (err) {
  587. pr_err("cannot register miscdev on minor=%d\n",
  588. watchdog_miscdev.minor);
  589. goto exit_reboot;
  590. }
  591. if (start_withtimeout) {
  592. if (start_withtimeout <= 0
  593. || start_withtimeout > max_timeout) {
  594. pr_err("starting timeout out of range\n");
  595. err = -EINVAL;
  596. goto exit_miscdev;
  597. }
  598. err = watchdog_start();
  599. if (err) {
  600. pr_err("cannot start watchdog timer\n");
  601. goto exit_miscdev;
  602. }
  603. mutex_lock(&watchdog.lock);
  604. err = superio_enter(sioaddr);
  605. if (err)
  606. goto exit_unlock;
  607. superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
  608. if (start_withtimeout > 0xff) {
  609. /* select minutes for timer units */
  610. superio_set_bit(sioaddr, F71808FG_REG_WDT_CONF,
  611. F71808FG_FLAG_WD_UNIT);
  612. superio_outb(sioaddr, F71808FG_REG_WD_TIME,
  613. DIV_ROUND_UP(start_withtimeout, 60));
  614. } else {
  615. /* select seconds for timer units */
  616. superio_clear_bit(sioaddr, F71808FG_REG_WDT_CONF,
  617. F71808FG_FLAG_WD_UNIT);
  618. superio_outb(sioaddr, F71808FG_REG_WD_TIME,
  619. start_withtimeout);
  620. }
  621. superio_exit(sioaddr);
  622. mutex_unlock(&watchdog.lock);
  623. if (nowayout)
  624. __module_get(THIS_MODULE);
  625. pr_info("watchdog started with initial timeout of %u sec\n",
  626. start_withtimeout);
  627. }
  628. return 0;
  629. exit_unlock:
  630. mutex_unlock(&watchdog.lock);
  631. exit_miscdev:
  632. misc_deregister(&watchdog_miscdev);
  633. exit_reboot:
  634. unregister_reboot_notifier(&watchdog_notifier);
  635. return err;
  636. }
  637. static int __init f71808e_find(int sioaddr)
  638. {
  639. u16 devid;
  640. int err = superio_enter(sioaddr);
  641. if (err)
  642. return err;
  643. devid = superio_inw(sioaddr, SIO_REG_MANID);
  644. if (devid != SIO_FINTEK_ID) {
  645. pr_debug("Not a Fintek device\n");
  646. err = -ENODEV;
  647. goto exit;
  648. }
  649. devid = force_id ? force_id : superio_inw(sioaddr, SIO_REG_DEVID);
  650. switch (devid) {
  651. case SIO_F71808_ID:
  652. watchdog.type = f71808fg;
  653. break;
  654. case SIO_F71862_ID:
  655. watchdog.type = f71862fg;
  656. break;
  657. case SIO_F71868_ID:
  658. watchdog.type = f71868;
  659. break;
  660. case SIO_F71869_ID:
  661. case SIO_F71869A_ID:
  662. watchdog.type = f71869;
  663. break;
  664. case SIO_F71882_ID:
  665. watchdog.type = f71882fg;
  666. break;
  667. case SIO_F71889_ID:
  668. watchdog.type = f71889fg;
  669. break;
  670. case SIO_F71858_ID:
  671. /* Confirmed (by datasheet) not to have a watchdog. */
  672. err = -ENODEV;
  673. goto exit;
  674. case SIO_F81803_ID:
  675. watchdog.type = f81803;
  676. break;
  677. case SIO_F81865_ID:
  678. watchdog.type = f81865;
  679. break;
  680. case SIO_F81866_ID:
  681. watchdog.type = f81866;
  682. break;
  683. default:
  684. pr_info("Unrecognized Fintek device: %04x\n",
  685. (unsigned int)devid);
  686. err = -ENODEV;
  687. goto exit;
  688. }
  689. pr_info("Found %s watchdog chip, revision %d\n",
  690. f71808e_names[watchdog.type],
  691. (int)superio_inb(sioaddr, SIO_REG_DEVREV));
  692. exit:
  693. superio_exit(sioaddr);
  694. return err;
  695. }
  696. static int __init f71808e_init(void)
  697. {
  698. static const unsigned short addrs[] = { 0x2e, 0x4e };
  699. int err = -ENODEV;
  700. int i;
  701. if (f71862fg_pin != 63 && f71862fg_pin != 56) {
  702. pr_err("Invalid argument f71862fg_pin=%d\n", f71862fg_pin);
  703. return -EINVAL;
  704. }
  705. for (i = 0; i < ARRAY_SIZE(addrs); i++) {
  706. err = f71808e_find(addrs[i]);
  707. if (err == 0)
  708. break;
  709. }
  710. if (i == ARRAY_SIZE(addrs))
  711. return err;
  712. return watchdog_init(addrs[i]);
  713. }
  714. static void __exit f71808e_exit(void)
  715. {
  716. if (watchdog_is_running()) {
  717. pr_warn("Watchdog timer still running, stopping it\n");
  718. watchdog_stop();
  719. }
  720. misc_deregister(&watchdog_miscdev);
  721. unregister_reboot_notifier(&watchdog_notifier);
  722. }
  723. MODULE_DESCRIPTION("F71808E Watchdog Driver");
  724. MODULE_AUTHOR("Giel van Schijndel <me@mortis.eu>");
  725. MODULE_LICENSE("GPL");
  726. module_init(f71808e_init);
  727. module_exit(f71808e_exit);