at91sam9_wdt.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Watchdog driver for Atmel AT91SAM9x processors.
  4. *
  5. * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
  6. *
  7. */
  8. /*
  9. * The Watchdog Timer Mode Register can be only written to once. If the
  10. * timeout need to be set from Linux, be sure that the bootstrap or the
  11. * bootloader doesn't write to this register.
  12. */
  13. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14. #include <linux/clk.h>
  15. #include <linux/errno.h>
  16. #include <linux/init.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/io.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/moduleparam.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/reboot.h>
  24. #include <linux/types.h>
  25. #include <linux/watchdog.h>
  26. #include <linux/jiffies.h>
  27. #include <linux/timer.h>
  28. #include <linux/bitops.h>
  29. #include <linux/uaccess.h>
  30. #include <linux/of.h>
  31. #include <linux/of_irq.h>
  32. #include "at91sam9_wdt.h"
  33. #define DRV_NAME "AT91SAM9 Watchdog"
  34. #define wdt_read(wdt, field) \
  35. readl_relaxed((wdt)->base + (field))
  36. #define wdt_write(wtd, field, val) \
  37. writel_relaxed((val), (wdt)->base + (field))
  38. /* AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
  39. * use this to convert a watchdog
  40. * value from/to milliseconds.
  41. */
  42. #define ticks_to_hz_rounddown(t) ((((t) + 1) * HZ) >> 8)
  43. #define ticks_to_hz_roundup(t) (((((t) + 1) * HZ) + 255) >> 8)
  44. #define ticks_to_secs(t) (((t) + 1) >> 8)
  45. #define secs_to_ticks(s) ((s) ? (((s) << 8) - 1) : 0)
  46. #define WDT_MR_RESET 0x3FFF2FFF
  47. /* Watchdog max counter value in ticks */
  48. #define WDT_COUNTER_MAX_TICKS 0xFFF
  49. /* Watchdog max delta/value in secs */
  50. #define WDT_COUNTER_MAX_SECS ticks_to_secs(WDT_COUNTER_MAX_TICKS)
  51. /* Hardware timeout in seconds */
  52. #define WDT_HW_TIMEOUT 2
  53. /* Timer heartbeat (500ms) */
  54. #define WDT_TIMEOUT (HZ/2)
  55. /* User land timeout */
  56. #define WDT_HEARTBEAT 15
  57. static int heartbeat;
  58. module_param(heartbeat, int, 0);
  59. MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds. "
  60. "(default = " __MODULE_STRING(WDT_HEARTBEAT) ")");
  61. static bool nowayout = WATCHDOG_NOWAYOUT;
  62. module_param(nowayout, bool, 0);
  63. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
  64. "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  65. #define to_wdt(wdd) container_of(wdd, struct at91wdt, wdd)
  66. struct at91wdt {
  67. struct watchdog_device wdd;
  68. void __iomem *base;
  69. unsigned long next_heartbeat; /* the next_heartbeat for the timer */
  70. struct timer_list timer; /* The timer that pings the watchdog */
  71. u32 mr;
  72. u32 mr_mask;
  73. unsigned long heartbeat; /* WDT heartbeat in jiffies */
  74. bool nowayout;
  75. unsigned int irq;
  76. struct clk *sclk;
  77. };
  78. /* ......................................................................... */
  79. static irqreturn_t wdt_interrupt(int irq, void *dev_id)
  80. {
  81. struct at91wdt *wdt = (struct at91wdt *)dev_id;
  82. if (wdt_read(wdt, AT91_WDT_SR)) {
  83. pr_crit("at91sam9 WDT software reset\n");
  84. emergency_restart();
  85. pr_crit("Reboot didn't ?????\n");
  86. }
  87. return IRQ_HANDLED;
  88. }
  89. /*
  90. * Reload the watchdog timer. (ie, pat the watchdog)
  91. */
  92. static inline void at91_wdt_reset(struct at91wdt *wdt)
  93. {
  94. wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
  95. }
  96. /*
  97. * Timer tick
  98. */
  99. static void at91_ping(struct timer_list *t)
  100. {
  101. struct at91wdt *wdt = from_timer(wdt, t, timer);
  102. if (time_before(jiffies, wdt->next_heartbeat) ||
  103. !watchdog_active(&wdt->wdd)) {
  104. at91_wdt_reset(wdt);
  105. mod_timer(&wdt->timer, jiffies + wdt->heartbeat);
  106. } else {
  107. pr_crit("I will reset your machine !\n");
  108. }
  109. }
  110. static int at91_wdt_start(struct watchdog_device *wdd)
  111. {
  112. struct at91wdt *wdt = to_wdt(wdd);
  113. /* calculate when the next userspace timeout will be */
  114. wdt->next_heartbeat = jiffies + wdd->timeout * HZ;
  115. return 0;
  116. }
  117. static int at91_wdt_stop(struct watchdog_device *wdd)
  118. {
  119. /* The watchdog timer hardware can not be stopped... */
  120. return 0;
  121. }
  122. static int at91_wdt_set_timeout(struct watchdog_device *wdd, unsigned int new_timeout)
  123. {
  124. wdd->timeout = new_timeout;
  125. return at91_wdt_start(wdd);
  126. }
  127. static int at91_wdt_init(struct platform_device *pdev, struct at91wdt *wdt)
  128. {
  129. u32 tmp;
  130. u32 delta;
  131. u32 value;
  132. int err;
  133. u32 mask = wdt->mr_mask;
  134. unsigned long min_heartbeat = 1;
  135. unsigned long max_heartbeat;
  136. struct device *dev = &pdev->dev;
  137. tmp = wdt_read(wdt, AT91_WDT_MR);
  138. if ((tmp & mask) != (wdt->mr & mask)) {
  139. if (tmp == WDT_MR_RESET) {
  140. wdt_write(wdt, AT91_WDT_MR, wdt->mr);
  141. tmp = wdt_read(wdt, AT91_WDT_MR);
  142. }
  143. }
  144. if (tmp & AT91_WDT_WDDIS) {
  145. if (wdt->mr & AT91_WDT_WDDIS)
  146. return 0;
  147. dev_err(dev, "watchdog is disabled\n");
  148. return -EINVAL;
  149. }
  150. value = tmp & AT91_WDT_WDV;
  151. delta = (tmp & AT91_WDT_WDD) >> 16;
  152. if (delta < value)
  153. min_heartbeat = ticks_to_hz_roundup(value - delta);
  154. max_heartbeat = ticks_to_hz_rounddown(value);
  155. if (!max_heartbeat) {
  156. dev_err(dev,
  157. "heartbeat is too small for the system to handle it correctly\n");
  158. return -EINVAL;
  159. }
  160. /*
  161. * Try to reset the watchdog counter 4 or 2 times more often than
  162. * actually requested, to avoid spurious watchdog reset.
  163. * If this is not possible because of the min_heartbeat value, reset
  164. * it at the min_heartbeat period.
  165. */
  166. if ((max_heartbeat / 4) >= min_heartbeat)
  167. wdt->heartbeat = max_heartbeat / 4;
  168. else if ((max_heartbeat / 2) >= min_heartbeat)
  169. wdt->heartbeat = max_heartbeat / 2;
  170. else
  171. wdt->heartbeat = min_heartbeat;
  172. if (max_heartbeat < min_heartbeat + 4)
  173. dev_warn(dev,
  174. "min heartbeat and max heartbeat might be too close for the system to handle it correctly\n");
  175. if ((tmp & AT91_WDT_WDFIEN) && wdt->irq) {
  176. err = request_irq(wdt->irq, wdt_interrupt,
  177. IRQF_SHARED | IRQF_IRQPOLL |
  178. IRQF_NO_SUSPEND,
  179. pdev->name, wdt);
  180. if (err)
  181. return err;
  182. }
  183. if ((tmp & wdt->mr_mask) != (wdt->mr & wdt->mr_mask))
  184. dev_warn(dev,
  185. "watchdog already configured differently (mr = %x expecting %x)\n",
  186. tmp & wdt->mr_mask, wdt->mr & wdt->mr_mask);
  187. timer_setup(&wdt->timer, at91_ping, 0);
  188. /*
  189. * Use min_heartbeat the first time to avoid spurious watchdog reset:
  190. * we don't know for how long the watchdog counter is running, and
  191. * - resetting it right now might trigger a watchdog fault reset
  192. * - waiting for heartbeat time might lead to a watchdog timeout
  193. * reset
  194. */
  195. mod_timer(&wdt->timer, jiffies + min_heartbeat);
  196. /* Try to set timeout from device tree first */
  197. if (watchdog_init_timeout(&wdt->wdd, 0, dev))
  198. watchdog_init_timeout(&wdt->wdd, heartbeat, dev);
  199. watchdog_set_nowayout(&wdt->wdd, wdt->nowayout);
  200. err = watchdog_register_device(&wdt->wdd);
  201. if (err)
  202. goto out_stop_timer;
  203. wdt->next_heartbeat = jiffies + wdt->wdd.timeout * HZ;
  204. return 0;
  205. out_stop_timer:
  206. del_timer(&wdt->timer);
  207. return err;
  208. }
  209. /* ......................................................................... */
  210. static const struct watchdog_info at91_wdt_info = {
  211. .identity = DRV_NAME,
  212. .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
  213. WDIOF_MAGICCLOSE,
  214. };
  215. static const struct watchdog_ops at91_wdt_ops = {
  216. .owner = THIS_MODULE,
  217. .start = at91_wdt_start,
  218. .stop = at91_wdt_stop,
  219. .set_timeout = at91_wdt_set_timeout,
  220. };
  221. #if defined(CONFIG_OF)
  222. static int of_at91wdt_init(struct device_node *np, struct at91wdt *wdt)
  223. {
  224. u32 min = 0;
  225. u32 max = WDT_COUNTER_MAX_SECS;
  226. const char *tmp;
  227. /* Get the interrupts property */
  228. wdt->irq = irq_of_parse_and_map(np, 0);
  229. if (!wdt->irq)
  230. dev_warn(wdt->wdd.parent, "failed to get IRQ from DT\n");
  231. if (!of_property_read_u32_index(np, "atmel,max-heartbeat-sec", 0,
  232. &max)) {
  233. if (!max || max > WDT_COUNTER_MAX_SECS)
  234. max = WDT_COUNTER_MAX_SECS;
  235. if (!of_property_read_u32_index(np, "atmel,min-heartbeat-sec",
  236. 0, &min)) {
  237. if (min >= max)
  238. min = max - 1;
  239. }
  240. }
  241. min = secs_to_ticks(min);
  242. max = secs_to_ticks(max);
  243. wdt->mr_mask = 0x3FFFFFFF;
  244. wdt->mr = 0;
  245. if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) &&
  246. !strcmp(tmp, "software")) {
  247. wdt->mr |= AT91_WDT_WDFIEN;
  248. wdt->mr_mask &= ~AT91_WDT_WDRPROC;
  249. } else {
  250. wdt->mr |= AT91_WDT_WDRSTEN;
  251. }
  252. if (!of_property_read_string(np, "atmel,reset-type", &tmp) &&
  253. !strcmp(tmp, "proc"))
  254. wdt->mr |= AT91_WDT_WDRPROC;
  255. if (of_property_read_bool(np, "atmel,disable")) {
  256. wdt->mr |= AT91_WDT_WDDIS;
  257. wdt->mr_mask &= AT91_WDT_WDDIS;
  258. }
  259. if (of_property_read_bool(np, "atmel,idle-halt"))
  260. wdt->mr |= AT91_WDT_WDIDLEHLT;
  261. if (of_property_read_bool(np, "atmel,dbg-halt"))
  262. wdt->mr |= AT91_WDT_WDDBGHLT;
  263. wdt->mr |= max | ((max - min) << 16);
  264. return 0;
  265. }
  266. #else
  267. static inline int of_at91wdt_init(struct device_node *np, struct at91wdt *wdt)
  268. {
  269. return 0;
  270. }
  271. #endif
  272. static int __init at91wdt_probe(struct platform_device *pdev)
  273. {
  274. int err;
  275. struct at91wdt *wdt;
  276. wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
  277. if (!wdt)
  278. return -ENOMEM;
  279. wdt->mr = (WDT_HW_TIMEOUT * 256) | AT91_WDT_WDRSTEN | AT91_WDT_WDD |
  280. AT91_WDT_WDDBGHLT | AT91_WDT_WDIDLEHLT;
  281. wdt->mr_mask = 0x3FFFFFFF;
  282. wdt->nowayout = nowayout;
  283. wdt->wdd.parent = &pdev->dev;
  284. wdt->wdd.info = &at91_wdt_info;
  285. wdt->wdd.ops = &at91_wdt_ops;
  286. wdt->wdd.timeout = WDT_HEARTBEAT;
  287. wdt->wdd.min_timeout = 1;
  288. wdt->wdd.max_timeout = 0xFFFF;
  289. wdt->base = devm_platform_ioremap_resource(pdev, 0);
  290. if (IS_ERR(wdt->base))
  291. return PTR_ERR(wdt->base);
  292. wdt->sclk = devm_clk_get(&pdev->dev, NULL);
  293. if (IS_ERR(wdt->sclk))
  294. return PTR_ERR(wdt->sclk);
  295. err = clk_prepare_enable(wdt->sclk);
  296. if (err) {
  297. dev_err(&pdev->dev, "Could not enable slow clock\n");
  298. return err;
  299. }
  300. if (pdev->dev.of_node) {
  301. err = of_at91wdt_init(pdev->dev.of_node, wdt);
  302. if (err)
  303. goto err_clk;
  304. }
  305. err = at91_wdt_init(pdev, wdt);
  306. if (err)
  307. goto err_clk;
  308. platform_set_drvdata(pdev, wdt);
  309. pr_info("enabled (heartbeat=%d sec, nowayout=%d)\n",
  310. wdt->wdd.timeout, wdt->nowayout);
  311. return 0;
  312. err_clk:
  313. clk_disable_unprepare(wdt->sclk);
  314. return err;
  315. }
  316. static int __exit at91wdt_remove(struct platform_device *pdev)
  317. {
  318. struct at91wdt *wdt = platform_get_drvdata(pdev);
  319. watchdog_unregister_device(&wdt->wdd);
  320. pr_warn("I quit now, hardware will probably reboot!\n");
  321. del_timer(&wdt->timer);
  322. clk_disable_unprepare(wdt->sclk);
  323. return 0;
  324. }
  325. #if defined(CONFIG_OF)
  326. static const struct of_device_id at91_wdt_dt_ids[] = {
  327. { .compatible = "atmel,at91sam9260-wdt" },
  328. { /* sentinel */ }
  329. };
  330. MODULE_DEVICE_TABLE(of, at91_wdt_dt_ids);
  331. #endif
  332. static struct platform_driver at91wdt_driver = {
  333. .remove = __exit_p(at91wdt_remove),
  334. .driver = {
  335. .name = "at91_wdt",
  336. .of_match_table = of_match_ptr(at91_wdt_dt_ids),
  337. },
  338. };
  339. module_platform_driver_probe(at91wdt_driver, at91wdt_probe);
  340. MODULE_AUTHOR("Renaud CERRATO <r.cerrato@til-technologies.fr>");
  341. MODULE_DESCRIPTION("Watchdog driver for Atmel AT91SAM9x processors");
  342. MODULE_LICENSE("GPL");