asm9260_wdt.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Watchdog driver for Alphascale ASM9260.
  4. *
  5. * Copyright (c) 2014 Oleksij Rempel <linux@rempel-privat.de>
  6. */
  7. #include <linux/bitops.h>
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/reset.h>
  16. #include <linux/watchdog.h>
  17. #define CLOCK_FREQ 1000000
  18. /* Watchdog Mode register */
  19. #define HW_WDMOD 0x00
  20. /* Wake interrupt. Set by HW, can't be cleared. */
  21. #define BM_MOD_WDINT BIT(3)
  22. /* This bit set if timeout reached. Cleared by SW. */
  23. #define BM_MOD_WDTOF BIT(2)
  24. /* HW Reset on timeout */
  25. #define BM_MOD_WDRESET BIT(1)
  26. /* WD enable */
  27. #define BM_MOD_WDEN BIT(0)
  28. /*
  29. * Watchdog Timer Constant register
  30. * Minimal value is 0xff, the meaning of this value
  31. * depends on used clock: T = WDCLK * (0xff + 1) * 4
  32. */
  33. #define HW_WDTC 0x04
  34. #define BM_WDTC_MAX(freq) (0x7fffffff / (freq))
  35. /* Watchdog Feed register */
  36. #define HW_WDFEED 0x08
  37. /* Watchdog Timer Value register */
  38. #define HW_WDTV 0x0c
  39. #define ASM9260_WDT_DEFAULT_TIMEOUT 30
  40. enum asm9260_wdt_mode {
  41. HW_RESET,
  42. SW_RESET,
  43. DEBUG,
  44. };
  45. struct asm9260_wdt_priv {
  46. struct device *dev;
  47. struct watchdog_device wdd;
  48. struct clk *clk;
  49. struct clk *clk_ahb;
  50. struct reset_control *rst;
  51. void __iomem *iobase;
  52. int irq;
  53. unsigned long wdt_freq;
  54. enum asm9260_wdt_mode mode;
  55. };
  56. static int asm9260_wdt_feed(struct watchdog_device *wdd)
  57. {
  58. struct asm9260_wdt_priv *priv = watchdog_get_drvdata(wdd);
  59. iowrite32(0xaa, priv->iobase + HW_WDFEED);
  60. iowrite32(0x55, priv->iobase + HW_WDFEED);
  61. return 0;
  62. }
  63. static unsigned int asm9260_wdt_gettimeleft(struct watchdog_device *wdd)
  64. {
  65. struct asm9260_wdt_priv *priv = watchdog_get_drvdata(wdd);
  66. u32 counter;
  67. counter = ioread32(priv->iobase + HW_WDTV);
  68. return counter / priv->wdt_freq;
  69. }
  70. static int asm9260_wdt_updatetimeout(struct watchdog_device *wdd)
  71. {
  72. struct asm9260_wdt_priv *priv = watchdog_get_drvdata(wdd);
  73. u32 counter;
  74. counter = wdd->timeout * priv->wdt_freq;
  75. iowrite32(counter, priv->iobase + HW_WDTC);
  76. return 0;
  77. }
  78. static int asm9260_wdt_enable(struct watchdog_device *wdd)
  79. {
  80. struct asm9260_wdt_priv *priv = watchdog_get_drvdata(wdd);
  81. u32 mode = 0;
  82. if (priv->mode == HW_RESET)
  83. mode = BM_MOD_WDRESET;
  84. iowrite32(BM_MOD_WDEN | mode, priv->iobase + HW_WDMOD);
  85. asm9260_wdt_updatetimeout(wdd);
  86. asm9260_wdt_feed(wdd);
  87. return 0;
  88. }
  89. static int asm9260_wdt_disable(struct watchdog_device *wdd)
  90. {
  91. struct asm9260_wdt_priv *priv = watchdog_get_drvdata(wdd);
  92. /* The only way to disable WD is to reset it. */
  93. reset_control_assert(priv->rst);
  94. reset_control_deassert(priv->rst);
  95. return 0;
  96. }
  97. static int asm9260_wdt_settimeout(struct watchdog_device *wdd, unsigned int to)
  98. {
  99. wdd->timeout = to;
  100. asm9260_wdt_updatetimeout(wdd);
  101. return 0;
  102. }
  103. static void asm9260_wdt_sys_reset(struct asm9260_wdt_priv *priv)
  104. {
  105. /* init WD if it was not started */
  106. iowrite32(BM_MOD_WDEN | BM_MOD_WDRESET, priv->iobase + HW_WDMOD);
  107. iowrite32(0xff, priv->iobase + HW_WDTC);
  108. /* first pass correct sequence */
  109. asm9260_wdt_feed(&priv->wdd);
  110. /*
  111. * Then write wrong pattern to the feed to trigger reset
  112. * ASAP.
  113. */
  114. iowrite32(0xff, priv->iobase + HW_WDFEED);
  115. mdelay(1000);
  116. }
  117. static irqreturn_t asm9260_wdt_irq(int irq, void *devid)
  118. {
  119. struct asm9260_wdt_priv *priv = devid;
  120. u32 stat;
  121. stat = ioread32(priv->iobase + HW_WDMOD);
  122. if (!(stat & BM_MOD_WDINT))
  123. return IRQ_NONE;
  124. if (priv->mode == DEBUG) {
  125. dev_info(priv->dev, "Watchdog Timeout. Do nothing.\n");
  126. } else {
  127. dev_info(priv->dev, "Watchdog Timeout. Doing SW Reset.\n");
  128. asm9260_wdt_sys_reset(priv);
  129. }
  130. return IRQ_HANDLED;
  131. }
  132. static int asm9260_restart(struct watchdog_device *wdd, unsigned long action,
  133. void *data)
  134. {
  135. struct asm9260_wdt_priv *priv = watchdog_get_drvdata(wdd);
  136. asm9260_wdt_sys_reset(priv);
  137. return 0;
  138. }
  139. static const struct watchdog_info asm9260_wdt_ident = {
  140. .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING
  141. | WDIOF_MAGICCLOSE,
  142. .identity = "Alphascale asm9260 Watchdog",
  143. };
  144. static const struct watchdog_ops asm9260_wdt_ops = {
  145. .owner = THIS_MODULE,
  146. .start = asm9260_wdt_enable,
  147. .stop = asm9260_wdt_disable,
  148. .get_timeleft = asm9260_wdt_gettimeleft,
  149. .ping = asm9260_wdt_feed,
  150. .set_timeout = asm9260_wdt_settimeout,
  151. .restart = asm9260_restart,
  152. };
  153. static void asm9260_clk_disable_unprepare(void *data)
  154. {
  155. clk_disable_unprepare(data);
  156. }
  157. static int asm9260_wdt_get_dt_clks(struct asm9260_wdt_priv *priv)
  158. {
  159. int err;
  160. unsigned long clk;
  161. priv->clk = devm_clk_get(priv->dev, "mod");
  162. if (IS_ERR(priv->clk)) {
  163. dev_err(priv->dev, "Failed to get \"mod\" clk\n");
  164. return PTR_ERR(priv->clk);
  165. }
  166. /* configure AHB clock */
  167. priv->clk_ahb = devm_clk_get(priv->dev, "ahb");
  168. if (IS_ERR(priv->clk_ahb)) {
  169. dev_err(priv->dev, "Failed to get \"ahb\" clk\n");
  170. return PTR_ERR(priv->clk_ahb);
  171. }
  172. err = clk_prepare_enable(priv->clk_ahb);
  173. if (err) {
  174. dev_err(priv->dev, "Failed to enable ahb_clk!\n");
  175. return err;
  176. }
  177. err = devm_add_action_or_reset(priv->dev,
  178. asm9260_clk_disable_unprepare,
  179. priv->clk_ahb);
  180. if (err)
  181. return err;
  182. err = clk_set_rate(priv->clk, CLOCK_FREQ);
  183. if (err) {
  184. dev_err(priv->dev, "Failed to set rate!\n");
  185. return err;
  186. }
  187. err = clk_prepare_enable(priv->clk);
  188. if (err) {
  189. dev_err(priv->dev, "Failed to enable clk!\n");
  190. return err;
  191. }
  192. err = devm_add_action_or_reset(priv->dev,
  193. asm9260_clk_disable_unprepare,
  194. priv->clk);
  195. if (err)
  196. return err;
  197. /* wdt has internal divider */
  198. clk = clk_get_rate(priv->clk);
  199. if (!clk) {
  200. dev_err(priv->dev, "Failed, clk is 0!\n");
  201. return -EINVAL;
  202. }
  203. priv->wdt_freq = clk / 2;
  204. return 0;
  205. }
  206. static void asm9260_wdt_get_dt_mode(struct asm9260_wdt_priv *priv)
  207. {
  208. const char *tmp;
  209. int ret;
  210. /* default mode */
  211. priv->mode = HW_RESET;
  212. ret = of_property_read_string(priv->dev->of_node,
  213. "alphascale,mode", &tmp);
  214. if (ret < 0)
  215. return;
  216. if (!strcmp(tmp, "hw"))
  217. priv->mode = HW_RESET;
  218. else if (!strcmp(tmp, "sw"))
  219. priv->mode = SW_RESET;
  220. else if (!strcmp(tmp, "debug"))
  221. priv->mode = DEBUG;
  222. else
  223. dev_warn(priv->dev, "unknown reset-type: %s. Using default \"hw\" mode.",
  224. tmp);
  225. }
  226. static int asm9260_wdt_probe(struct platform_device *pdev)
  227. {
  228. struct device *dev = &pdev->dev;
  229. struct asm9260_wdt_priv *priv;
  230. struct watchdog_device *wdd;
  231. int ret;
  232. static const char * const mode_name[] = { "hw", "sw", "debug", };
  233. priv = devm_kzalloc(dev, sizeof(struct asm9260_wdt_priv), GFP_KERNEL);
  234. if (!priv)
  235. return -ENOMEM;
  236. priv->dev = dev;
  237. priv->iobase = devm_platform_ioremap_resource(pdev, 0);
  238. if (IS_ERR(priv->iobase))
  239. return PTR_ERR(priv->iobase);
  240. priv->rst = devm_reset_control_get_exclusive(dev, "wdt_rst");
  241. if (IS_ERR(priv->rst))
  242. return PTR_ERR(priv->rst);
  243. ret = asm9260_wdt_get_dt_clks(priv);
  244. if (ret)
  245. return ret;
  246. wdd = &priv->wdd;
  247. wdd->info = &asm9260_wdt_ident;
  248. wdd->ops = &asm9260_wdt_ops;
  249. wdd->min_timeout = 1;
  250. wdd->max_timeout = BM_WDTC_MAX(priv->wdt_freq);
  251. wdd->parent = dev;
  252. watchdog_set_drvdata(wdd, priv);
  253. /*
  254. * If 'timeout-sec' unspecified in devicetree, assume a 30 second
  255. * default, unless the max timeout is less than 30 seconds, then use
  256. * the max instead.
  257. */
  258. wdd->timeout = ASM9260_WDT_DEFAULT_TIMEOUT;
  259. watchdog_init_timeout(wdd, 0, dev);
  260. asm9260_wdt_get_dt_mode(priv);
  261. if (priv->mode != HW_RESET)
  262. priv->irq = platform_get_irq(pdev, 0);
  263. if (priv->irq > 0) {
  264. /*
  265. * Not all supported platforms specify an interrupt for the
  266. * watchdog, so let's make it optional.
  267. */
  268. ret = devm_request_irq(dev, priv->irq, asm9260_wdt_irq, 0,
  269. pdev->name, priv);
  270. if (ret < 0)
  271. dev_warn(dev, "failed to request IRQ\n");
  272. }
  273. watchdog_set_restart_priority(wdd, 128);
  274. watchdog_stop_on_reboot(wdd);
  275. watchdog_stop_on_unregister(wdd);
  276. ret = devm_watchdog_register_device(dev, wdd);
  277. if (ret)
  278. return ret;
  279. platform_set_drvdata(pdev, priv);
  280. dev_info(dev, "Watchdog enabled (timeout: %d sec, mode: %s)\n",
  281. wdd->timeout, mode_name[priv->mode]);
  282. return 0;
  283. }
  284. static const struct of_device_id asm9260_wdt_of_match[] = {
  285. { .compatible = "alphascale,asm9260-wdt"},
  286. {},
  287. };
  288. MODULE_DEVICE_TABLE(of, asm9260_wdt_of_match);
  289. static struct platform_driver asm9260_wdt_driver = {
  290. .driver = {
  291. .name = "asm9260-wdt",
  292. .of_match_table = asm9260_wdt_of_match,
  293. },
  294. .probe = asm9260_wdt_probe,
  295. };
  296. module_platform_driver(asm9260_wdt_driver);
  297. MODULE_DESCRIPTION("asm9260 WatchDog Timer Driver");
  298. MODULE_AUTHOR("Oleksij Rempel <linux@rempel-privat.de>");
  299. MODULE_LICENSE("GPL");