uniphier_thermal.c 9.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * uniphier_thermal.c - Socionext UniPhier thermal driver
  4. * Copyright 2014 Panasonic Corporation
  5. * Copyright 2016-2017 Socionext Inc.
  6. * Author:
  7. * Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
  8. */
  9. #include <linux/bitops.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/mfd/syscon.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/of_device.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/regmap.h>
  17. #include <linux/thermal.h>
  18. #include "thermal_core.h"
  19. /*
  20. * block registers
  21. * addresses are the offset from .block_base
  22. */
  23. #define PVTCTLEN 0x0000
  24. #define PVTCTLEN_EN BIT(0)
  25. #define PVTCTLMODE 0x0004
  26. #define PVTCTLMODE_MASK 0xf
  27. #define PVTCTLMODE_TEMPMON 0x5
  28. #define EMONREPEAT 0x0040
  29. #define EMONREPEAT_ENDLESS BIT(24)
  30. #define EMONREPEAT_PERIOD GENMASK(3, 0)
  31. #define EMONREPEAT_PERIOD_1000000 0x9
  32. /*
  33. * common registers
  34. * addresses are the offset from .map_base
  35. */
  36. #define PVTCTLSEL 0x0900
  37. #define PVTCTLSEL_MASK GENMASK(2, 0)
  38. #define PVTCTLSEL_MONITOR 0
  39. #define SETALERT0 0x0910
  40. #define SETALERT1 0x0914
  41. #define SETALERT2 0x0918
  42. #define SETALERT_TEMP_OVF (GENMASK(7, 0) << 16)
  43. #define SETALERT_TEMP_OVF_VALUE(val) (((val) & GENMASK(7, 0)) << 16)
  44. #define SETALERT_EN BIT(0)
  45. #define PMALERTINTCTL 0x0920
  46. #define PMALERTINTCTL_CLR(ch) BIT(4 * (ch) + 2)
  47. #define PMALERTINTCTL_SET(ch) BIT(4 * (ch) + 1)
  48. #define PMALERTINTCTL_EN(ch) BIT(4 * (ch) + 0)
  49. #define PMALERTINTCTL_MASK (GENMASK(10, 8) | GENMASK(6, 4) | \
  50. GENMASK(2, 0))
  51. #define TMOD 0x0928
  52. #define TMOD_WIDTH 9
  53. #define TMODCOEF 0x0e5c
  54. #define TMODSETUP0_EN BIT(30)
  55. #define TMODSETUP0_VAL(val) (((val) & GENMASK(13, 0)) << 16)
  56. #define TMODSETUP1_EN BIT(15)
  57. #define TMODSETUP1_VAL(val) ((val) & GENMASK(14, 0))
  58. /* SoC critical temperature */
  59. #define CRITICAL_TEMP_LIMIT (120 * 1000)
  60. /* Max # of alert channels */
  61. #define ALERT_CH_NUM 3
  62. /* SoC specific thermal sensor data */
  63. struct uniphier_tm_soc_data {
  64. u32 map_base;
  65. u32 block_base;
  66. u32 tmod_setup_addr;
  67. };
  68. struct uniphier_tm_dev {
  69. struct regmap *regmap;
  70. struct device *dev;
  71. bool alert_en[ALERT_CH_NUM];
  72. struct thermal_zone_device *tz_dev;
  73. const struct uniphier_tm_soc_data *data;
  74. };
  75. static int uniphier_tm_initialize_sensor(struct uniphier_tm_dev *tdev)
  76. {
  77. struct regmap *map = tdev->regmap;
  78. u32 val;
  79. u32 tmod_calib[2];
  80. int ret;
  81. /* stop PVT */
  82. regmap_write_bits(map, tdev->data->block_base + PVTCTLEN,
  83. PVTCTLEN_EN, 0);
  84. /*
  85. * Since SoC has a calibrated value that was set in advance,
  86. * TMODCOEF shows non-zero and PVT refers the value internally.
  87. *
  88. * If TMODCOEF shows zero, the boards don't have the calibrated
  89. * value, and the driver has to set default value from DT.
  90. */
  91. ret = regmap_read(map, tdev->data->map_base + TMODCOEF, &val);
  92. if (ret)
  93. return ret;
  94. if (!val) {
  95. /* look for the default values in DT */
  96. ret = of_property_read_u32_array(tdev->dev->of_node,
  97. "socionext,tmod-calibration",
  98. tmod_calib,
  99. ARRAY_SIZE(tmod_calib));
  100. if (ret)
  101. return ret;
  102. regmap_write(map, tdev->data->tmod_setup_addr,
  103. TMODSETUP0_EN | TMODSETUP0_VAL(tmod_calib[0]) |
  104. TMODSETUP1_EN | TMODSETUP1_VAL(tmod_calib[1]));
  105. }
  106. /* select temperature mode */
  107. regmap_write_bits(map, tdev->data->block_base + PVTCTLMODE,
  108. PVTCTLMODE_MASK, PVTCTLMODE_TEMPMON);
  109. /* set monitoring period */
  110. regmap_write_bits(map, tdev->data->block_base + EMONREPEAT,
  111. EMONREPEAT_ENDLESS | EMONREPEAT_PERIOD,
  112. EMONREPEAT_ENDLESS | EMONREPEAT_PERIOD_1000000);
  113. /* set monitor mode */
  114. regmap_write_bits(map, tdev->data->map_base + PVTCTLSEL,
  115. PVTCTLSEL_MASK, PVTCTLSEL_MONITOR);
  116. return 0;
  117. }
  118. static void uniphier_tm_set_alert(struct uniphier_tm_dev *tdev, u32 ch,
  119. u32 temp)
  120. {
  121. struct regmap *map = tdev->regmap;
  122. /* set alert temperature */
  123. regmap_write_bits(map, tdev->data->map_base + SETALERT0 + (ch << 2),
  124. SETALERT_EN | SETALERT_TEMP_OVF,
  125. SETALERT_EN |
  126. SETALERT_TEMP_OVF_VALUE(temp / 1000));
  127. }
  128. static void uniphier_tm_enable_sensor(struct uniphier_tm_dev *tdev)
  129. {
  130. struct regmap *map = tdev->regmap;
  131. int i;
  132. u32 bits = 0;
  133. for (i = 0; i < ALERT_CH_NUM; i++)
  134. if (tdev->alert_en[i])
  135. bits |= PMALERTINTCTL_EN(i);
  136. /* enable alert interrupt */
  137. regmap_write_bits(map, tdev->data->map_base + PMALERTINTCTL,
  138. PMALERTINTCTL_MASK, bits);
  139. /* start PVT */
  140. regmap_write_bits(map, tdev->data->block_base + PVTCTLEN,
  141. PVTCTLEN_EN, PVTCTLEN_EN);
  142. usleep_range(700, 1500); /* The spec note says at least 700us */
  143. }
  144. static void uniphier_tm_disable_sensor(struct uniphier_tm_dev *tdev)
  145. {
  146. struct regmap *map = tdev->regmap;
  147. /* disable alert interrupt */
  148. regmap_write_bits(map, tdev->data->map_base + PMALERTINTCTL,
  149. PMALERTINTCTL_MASK, 0);
  150. /* stop PVT */
  151. regmap_write_bits(map, tdev->data->block_base + PVTCTLEN,
  152. PVTCTLEN_EN, 0);
  153. usleep_range(1000, 2000); /* The spec note says at least 1ms */
  154. }
  155. static int uniphier_tm_get_temp(void *data, int *out_temp)
  156. {
  157. struct uniphier_tm_dev *tdev = data;
  158. struct regmap *map = tdev->regmap;
  159. int ret;
  160. u32 temp;
  161. ret = regmap_read(map, tdev->data->map_base + TMOD, &temp);
  162. if (ret)
  163. return ret;
  164. /* MSB of the TMOD field is a sign bit */
  165. *out_temp = sign_extend32(temp, TMOD_WIDTH - 1) * 1000;
  166. return 0;
  167. }
  168. static const struct thermal_zone_of_device_ops uniphier_of_thermal_ops = {
  169. .get_temp = uniphier_tm_get_temp,
  170. };
  171. static void uniphier_tm_irq_clear(struct uniphier_tm_dev *tdev)
  172. {
  173. u32 mask = 0, bits = 0;
  174. int i;
  175. for (i = 0; i < ALERT_CH_NUM; i++) {
  176. mask |= (PMALERTINTCTL_CLR(i) | PMALERTINTCTL_SET(i));
  177. bits |= PMALERTINTCTL_CLR(i);
  178. }
  179. /* clear alert interrupt */
  180. regmap_write_bits(tdev->regmap,
  181. tdev->data->map_base + PMALERTINTCTL, mask, bits);
  182. }
  183. static irqreturn_t uniphier_tm_alarm_irq(int irq, void *_tdev)
  184. {
  185. struct uniphier_tm_dev *tdev = _tdev;
  186. disable_irq_nosync(irq);
  187. uniphier_tm_irq_clear(tdev);
  188. return IRQ_WAKE_THREAD;
  189. }
  190. static irqreturn_t uniphier_tm_alarm_irq_thread(int irq, void *_tdev)
  191. {
  192. struct uniphier_tm_dev *tdev = _tdev;
  193. thermal_zone_device_update(tdev->tz_dev, THERMAL_EVENT_UNSPECIFIED);
  194. return IRQ_HANDLED;
  195. }
  196. static int uniphier_tm_probe(struct platform_device *pdev)
  197. {
  198. struct device *dev = &pdev->dev;
  199. struct regmap *regmap;
  200. struct device_node *parent;
  201. struct uniphier_tm_dev *tdev;
  202. const struct thermal_trip *trips;
  203. int i, ret, irq, ntrips, crit_temp = INT_MAX;
  204. tdev = devm_kzalloc(dev, sizeof(*tdev), GFP_KERNEL);
  205. if (!tdev)
  206. return -ENOMEM;
  207. tdev->dev = dev;
  208. tdev->data = of_device_get_match_data(dev);
  209. if (WARN_ON(!tdev->data))
  210. return -EINVAL;
  211. irq = platform_get_irq(pdev, 0);
  212. if (irq < 0)
  213. return irq;
  214. /* get regmap from syscon node */
  215. parent = of_get_parent(dev->of_node); /* parent should be syscon node */
  216. regmap = syscon_node_to_regmap(parent);
  217. of_node_put(parent);
  218. if (IS_ERR(regmap)) {
  219. dev_err(dev, "failed to get regmap (error %ld)\n",
  220. PTR_ERR(regmap));
  221. return PTR_ERR(regmap);
  222. }
  223. tdev->regmap = regmap;
  224. ret = uniphier_tm_initialize_sensor(tdev);
  225. if (ret) {
  226. dev_err(dev, "failed to initialize sensor\n");
  227. return ret;
  228. }
  229. ret = devm_request_threaded_irq(dev, irq, uniphier_tm_alarm_irq,
  230. uniphier_tm_alarm_irq_thread,
  231. 0, "thermal", tdev);
  232. if (ret)
  233. return ret;
  234. platform_set_drvdata(pdev, tdev);
  235. tdev->tz_dev = devm_thermal_zone_of_sensor_register(dev, 0, tdev,
  236. &uniphier_of_thermal_ops);
  237. if (IS_ERR(tdev->tz_dev)) {
  238. dev_err(dev, "failed to register sensor device\n");
  239. return PTR_ERR(tdev->tz_dev);
  240. }
  241. /* get trip points */
  242. trips = of_thermal_get_trip_points(tdev->tz_dev);
  243. ntrips = of_thermal_get_ntrips(tdev->tz_dev);
  244. if (ntrips > ALERT_CH_NUM) {
  245. dev_err(dev, "thermal zone has too many trips\n");
  246. return -E2BIG;
  247. }
  248. /* set alert temperatures */
  249. for (i = 0; i < ntrips; i++) {
  250. if (trips[i].type == THERMAL_TRIP_CRITICAL &&
  251. trips[i].temperature < crit_temp)
  252. crit_temp = trips[i].temperature;
  253. uniphier_tm_set_alert(tdev, i, trips[i].temperature);
  254. tdev->alert_en[i] = true;
  255. }
  256. if (crit_temp > CRITICAL_TEMP_LIMIT) {
  257. dev_err(dev, "critical trip is over limit(>%d), or not set\n",
  258. CRITICAL_TEMP_LIMIT);
  259. return -EINVAL;
  260. }
  261. uniphier_tm_enable_sensor(tdev);
  262. return 0;
  263. }
  264. static int uniphier_tm_remove(struct platform_device *pdev)
  265. {
  266. struct uniphier_tm_dev *tdev = platform_get_drvdata(pdev);
  267. /* disable sensor */
  268. uniphier_tm_disable_sensor(tdev);
  269. return 0;
  270. }
  271. static const struct uniphier_tm_soc_data uniphier_pxs2_tm_data = {
  272. .map_base = 0xe000,
  273. .block_base = 0xe000,
  274. .tmod_setup_addr = 0xe904,
  275. };
  276. static const struct uniphier_tm_soc_data uniphier_ld20_tm_data = {
  277. .map_base = 0xe000,
  278. .block_base = 0xe800,
  279. .tmod_setup_addr = 0xe938,
  280. };
  281. static const struct of_device_id uniphier_tm_dt_ids[] = {
  282. {
  283. .compatible = "socionext,uniphier-pxs2-thermal",
  284. .data = &uniphier_pxs2_tm_data,
  285. },
  286. {
  287. .compatible = "socionext,uniphier-ld20-thermal",
  288. .data = &uniphier_ld20_tm_data,
  289. },
  290. {
  291. .compatible = "socionext,uniphier-pxs3-thermal",
  292. .data = &uniphier_ld20_tm_data,
  293. },
  294. { /* sentinel */ }
  295. };
  296. MODULE_DEVICE_TABLE(of, uniphier_tm_dt_ids);
  297. static struct platform_driver uniphier_tm_driver = {
  298. .probe = uniphier_tm_probe,
  299. .remove = uniphier_tm_remove,
  300. .driver = {
  301. .name = "uniphier-thermal",
  302. .of_match_table = uniphier_tm_dt_ids,
  303. },
  304. };
  305. module_platform_driver(uniphier_tm_driver);
  306. MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
  307. MODULE_DESCRIPTION("UniPhier thermal driver");
  308. MODULE_LICENSE("GPL v2");