armada_thermal.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Marvell EBU Armada SoCs thermal sensor driver
  4. *
  5. * Copyright (C) 2013 Marvell
  6. */
  7. #include <linux/device.h>
  8. #include <linux/err.h>
  9. #include <linux/io.h>
  10. #include <linux/kernel.h>
  11. #include <linux/of.h>
  12. #include <linux/module.h>
  13. #include <linux/delay.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/of_device.h>
  16. #include <linux/thermal.h>
  17. #include <linux/iopoll.h>
  18. #include <linux/mfd/syscon.h>
  19. #include <linux/regmap.h>
  20. #include <linux/interrupt.h>
  21. #include "thermal_core.h"
  22. /* Thermal Manager Control and Status Register */
  23. #define PMU_TDC0_SW_RST_MASK (0x1 << 1)
  24. #define PMU_TM_DISABLE_OFFS 0
  25. #define PMU_TM_DISABLE_MASK (0x1 << PMU_TM_DISABLE_OFFS)
  26. #define PMU_TDC0_REF_CAL_CNT_OFFS 11
  27. #define PMU_TDC0_REF_CAL_CNT_MASK (0x1ff << PMU_TDC0_REF_CAL_CNT_OFFS)
  28. #define PMU_TDC0_OTF_CAL_MASK (0x1 << 30)
  29. #define PMU_TDC0_START_CAL_MASK (0x1 << 25)
  30. #define A375_UNIT_CONTROL_SHIFT 27
  31. #define A375_UNIT_CONTROL_MASK 0x7
  32. #define A375_READOUT_INVERT BIT(15)
  33. #define A375_HW_RESETn BIT(8)
  34. /* Errata fields */
  35. #define CONTROL0_TSEN_TC_TRIM_MASK 0x7
  36. #define CONTROL0_TSEN_TC_TRIM_VAL 0x3
  37. #define CONTROL0_TSEN_START BIT(0)
  38. #define CONTROL0_TSEN_RESET BIT(1)
  39. #define CONTROL0_TSEN_ENABLE BIT(2)
  40. #define CONTROL0_TSEN_AVG_BYPASS BIT(6)
  41. #define CONTROL0_TSEN_CHAN_SHIFT 13
  42. #define CONTROL0_TSEN_CHAN_MASK 0xF
  43. #define CONTROL0_TSEN_OSR_SHIFT 24
  44. #define CONTROL0_TSEN_OSR_MAX 0x3
  45. #define CONTROL0_TSEN_MODE_SHIFT 30
  46. #define CONTROL0_TSEN_MODE_EXTERNAL 0x2
  47. #define CONTROL0_TSEN_MODE_MASK 0x3
  48. #define CONTROL1_TSEN_AVG_MASK 0x7
  49. #define CONTROL1_EXT_TSEN_SW_RESET BIT(7)
  50. #define CONTROL1_EXT_TSEN_HW_RESETn BIT(8)
  51. #define CONTROL1_TSEN_INT_EN BIT(25)
  52. #define CONTROL1_TSEN_SELECT_OFF 21
  53. #define CONTROL1_TSEN_SELECT_MASK 0x3
  54. #define STATUS_POLL_PERIOD_US 1000
  55. #define STATUS_POLL_TIMEOUT_US 100000
  56. #define OVERHEAT_INT_POLL_DELAY_MS 1000
  57. struct armada_thermal_data;
  58. /* Marvell EBU Thermal Sensor Dev Structure */
  59. struct armada_thermal_priv {
  60. struct device *dev;
  61. struct regmap *syscon;
  62. char zone_name[THERMAL_NAME_LENGTH];
  63. /* serialize temperature reads/updates */
  64. struct mutex update_lock;
  65. struct armada_thermal_data *data;
  66. struct thermal_zone_device *overheat_sensor;
  67. int interrupt_source;
  68. int current_channel;
  69. long current_threshold;
  70. long current_hysteresis;
  71. };
  72. struct armada_thermal_data {
  73. /* Initialize the thermal IC */
  74. void (*init)(struct platform_device *pdev,
  75. struct armada_thermal_priv *priv);
  76. /* Formula coeficients: temp = (b - m * reg) / div */
  77. s64 coef_b;
  78. s64 coef_m;
  79. u32 coef_div;
  80. bool inverted;
  81. bool signed_sample;
  82. /* Register shift and mask to access the sensor temperature */
  83. unsigned int temp_shift;
  84. unsigned int temp_mask;
  85. unsigned int thresh_shift;
  86. unsigned int hyst_shift;
  87. unsigned int hyst_mask;
  88. u32 is_valid_bit;
  89. /* Syscon access */
  90. unsigned int syscon_control0_off;
  91. unsigned int syscon_control1_off;
  92. unsigned int syscon_status_off;
  93. unsigned int dfx_irq_cause_off;
  94. unsigned int dfx_irq_mask_off;
  95. unsigned int dfx_overheat_irq;
  96. unsigned int dfx_server_irq_mask_off;
  97. unsigned int dfx_server_irq_en;
  98. /* One sensor is in the thermal IC, the others are in the CPUs if any */
  99. unsigned int cpu_nr;
  100. };
  101. struct armada_drvdata {
  102. enum drvtype {
  103. LEGACY,
  104. SYSCON
  105. } type;
  106. union {
  107. struct armada_thermal_priv *priv;
  108. struct thermal_zone_device *tz;
  109. } data;
  110. };
  111. /*
  112. * struct armada_thermal_sensor - hold the information of one thermal sensor
  113. * @thermal: pointer to the local private structure
  114. * @tzd: pointer to the thermal zone device
  115. * @id: identifier of the thermal sensor
  116. */
  117. struct armada_thermal_sensor {
  118. struct armada_thermal_priv *priv;
  119. int id;
  120. };
  121. static void armadaxp_init(struct platform_device *pdev,
  122. struct armada_thermal_priv *priv)
  123. {
  124. struct armada_thermal_data *data = priv->data;
  125. u32 reg;
  126. regmap_read(priv->syscon, data->syscon_control1_off, &reg);
  127. reg |= PMU_TDC0_OTF_CAL_MASK;
  128. /* Reference calibration value */
  129. reg &= ~PMU_TDC0_REF_CAL_CNT_MASK;
  130. reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS);
  131. /* Reset the sensor */
  132. reg |= PMU_TDC0_SW_RST_MASK;
  133. regmap_write(priv->syscon, data->syscon_control1_off, reg);
  134. reg &= ~PMU_TDC0_SW_RST_MASK;
  135. regmap_write(priv->syscon, data->syscon_control1_off, reg);
  136. /* Enable the sensor */
  137. regmap_read(priv->syscon, data->syscon_status_off, &reg);
  138. reg &= ~PMU_TM_DISABLE_MASK;
  139. regmap_write(priv->syscon, data->syscon_status_off, reg);
  140. }
  141. static void armada370_init(struct platform_device *pdev,
  142. struct armada_thermal_priv *priv)
  143. {
  144. struct armada_thermal_data *data = priv->data;
  145. u32 reg;
  146. regmap_read(priv->syscon, data->syscon_control1_off, &reg);
  147. reg |= PMU_TDC0_OTF_CAL_MASK;
  148. /* Reference calibration value */
  149. reg &= ~PMU_TDC0_REF_CAL_CNT_MASK;
  150. reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS);
  151. /* Reset the sensor */
  152. reg &= ~PMU_TDC0_START_CAL_MASK;
  153. regmap_write(priv->syscon, data->syscon_control1_off, reg);
  154. msleep(10);
  155. }
  156. static void armada375_init(struct platform_device *pdev,
  157. struct armada_thermal_priv *priv)
  158. {
  159. struct armada_thermal_data *data = priv->data;
  160. u32 reg;
  161. regmap_read(priv->syscon, data->syscon_control1_off, &reg);
  162. reg &= ~(A375_UNIT_CONTROL_MASK << A375_UNIT_CONTROL_SHIFT);
  163. reg &= ~A375_READOUT_INVERT;
  164. reg &= ~A375_HW_RESETn;
  165. regmap_write(priv->syscon, data->syscon_control1_off, reg);
  166. msleep(20);
  167. reg |= A375_HW_RESETn;
  168. regmap_write(priv->syscon, data->syscon_control1_off, reg);
  169. msleep(50);
  170. }
  171. static int armada_wait_sensor_validity(struct armada_thermal_priv *priv)
  172. {
  173. u32 reg;
  174. return regmap_read_poll_timeout(priv->syscon,
  175. priv->data->syscon_status_off, reg,
  176. reg & priv->data->is_valid_bit,
  177. STATUS_POLL_PERIOD_US,
  178. STATUS_POLL_TIMEOUT_US);
  179. }
  180. static void armada380_init(struct platform_device *pdev,
  181. struct armada_thermal_priv *priv)
  182. {
  183. struct armada_thermal_data *data = priv->data;
  184. u32 reg;
  185. /* Disable the HW/SW reset */
  186. regmap_read(priv->syscon, data->syscon_control1_off, &reg);
  187. reg |= CONTROL1_EXT_TSEN_HW_RESETn;
  188. reg &= ~CONTROL1_EXT_TSEN_SW_RESET;
  189. regmap_write(priv->syscon, data->syscon_control1_off, reg);
  190. /* Set Tsen Tc Trim to correct default value (errata #132698) */
  191. regmap_read(priv->syscon, data->syscon_control0_off, &reg);
  192. reg &= ~CONTROL0_TSEN_TC_TRIM_MASK;
  193. reg |= CONTROL0_TSEN_TC_TRIM_VAL;
  194. regmap_write(priv->syscon, data->syscon_control0_off, reg);
  195. }
  196. static void armada_ap806_init(struct platform_device *pdev,
  197. struct armada_thermal_priv *priv)
  198. {
  199. struct armada_thermal_data *data = priv->data;
  200. u32 reg;
  201. regmap_read(priv->syscon, data->syscon_control0_off, &reg);
  202. reg &= ~CONTROL0_TSEN_RESET;
  203. reg |= CONTROL0_TSEN_START | CONTROL0_TSEN_ENABLE;
  204. /* Sample every ~2ms */
  205. reg |= CONTROL0_TSEN_OSR_MAX << CONTROL0_TSEN_OSR_SHIFT;
  206. /* Enable average (2 samples by default) */
  207. reg &= ~CONTROL0_TSEN_AVG_BYPASS;
  208. regmap_write(priv->syscon, data->syscon_control0_off, reg);
  209. }
  210. static void armada_cp110_init(struct platform_device *pdev,
  211. struct armada_thermal_priv *priv)
  212. {
  213. struct armada_thermal_data *data = priv->data;
  214. u32 reg;
  215. armada380_init(pdev, priv);
  216. /* Sample every ~2ms */
  217. regmap_read(priv->syscon, data->syscon_control0_off, &reg);
  218. reg |= CONTROL0_TSEN_OSR_MAX << CONTROL0_TSEN_OSR_SHIFT;
  219. regmap_write(priv->syscon, data->syscon_control0_off, reg);
  220. /* Average the output value over 2^1 = 2 samples */
  221. regmap_read(priv->syscon, data->syscon_control1_off, &reg);
  222. reg &= ~CONTROL1_TSEN_AVG_MASK;
  223. reg |= 1;
  224. regmap_write(priv->syscon, data->syscon_control1_off, reg);
  225. }
  226. static bool armada_is_valid(struct armada_thermal_priv *priv)
  227. {
  228. u32 reg;
  229. if (!priv->data->is_valid_bit)
  230. return true;
  231. regmap_read(priv->syscon, priv->data->syscon_status_off, &reg);
  232. return reg & priv->data->is_valid_bit;
  233. }
  234. static void armada_enable_overheat_interrupt(struct armada_thermal_priv *priv)
  235. {
  236. struct armada_thermal_data *data = priv->data;
  237. u32 reg;
  238. /* Clear DFX temperature IRQ cause */
  239. regmap_read(priv->syscon, data->dfx_irq_cause_off, &reg);
  240. /* Enable DFX Temperature IRQ */
  241. regmap_read(priv->syscon, data->dfx_irq_mask_off, &reg);
  242. reg |= data->dfx_overheat_irq;
  243. regmap_write(priv->syscon, data->dfx_irq_mask_off, reg);
  244. /* Enable DFX server IRQ */
  245. regmap_read(priv->syscon, data->dfx_server_irq_mask_off, &reg);
  246. reg |= data->dfx_server_irq_en;
  247. regmap_write(priv->syscon, data->dfx_server_irq_mask_off, reg);
  248. /* Enable overheat interrupt */
  249. regmap_read(priv->syscon, data->syscon_control1_off, &reg);
  250. reg |= CONTROL1_TSEN_INT_EN;
  251. regmap_write(priv->syscon, data->syscon_control1_off, reg);
  252. }
  253. static void __maybe_unused
  254. armada_disable_overheat_interrupt(struct armada_thermal_priv *priv)
  255. {
  256. struct armada_thermal_data *data = priv->data;
  257. u32 reg;
  258. regmap_read(priv->syscon, data->syscon_control1_off, &reg);
  259. reg &= ~CONTROL1_TSEN_INT_EN;
  260. regmap_write(priv->syscon, data->syscon_control1_off, reg);
  261. }
  262. /* There is currently no board with more than one sensor per channel */
  263. static int armada_select_channel(struct armada_thermal_priv *priv, int channel)
  264. {
  265. struct armada_thermal_data *data = priv->data;
  266. u32 ctrl0;
  267. if (channel < 0 || channel > priv->data->cpu_nr)
  268. return -EINVAL;
  269. if (priv->current_channel == channel)
  270. return 0;
  271. /* Stop the measurements */
  272. regmap_read(priv->syscon, data->syscon_control0_off, &ctrl0);
  273. ctrl0 &= ~CONTROL0_TSEN_START;
  274. regmap_write(priv->syscon, data->syscon_control0_off, ctrl0);
  275. /* Reset the mode, internal sensor will be automatically selected */
  276. ctrl0 &= ~(CONTROL0_TSEN_MODE_MASK << CONTROL0_TSEN_MODE_SHIFT);
  277. /* Other channels are external and should be selected accordingly */
  278. if (channel) {
  279. /* Change the mode to external */
  280. ctrl0 |= CONTROL0_TSEN_MODE_EXTERNAL <<
  281. CONTROL0_TSEN_MODE_SHIFT;
  282. /* Select the sensor */
  283. ctrl0 &= ~(CONTROL0_TSEN_CHAN_MASK << CONTROL0_TSEN_CHAN_SHIFT);
  284. ctrl0 |= (channel - 1) << CONTROL0_TSEN_CHAN_SHIFT;
  285. }
  286. /* Actually set the mode/channel */
  287. regmap_write(priv->syscon, data->syscon_control0_off, ctrl0);
  288. priv->current_channel = channel;
  289. /* Re-start the measurements */
  290. ctrl0 |= CONTROL0_TSEN_START;
  291. regmap_write(priv->syscon, data->syscon_control0_off, ctrl0);
  292. /*
  293. * The IP has a latency of ~15ms, so after updating the selected source,
  294. * we must absolutely wait for the sensor validity bit to ensure we read
  295. * actual data.
  296. */
  297. if (armada_wait_sensor_validity(priv)) {
  298. dev_err(priv->dev,
  299. "Temperature sensor reading not valid\n");
  300. return -EIO;
  301. }
  302. return 0;
  303. }
  304. static int armada_read_sensor(struct armada_thermal_priv *priv, int *temp)
  305. {
  306. u32 reg, div;
  307. s64 sample, b, m;
  308. regmap_read(priv->syscon, priv->data->syscon_status_off, &reg);
  309. reg = (reg >> priv->data->temp_shift) & priv->data->temp_mask;
  310. if (priv->data->signed_sample)
  311. /* The most significant bit is the sign bit */
  312. sample = sign_extend32(reg, fls(priv->data->temp_mask) - 1);
  313. else
  314. sample = reg;
  315. /* Get formula coeficients */
  316. b = priv->data->coef_b;
  317. m = priv->data->coef_m;
  318. div = priv->data->coef_div;
  319. if (priv->data->inverted)
  320. *temp = div_s64((m * sample) - b, div);
  321. else
  322. *temp = div_s64(b - (m * sample), div);
  323. return 0;
  324. }
  325. static int armada_get_temp_legacy(struct thermal_zone_device *thermal,
  326. int *temp)
  327. {
  328. struct armada_thermal_priv *priv = thermal->devdata;
  329. int ret;
  330. /* Valid check */
  331. if (!armada_is_valid(priv)) {
  332. dev_err(priv->dev,
  333. "Temperature sensor reading not valid\n");
  334. return -EIO;
  335. }
  336. /* Do the actual reading */
  337. ret = armada_read_sensor(priv, temp);
  338. return ret;
  339. }
  340. static struct thermal_zone_device_ops legacy_ops = {
  341. .get_temp = armada_get_temp_legacy,
  342. };
  343. static int armada_get_temp(void *_sensor, int *temp)
  344. {
  345. struct armada_thermal_sensor *sensor = _sensor;
  346. struct armada_thermal_priv *priv = sensor->priv;
  347. int ret;
  348. mutex_lock(&priv->update_lock);
  349. /* Select the desired channel */
  350. ret = armada_select_channel(priv, sensor->id);
  351. if (ret)
  352. goto unlock_mutex;
  353. /* Do the actual reading */
  354. ret = armada_read_sensor(priv, temp);
  355. if (ret)
  356. goto unlock_mutex;
  357. /*
  358. * Select back the interrupt source channel from which a potential
  359. * critical trip point has been set.
  360. */
  361. ret = armada_select_channel(priv, priv->interrupt_source);
  362. unlock_mutex:
  363. mutex_unlock(&priv->update_lock);
  364. return ret;
  365. }
  366. static const struct thermal_zone_of_device_ops of_ops = {
  367. .get_temp = armada_get_temp,
  368. };
  369. static unsigned int armada_mc_to_reg_temp(struct armada_thermal_data *data,
  370. unsigned int temp_mc)
  371. {
  372. s64 b = data->coef_b;
  373. s64 m = data->coef_m;
  374. s64 div = data->coef_div;
  375. unsigned int sample;
  376. if (data->inverted)
  377. sample = div_s64(((temp_mc * div) + b), m);
  378. else
  379. sample = div_s64((b - (temp_mc * div)), m);
  380. return sample & data->temp_mask;
  381. }
  382. /*
  383. * The documentation states:
  384. * high/low watermark = threshold +/- 0.4761 * 2^(hysteresis + 2)
  385. * which is the mathematical derivation for:
  386. * 0x0 <=> 1.9°C, 0x1 <=> 3.8°C, 0x2 <=> 7.6°C, 0x3 <=> 15.2°C
  387. */
  388. static unsigned int hyst_levels_mc[] = {1900, 3800, 7600, 15200};
  389. static unsigned int armada_mc_to_reg_hyst(struct armada_thermal_data *data,
  390. unsigned int hyst_mc)
  391. {
  392. int i;
  393. /*
  394. * We will always take the smallest possible hysteresis to avoid risking
  395. * the hardware integrity by enlarging the threshold by +8°C in the
  396. * worst case.
  397. */
  398. for (i = ARRAY_SIZE(hyst_levels_mc) - 1; i > 0; i--)
  399. if (hyst_mc >= hyst_levels_mc[i])
  400. break;
  401. return i & data->hyst_mask;
  402. }
  403. static void armada_set_overheat_thresholds(struct armada_thermal_priv *priv,
  404. int thresh_mc, int hyst_mc)
  405. {
  406. struct armada_thermal_data *data = priv->data;
  407. unsigned int threshold = armada_mc_to_reg_temp(data, thresh_mc);
  408. unsigned int hysteresis = armada_mc_to_reg_hyst(data, hyst_mc);
  409. u32 ctrl1;
  410. regmap_read(priv->syscon, data->syscon_control1_off, &ctrl1);
  411. /* Set Threshold */
  412. if (thresh_mc >= 0) {
  413. ctrl1 &= ~(data->temp_mask << data->thresh_shift);
  414. ctrl1 |= threshold << data->thresh_shift;
  415. priv->current_threshold = thresh_mc;
  416. }
  417. /* Set Hysteresis */
  418. if (hyst_mc >= 0) {
  419. ctrl1 &= ~(data->hyst_mask << data->hyst_shift);
  420. ctrl1 |= hysteresis << data->hyst_shift;
  421. priv->current_hysteresis = hyst_mc;
  422. }
  423. regmap_write(priv->syscon, data->syscon_control1_off, ctrl1);
  424. }
  425. static irqreturn_t armada_overheat_isr(int irq, void *blob)
  426. {
  427. /*
  428. * Disable the IRQ and continue in thread context (thermal core
  429. * notification and temperature monitoring).
  430. */
  431. disable_irq_nosync(irq);
  432. return IRQ_WAKE_THREAD;
  433. }
  434. static irqreturn_t armada_overheat_isr_thread(int irq, void *blob)
  435. {
  436. struct armada_thermal_priv *priv = blob;
  437. int low_threshold = priv->current_threshold - priv->current_hysteresis;
  438. int temperature;
  439. u32 dummy;
  440. int ret;
  441. /* Notify the core in thread context */
  442. thermal_zone_device_update(priv->overheat_sensor,
  443. THERMAL_EVENT_UNSPECIFIED);
  444. /*
  445. * The overheat interrupt must be cleared by reading the DFX interrupt
  446. * cause _after_ the temperature has fallen down to the low threshold.
  447. * Otherwise future interrupts might not be served.
  448. */
  449. do {
  450. msleep(OVERHEAT_INT_POLL_DELAY_MS);
  451. mutex_lock(&priv->update_lock);
  452. ret = armada_read_sensor(priv, &temperature);
  453. mutex_unlock(&priv->update_lock);
  454. if (ret)
  455. goto enable_irq;
  456. } while (temperature >= low_threshold);
  457. regmap_read(priv->syscon, priv->data->dfx_irq_cause_off, &dummy);
  458. /* Notify the thermal core that the temperature is acceptable again */
  459. thermal_zone_device_update(priv->overheat_sensor,
  460. THERMAL_EVENT_UNSPECIFIED);
  461. enable_irq:
  462. enable_irq(irq);
  463. return IRQ_HANDLED;
  464. }
  465. static const struct armada_thermal_data armadaxp_data = {
  466. .init = armadaxp_init,
  467. .temp_shift = 10,
  468. .temp_mask = 0x1ff,
  469. .coef_b = 3153000000ULL,
  470. .coef_m = 10000000ULL,
  471. .coef_div = 13825,
  472. .syscon_status_off = 0xb0,
  473. .syscon_control1_off = 0x2d0,
  474. };
  475. static const struct armada_thermal_data armada370_data = {
  476. .init = armada370_init,
  477. .is_valid_bit = BIT(9),
  478. .temp_shift = 10,
  479. .temp_mask = 0x1ff,
  480. .coef_b = 3153000000ULL,
  481. .coef_m = 10000000ULL,
  482. .coef_div = 13825,
  483. .syscon_status_off = 0x0,
  484. .syscon_control1_off = 0x4,
  485. };
  486. static const struct armada_thermal_data armada375_data = {
  487. .init = armada375_init,
  488. .is_valid_bit = BIT(10),
  489. .temp_shift = 0,
  490. .temp_mask = 0x1ff,
  491. .coef_b = 3171900000ULL,
  492. .coef_m = 10000000ULL,
  493. .coef_div = 13616,
  494. .syscon_status_off = 0x78,
  495. .syscon_control0_off = 0x7c,
  496. .syscon_control1_off = 0x80,
  497. };
  498. static const struct armada_thermal_data armada380_data = {
  499. .init = armada380_init,
  500. .is_valid_bit = BIT(10),
  501. .temp_shift = 0,
  502. .temp_mask = 0x3ff,
  503. .coef_b = 1172499100ULL,
  504. .coef_m = 2000096ULL,
  505. .coef_div = 4201,
  506. .inverted = true,
  507. .syscon_control0_off = 0x70,
  508. .syscon_control1_off = 0x74,
  509. .syscon_status_off = 0x78,
  510. };
  511. static const struct armada_thermal_data armada_ap806_data = {
  512. .init = armada_ap806_init,
  513. .is_valid_bit = BIT(16),
  514. .temp_shift = 0,
  515. .temp_mask = 0x3ff,
  516. .thresh_shift = 3,
  517. .hyst_shift = 19,
  518. .hyst_mask = 0x3,
  519. .coef_b = -150000LL,
  520. .coef_m = 423ULL,
  521. .coef_div = 1,
  522. .inverted = true,
  523. .signed_sample = true,
  524. .syscon_control0_off = 0x84,
  525. .syscon_control1_off = 0x88,
  526. .syscon_status_off = 0x8C,
  527. .dfx_irq_cause_off = 0x108,
  528. .dfx_irq_mask_off = 0x10C,
  529. .dfx_overheat_irq = BIT(22),
  530. .dfx_server_irq_mask_off = 0x104,
  531. .dfx_server_irq_en = BIT(1),
  532. .cpu_nr = 4,
  533. };
  534. static const struct armada_thermal_data armada_cp110_data = {
  535. .init = armada_cp110_init,
  536. .is_valid_bit = BIT(10),
  537. .temp_shift = 0,
  538. .temp_mask = 0x3ff,
  539. .thresh_shift = 16,
  540. .hyst_shift = 26,
  541. .hyst_mask = 0x3,
  542. .coef_b = 1172499100ULL,
  543. .coef_m = 2000096ULL,
  544. .coef_div = 4201,
  545. .inverted = true,
  546. .syscon_control0_off = 0x70,
  547. .syscon_control1_off = 0x74,
  548. .syscon_status_off = 0x78,
  549. .dfx_irq_cause_off = 0x108,
  550. .dfx_irq_mask_off = 0x10C,
  551. .dfx_overheat_irq = BIT(20),
  552. .dfx_server_irq_mask_off = 0x104,
  553. .dfx_server_irq_en = BIT(1),
  554. };
  555. static const struct of_device_id armada_thermal_id_table[] = {
  556. {
  557. .compatible = "marvell,armadaxp-thermal",
  558. .data = &armadaxp_data,
  559. },
  560. {
  561. .compatible = "marvell,armada370-thermal",
  562. .data = &armada370_data,
  563. },
  564. {
  565. .compatible = "marvell,armada375-thermal",
  566. .data = &armada375_data,
  567. },
  568. {
  569. .compatible = "marvell,armada380-thermal",
  570. .data = &armada380_data,
  571. },
  572. {
  573. .compatible = "marvell,armada-ap806-thermal",
  574. .data = &armada_ap806_data,
  575. },
  576. {
  577. .compatible = "marvell,armada-cp110-thermal",
  578. .data = &armada_cp110_data,
  579. },
  580. {
  581. /* sentinel */
  582. },
  583. };
  584. MODULE_DEVICE_TABLE(of, armada_thermal_id_table);
  585. static const struct regmap_config armada_thermal_regmap_config = {
  586. .reg_bits = 32,
  587. .reg_stride = 4,
  588. .val_bits = 32,
  589. .fast_io = true,
  590. };
  591. static int armada_thermal_probe_legacy(struct platform_device *pdev,
  592. struct armada_thermal_priv *priv)
  593. {
  594. struct armada_thermal_data *data = priv->data;
  595. struct resource *res;
  596. void __iomem *base;
  597. /* First memory region points towards the status register */
  598. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  599. base = devm_ioremap_resource(&pdev->dev, res);
  600. if (IS_ERR(base))
  601. return PTR_ERR(base);
  602. /*
  603. * Fix up from the old individual DT register specification to
  604. * cover all the registers. We do this by adjusting the ioremap()
  605. * result, which should be fine as ioremap() deals with pages.
  606. * However, validate that we do not cross a page boundary while
  607. * making this adjustment.
  608. */
  609. if (((unsigned long)base & ~PAGE_MASK) < data->syscon_status_off)
  610. return -EINVAL;
  611. base -= data->syscon_status_off;
  612. priv->syscon = devm_regmap_init_mmio(&pdev->dev, base,
  613. &armada_thermal_regmap_config);
  614. return PTR_ERR_OR_ZERO(priv->syscon);
  615. }
  616. static int armada_thermal_probe_syscon(struct platform_device *pdev,
  617. struct armada_thermal_priv *priv)
  618. {
  619. priv->syscon = syscon_node_to_regmap(pdev->dev.parent->of_node);
  620. return PTR_ERR_OR_ZERO(priv->syscon);
  621. }
  622. static void armada_set_sane_name(struct platform_device *pdev,
  623. struct armada_thermal_priv *priv)
  624. {
  625. const char *name = dev_name(&pdev->dev);
  626. char *insane_char;
  627. if (strlen(name) > THERMAL_NAME_LENGTH) {
  628. /*
  629. * When inside a system controller, the device name has the
  630. * form: f06f8000.system-controller:ap-thermal so stripping
  631. * after the ':' should give us a shorter but meaningful name.
  632. */
  633. name = strrchr(name, ':');
  634. if (!name)
  635. name = "armada_thermal";
  636. else
  637. name++;
  638. }
  639. /* Save the name locally */
  640. strncpy(priv->zone_name, name, THERMAL_NAME_LENGTH - 1);
  641. priv->zone_name[THERMAL_NAME_LENGTH - 1] = '\0';
  642. /* Then check there are no '-' or hwmon core will complain */
  643. do {
  644. insane_char = strpbrk(priv->zone_name, "-");
  645. if (insane_char)
  646. *insane_char = '_';
  647. } while (insane_char);
  648. }
  649. /*
  650. * The IP can manage to trigger interrupts on overheat situation from all the
  651. * sensors. However, the interrupt source changes along with the last selected
  652. * source (ie. the last read sensor), which is an inconsistent behavior. Avoid
  653. * possible glitches by always selecting back only one channel (arbitrarily: the
  654. * first in the DT which has a critical trip point). We also disable sensor
  655. * switch during overheat situations.
  656. */
  657. static int armada_configure_overheat_int(struct armada_thermal_priv *priv,
  658. struct thermal_zone_device *tz,
  659. int sensor_id)
  660. {
  661. /* Retrieve the critical trip point to enable the overheat interrupt */
  662. const struct thermal_trip *trips = of_thermal_get_trip_points(tz);
  663. int ret;
  664. int i;
  665. if (!trips)
  666. return -EINVAL;
  667. for (i = 0; i < of_thermal_get_ntrips(tz); i++)
  668. if (trips[i].type == THERMAL_TRIP_CRITICAL)
  669. break;
  670. if (i == of_thermal_get_ntrips(tz))
  671. return -EINVAL;
  672. ret = armada_select_channel(priv, sensor_id);
  673. if (ret)
  674. return ret;
  675. armada_set_overheat_thresholds(priv,
  676. trips[i].temperature,
  677. trips[i].hysteresis);
  678. priv->overheat_sensor = tz;
  679. priv->interrupt_source = sensor_id;
  680. armada_enable_overheat_interrupt(priv);
  681. return 0;
  682. }
  683. static int armada_thermal_probe(struct platform_device *pdev)
  684. {
  685. struct thermal_zone_device *tz;
  686. struct armada_thermal_sensor *sensor;
  687. struct armada_drvdata *drvdata;
  688. const struct of_device_id *match;
  689. struct armada_thermal_priv *priv;
  690. int sensor_id, irq;
  691. int ret;
  692. match = of_match_device(armada_thermal_id_table, &pdev->dev);
  693. if (!match)
  694. return -ENODEV;
  695. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  696. if (!priv)
  697. return -ENOMEM;
  698. drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
  699. if (!drvdata)
  700. return -ENOMEM;
  701. priv->dev = &pdev->dev;
  702. priv->data = (struct armada_thermal_data *)match->data;
  703. mutex_init(&priv->update_lock);
  704. /*
  705. * Legacy DT bindings only described "control1" register (also referred
  706. * as "control MSB" on old documentation). Then, bindings moved to cover
  707. * "control0/control LSB" and "control1/control MSB" registers within
  708. * the same resource, which was then of size 8 instead of 4.
  709. *
  710. * The logic of defining sporadic registers is broken. For instance, it
  711. * blocked the addition of the overheat interrupt feature that needed
  712. * another resource somewhere else in the same memory area. One solution
  713. * is to define an overall system controller and put the thermal node
  714. * into it, which requires the use of regmaps across all the driver.
  715. */
  716. if (IS_ERR(syscon_node_to_regmap(pdev->dev.parent->of_node))) {
  717. /* Ensure device name is correct for the thermal core */
  718. armada_set_sane_name(pdev, priv);
  719. ret = armada_thermal_probe_legacy(pdev, priv);
  720. if (ret)
  721. return ret;
  722. priv->data->init(pdev, priv);
  723. /* Wait the sensors to be valid */
  724. armada_wait_sensor_validity(priv);
  725. tz = thermal_zone_device_register(priv->zone_name, 0, 0, priv,
  726. &legacy_ops, NULL, 0, 0);
  727. if (IS_ERR(tz)) {
  728. dev_err(&pdev->dev,
  729. "Failed to register thermal zone device\n");
  730. return PTR_ERR(tz);
  731. }
  732. ret = thermal_zone_device_enable(tz);
  733. if (ret) {
  734. thermal_zone_device_unregister(tz);
  735. return ret;
  736. }
  737. drvdata->type = LEGACY;
  738. drvdata->data.tz = tz;
  739. platform_set_drvdata(pdev, drvdata);
  740. return 0;
  741. }
  742. ret = armada_thermal_probe_syscon(pdev, priv);
  743. if (ret)
  744. return ret;
  745. priv->current_channel = -1;
  746. priv->data->init(pdev, priv);
  747. drvdata->type = SYSCON;
  748. drvdata->data.priv = priv;
  749. platform_set_drvdata(pdev, drvdata);
  750. irq = platform_get_irq(pdev, 0);
  751. if (irq == -EPROBE_DEFER)
  752. return irq;
  753. /* The overheat interrupt feature is not mandatory */
  754. if (irq > 0) {
  755. ret = devm_request_threaded_irq(&pdev->dev, irq,
  756. armada_overheat_isr,
  757. armada_overheat_isr_thread,
  758. 0, NULL, priv);
  759. if (ret) {
  760. dev_err(&pdev->dev, "Cannot request threaded IRQ %d\n",
  761. irq);
  762. return ret;
  763. }
  764. }
  765. /*
  766. * There is one channel for the IC and one per CPU (if any), each
  767. * channel has one sensor.
  768. */
  769. for (sensor_id = 0; sensor_id <= priv->data->cpu_nr; sensor_id++) {
  770. sensor = devm_kzalloc(&pdev->dev,
  771. sizeof(struct armada_thermal_sensor),
  772. GFP_KERNEL);
  773. if (!sensor)
  774. return -ENOMEM;
  775. /* Register the sensor */
  776. sensor->priv = priv;
  777. sensor->id = sensor_id;
  778. tz = devm_thermal_zone_of_sensor_register(&pdev->dev,
  779. sensor->id, sensor,
  780. &of_ops);
  781. if (IS_ERR(tz)) {
  782. dev_info(&pdev->dev, "Thermal sensor %d unavailable\n",
  783. sensor_id);
  784. devm_kfree(&pdev->dev, sensor);
  785. continue;
  786. }
  787. /*
  788. * The first channel that has a critical trip point registered
  789. * in the DT will serve as interrupt source. Others possible
  790. * critical trip points will simply be ignored by the driver.
  791. */
  792. if (irq > 0 && !priv->overheat_sensor)
  793. armada_configure_overheat_int(priv, tz, sensor->id);
  794. }
  795. /* Just complain if no overheat interrupt was set up */
  796. if (!priv->overheat_sensor)
  797. dev_warn(&pdev->dev, "Overheat interrupt not available\n");
  798. return 0;
  799. }
  800. static int armada_thermal_exit(struct platform_device *pdev)
  801. {
  802. struct armada_drvdata *drvdata = platform_get_drvdata(pdev);
  803. if (drvdata->type == LEGACY)
  804. thermal_zone_device_unregister(drvdata->data.tz);
  805. return 0;
  806. }
  807. static struct platform_driver armada_thermal_driver = {
  808. .probe = armada_thermal_probe,
  809. .remove = armada_thermal_exit,
  810. .driver = {
  811. .name = "armada_thermal",
  812. .of_match_table = armada_thermal_id_table,
  813. },
  814. };
  815. module_platform_driver(armada_thermal_driver);
  816. MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@free-electrons.com>");
  817. MODULE_DESCRIPTION("Marvell EBU Armada SoCs thermal driver");
  818. MODULE_LICENSE("GPL v2");