spmi-pmic-arb.c 37 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2012-2015, 2017, 2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/bitmap.h>
  6. #include <linux/delay.h>
  7. #include <linux/err.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/io.h>
  10. #include <linux/irqchip/chained_irq.h>
  11. #include <linux/irqdomain.h>
  12. #include <linux/irq.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/spmi.h>
  19. /* PMIC Arbiter configuration registers */
  20. #define PMIC_ARB_VERSION 0x0000
  21. #define PMIC_ARB_VERSION_V2_MIN 0x20010000
  22. #define PMIC_ARB_VERSION_V3_MIN 0x30000000
  23. #define PMIC_ARB_VERSION_V5_MIN 0x50000000
  24. #define PMIC_ARB_INT_EN 0x0004
  25. /* PMIC Arbiter channel registers offsets */
  26. #define PMIC_ARB_CMD 0x00
  27. #define PMIC_ARB_CONFIG 0x04
  28. #define PMIC_ARB_STATUS 0x08
  29. #define PMIC_ARB_WDATA0 0x10
  30. #define PMIC_ARB_WDATA1 0x14
  31. #define PMIC_ARB_RDATA0 0x18
  32. #define PMIC_ARB_RDATA1 0x1C
  33. /* Mapping Table */
  34. #define SPMI_MAPPING_TABLE_REG(N) (0x0B00 + (4 * (N)))
  35. #define SPMI_MAPPING_BIT_INDEX(X) (((X) >> 18) & 0xF)
  36. #define SPMI_MAPPING_BIT_IS_0_FLAG(X) (((X) >> 17) & 0x1)
  37. #define SPMI_MAPPING_BIT_IS_0_RESULT(X) (((X) >> 9) & 0xFF)
  38. #define SPMI_MAPPING_BIT_IS_1_FLAG(X) (((X) >> 8) & 0x1)
  39. #define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF)
  40. #define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */
  41. #define PMIC_ARB_MAX_PPID BIT(12) /* PPID is 12bit */
  42. #define PMIC_ARB_APID_VALID BIT(15)
  43. #define PMIC_ARB_CHAN_IS_IRQ_OWNER(reg) ((reg) & BIT(24))
  44. #define INVALID_EE 0xFF
  45. /* Ownership Table */
  46. #define SPMI_OWNERSHIP_TABLE_REG(N) (0x0700 + (4 * (N)))
  47. #define SPMI_OWNERSHIP_PERIPH2OWNER(X) ((X) & 0x7)
  48. /* Channel Status fields */
  49. enum pmic_arb_chnl_status {
  50. PMIC_ARB_STATUS_DONE = BIT(0),
  51. PMIC_ARB_STATUS_FAILURE = BIT(1),
  52. PMIC_ARB_STATUS_DENIED = BIT(2),
  53. PMIC_ARB_STATUS_DROPPED = BIT(3),
  54. };
  55. /* Command register fields */
  56. #define PMIC_ARB_CMD_MAX_BYTE_COUNT 8
  57. /* Command Opcodes */
  58. enum pmic_arb_cmd_op_code {
  59. PMIC_ARB_OP_EXT_WRITEL = 0,
  60. PMIC_ARB_OP_EXT_READL = 1,
  61. PMIC_ARB_OP_EXT_WRITE = 2,
  62. PMIC_ARB_OP_RESET = 3,
  63. PMIC_ARB_OP_SLEEP = 4,
  64. PMIC_ARB_OP_SHUTDOWN = 5,
  65. PMIC_ARB_OP_WAKEUP = 6,
  66. PMIC_ARB_OP_AUTHENTICATE = 7,
  67. PMIC_ARB_OP_MSTR_READ = 8,
  68. PMIC_ARB_OP_MSTR_WRITE = 9,
  69. PMIC_ARB_OP_EXT_READ = 13,
  70. PMIC_ARB_OP_WRITE = 14,
  71. PMIC_ARB_OP_READ = 15,
  72. PMIC_ARB_OP_ZERO_WRITE = 16,
  73. };
  74. /*
  75. * PMIC arbiter version 5 uses different register offsets for read/write vs
  76. * observer channels.
  77. */
  78. enum pmic_arb_channel {
  79. PMIC_ARB_CHANNEL_RW,
  80. PMIC_ARB_CHANNEL_OBS,
  81. };
  82. /* Maximum number of support PMIC peripherals */
  83. #define PMIC_ARB_MAX_PERIPHS 512
  84. #define PMIC_ARB_TIMEOUT_US 100
  85. #define PMIC_ARB_MAX_TRANS_BYTES (8)
  86. #define PMIC_ARB_APID_MASK 0xFF
  87. #define PMIC_ARB_PPID_MASK 0xFFF
  88. /* interrupt enable bit */
  89. #define SPMI_PIC_ACC_ENABLE_BIT BIT(0)
  90. #define spec_to_hwirq(slave_id, periph_id, irq_id, apid) \
  91. ((((slave_id) & 0xF) << 28) | \
  92. (((periph_id) & 0xFF) << 20) | \
  93. (((irq_id) & 0x7) << 16) | \
  94. (((apid) & 0x1FF) << 0))
  95. #define hwirq_to_sid(hwirq) (((hwirq) >> 28) & 0xF)
  96. #define hwirq_to_per(hwirq) (((hwirq) >> 20) & 0xFF)
  97. #define hwirq_to_irq(hwirq) (((hwirq) >> 16) & 0x7)
  98. #define hwirq_to_apid(hwirq) (((hwirq) >> 0) & 0x1FF)
  99. struct pmic_arb_ver_ops;
  100. struct apid_data {
  101. u16 ppid;
  102. u8 write_ee;
  103. u8 irq_ee;
  104. };
  105. /**
  106. * spmi_pmic_arb - SPMI PMIC Arbiter object
  107. *
  108. * @rd_base: on v1 "core", on v2 "observer" register base off DT.
  109. * @wr_base: on v1 "core", on v2 "chnls" register base off DT.
  110. * @intr: address of the SPMI interrupt control registers.
  111. * @cnfg: address of the PMIC Arbiter configuration registers.
  112. * @lock: lock to synchronize accesses.
  113. * @channel: execution environment channel to use for accesses.
  114. * @irq: PMIC ARB interrupt.
  115. * @ee: the current Execution Environment
  116. * @min_apid: minimum APID (used for bounding IRQ search)
  117. * @max_apid: maximum APID
  118. * @mapping_table: in-memory copy of PPID -> APID mapping table.
  119. * @domain: irq domain object for PMIC IRQ domain
  120. * @spmic: SPMI controller object
  121. * @ver_ops: version dependent operations.
  122. * @ppid_to_apid in-memory copy of PPID -> APID mapping table.
  123. */
  124. struct spmi_pmic_arb {
  125. void __iomem *rd_base;
  126. void __iomem *wr_base;
  127. void __iomem *intr;
  128. void __iomem *cnfg;
  129. void __iomem *core;
  130. resource_size_t core_size;
  131. raw_spinlock_t lock;
  132. u8 channel;
  133. int irq;
  134. u8 ee;
  135. u16 min_apid;
  136. u16 max_apid;
  137. u32 *mapping_table;
  138. DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS);
  139. struct irq_domain *domain;
  140. struct spmi_controller *spmic;
  141. const struct pmic_arb_ver_ops *ver_ops;
  142. u16 *ppid_to_apid;
  143. u16 last_apid;
  144. struct apid_data apid_data[PMIC_ARB_MAX_PERIPHS];
  145. };
  146. /**
  147. * pmic_arb_ver: version dependent functionality.
  148. *
  149. * @ver_str: version string.
  150. * @ppid_to_apid: finds the apid for a given ppid.
  151. * @non_data_cmd: on v1 issues an spmi non-data command.
  152. * on v2 no HW support, returns -EOPNOTSUPP.
  153. * @offset: on v1 offset of per-ee channel.
  154. * on v2 offset of per-ee and per-ppid channel.
  155. * @fmt_cmd: formats a GENI/SPMI command.
  156. * @owner_acc_status: on v1 address of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn
  157. * on v2 address of SPMI_PIC_OWNERm_ACC_STATUSn.
  158. * @acc_enable: on v1 address of PMIC_ARB_SPMI_PIC_ACC_ENABLEn
  159. * on v2 address of SPMI_PIC_ACC_ENABLEn.
  160. * @irq_status: on v1 address of PMIC_ARB_SPMI_PIC_IRQ_STATUSn
  161. * on v2 address of SPMI_PIC_IRQ_STATUSn.
  162. * @irq_clear: on v1 address of PMIC_ARB_SPMI_PIC_IRQ_CLEARn
  163. * on v2 address of SPMI_PIC_IRQ_CLEARn.
  164. * @apid_map_offset: offset of PMIC_ARB_REG_CHNLn
  165. */
  166. struct pmic_arb_ver_ops {
  167. const char *ver_str;
  168. int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid);
  169. /* spmi commands (read_cmd, write_cmd, cmd) functionality */
  170. int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
  171. enum pmic_arb_channel ch_type);
  172. u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc);
  173. int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid);
  174. /* Interrupts controller functionality (offset of PIC registers) */
  175. void __iomem *(*owner_acc_status)(struct spmi_pmic_arb *pmic_arb, u8 m,
  176. u16 n);
  177. void __iomem *(*acc_enable)(struct spmi_pmic_arb *pmic_arb, u16 n);
  178. void __iomem *(*irq_status)(struct spmi_pmic_arb *pmic_arb, u16 n);
  179. void __iomem *(*irq_clear)(struct spmi_pmic_arb *pmic_arb, u16 n);
  180. u32 (*apid_map_offset)(u16 n);
  181. };
  182. static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb,
  183. u32 offset, u32 val)
  184. {
  185. writel_relaxed(val, pmic_arb->wr_base + offset);
  186. }
  187. static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pmic_arb,
  188. u32 offset, u32 val)
  189. {
  190. writel_relaxed(val, pmic_arb->rd_base + offset);
  191. }
  192. /**
  193. * pmic_arb_read_data: reads pmic-arb's register and copy 1..4 bytes to buf
  194. * @bc: byte count -1. range: 0..3
  195. * @reg: register's address
  196. * @buf: output parameter, length must be bc + 1
  197. */
  198. static void
  199. pmic_arb_read_data(struct spmi_pmic_arb *pmic_arb, u8 *buf, u32 reg, u8 bc)
  200. {
  201. u32 data = __raw_readl(pmic_arb->rd_base + reg);
  202. memcpy(buf, &data, (bc & 3) + 1);
  203. }
  204. /**
  205. * pmic_arb_write_data: write 1..4 bytes from buf to pmic-arb's register
  206. * @bc: byte-count -1. range: 0..3.
  207. * @reg: register's address.
  208. * @buf: buffer to write. length must be bc + 1.
  209. */
  210. static void pmic_arb_write_data(struct spmi_pmic_arb *pmic_arb, const u8 *buf,
  211. u32 reg, u8 bc)
  212. {
  213. u32 data = 0;
  214. memcpy(&data, buf, (bc & 3) + 1);
  215. __raw_writel(data, pmic_arb->wr_base + reg);
  216. }
  217. static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
  218. void __iomem *base, u8 sid, u16 addr,
  219. enum pmic_arb_channel ch_type)
  220. {
  221. struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
  222. u32 status = 0;
  223. u32 timeout = PMIC_ARB_TIMEOUT_US;
  224. u32 offset;
  225. int rc;
  226. rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr, ch_type);
  227. if (rc < 0)
  228. return rc;
  229. offset = rc;
  230. offset += PMIC_ARB_STATUS;
  231. while (timeout--) {
  232. status = readl_relaxed(base + offset);
  233. if (status & PMIC_ARB_STATUS_DONE) {
  234. if (status & PMIC_ARB_STATUS_DENIED) {
  235. dev_err(&ctrl->dev, "%s: transaction denied (0x%x)\n",
  236. __func__, status);
  237. return -EPERM;
  238. }
  239. if (status & PMIC_ARB_STATUS_FAILURE) {
  240. dev_err(&ctrl->dev, "%s: transaction failed (0x%x)\n",
  241. __func__, status);
  242. return -EIO;
  243. }
  244. if (status & PMIC_ARB_STATUS_DROPPED) {
  245. dev_err(&ctrl->dev, "%s: transaction dropped (0x%x)\n",
  246. __func__, status);
  247. return -EIO;
  248. }
  249. return 0;
  250. }
  251. udelay(1);
  252. }
  253. dev_err(&ctrl->dev, "%s: timeout, status 0x%x\n",
  254. __func__, status);
  255. return -ETIMEDOUT;
  256. }
  257. static int
  258. pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid)
  259. {
  260. struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
  261. unsigned long flags;
  262. u32 cmd;
  263. int rc;
  264. u32 offset;
  265. rc = pmic_arb->ver_ops->offset(pmic_arb, sid, 0, PMIC_ARB_CHANNEL_RW);
  266. if (rc < 0)
  267. return rc;
  268. offset = rc;
  269. cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20);
  270. raw_spin_lock_irqsave(&pmic_arb->lock, flags);
  271. pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
  272. rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0,
  273. PMIC_ARB_CHANNEL_RW);
  274. raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
  275. return rc;
  276. }
  277. static int
  278. pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid)
  279. {
  280. return -EOPNOTSUPP;
  281. }
  282. /* Non-data command */
  283. static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
  284. {
  285. struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
  286. dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid);
  287. /* Check for valid non-data command */
  288. if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
  289. return -EINVAL;
  290. return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid);
  291. }
  292. static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
  293. u16 addr, u8 *buf, size_t len)
  294. {
  295. struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
  296. unsigned long flags;
  297. u8 bc = len - 1;
  298. u32 cmd;
  299. int rc;
  300. u32 offset;
  301. rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
  302. PMIC_ARB_CHANNEL_OBS);
  303. if (rc < 0)
  304. return rc;
  305. offset = rc;
  306. if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
  307. dev_err(&ctrl->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
  308. PMIC_ARB_MAX_TRANS_BYTES, len);
  309. return -EINVAL;
  310. }
  311. /* Check the opcode */
  312. if (opc >= 0x60 && opc <= 0x7F)
  313. opc = PMIC_ARB_OP_READ;
  314. else if (opc >= 0x20 && opc <= 0x2F)
  315. opc = PMIC_ARB_OP_EXT_READ;
  316. else if (opc >= 0x38 && opc <= 0x3F)
  317. opc = PMIC_ARB_OP_EXT_READL;
  318. else
  319. return -EINVAL;
  320. cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
  321. raw_spin_lock_irqsave(&pmic_arb->lock, flags);
  322. pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd);
  323. rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr,
  324. PMIC_ARB_CHANNEL_OBS);
  325. if (rc)
  326. goto done;
  327. pmic_arb_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0,
  328. min_t(u8, bc, 3));
  329. if (bc > 3)
  330. pmic_arb_read_data(pmic_arb, buf + 4, offset + PMIC_ARB_RDATA1,
  331. bc - 4);
  332. done:
  333. raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
  334. return rc;
  335. }
  336. static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
  337. u16 addr, const u8 *buf, size_t len)
  338. {
  339. struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
  340. unsigned long flags;
  341. u8 bc = len - 1;
  342. u32 cmd;
  343. int rc;
  344. u32 offset;
  345. rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
  346. PMIC_ARB_CHANNEL_RW);
  347. if (rc < 0)
  348. return rc;
  349. offset = rc;
  350. if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
  351. dev_err(&ctrl->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
  352. PMIC_ARB_MAX_TRANS_BYTES, len);
  353. return -EINVAL;
  354. }
  355. /* Check the opcode */
  356. if (opc >= 0x40 && opc <= 0x5F)
  357. opc = PMIC_ARB_OP_WRITE;
  358. else if (opc <= 0x0F)
  359. opc = PMIC_ARB_OP_EXT_WRITE;
  360. else if (opc >= 0x30 && opc <= 0x37)
  361. opc = PMIC_ARB_OP_EXT_WRITEL;
  362. else if (opc >= 0x80)
  363. opc = PMIC_ARB_OP_ZERO_WRITE;
  364. else
  365. return -EINVAL;
  366. cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
  367. /* Write data to FIFOs */
  368. raw_spin_lock_irqsave(&pmic_arb->lock, flags);
  369. pmic_arb_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0,
  370. min_t(u8, bc, 3));
  371. if (bc > 3)
  372. pmic_arb_write_data(pmic_arb, buf + 4, offset + PMIC_ARB_WDATA1,
  373. bc - 4);
  374. /* Start the transaction */
  375. pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
  376. rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr,
  377. PMIC_ARB_CHANNEL_RW);
  378. raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
  379. return rc;
  380. }
  381. enum qpnpint_regs {
  382. QPNPINT_REG_RT_STS = 0x10,
  383. QPNPINT_REG_SET_TYPE = 0x11,
  384. QPNPINT_REG_POLARITY_HIGH = 0x12,
  385. QPNPINT_REG_POLARITY_LOW = 0x13,
  386. QPNPINT_REG_LATCHED_CLR = 0x14,
  387. QPNPINT_REG_EN_SET = 0x15,
  388. QPNPINT_REG_EN_CLR = 0x16,
  389. QPNPINT_REG_LATCHED_STS = 0x18,
  390. };
  391. struct spmi_pmic_arb_qpnpint_type {
  392. u8 type; /* 1 -> edge */
  393. u8 polarity_high;
  394. u8 polarity_low;
  395. } __packed;
  396. /* Simplified accessor functions for irqchip callbacks */
  397. static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
  398. size_t len)
  399. {
  400. struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
  401. u8 sid = hwirq_to_sid(d->hwirq);
  402. u8 per = hwirq_to_per(d->hwirq);
  403. if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
  404. (per << 8) + reg, buf, len))
  405. dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
  406. d->irq);
  407. }
  408. static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)
  409. {
  410. struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
  411. u8 sid = hwirq_to_sid(d->hwirq);
  412. u8 per = hwirq_to_per(d->hwirq);
  413. if (pmic_arb_read_cmd(pmic_arb->spmic, SPMI_CMD_EXT_READL, sid,
  414. (per << 8) + reg, buf, len))
  415. dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
  416. d->irq);
  417. }
  418. static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id)
  419. {
  420. u16 ppid = pmic_arb->apid_data[apid].ppid;
  421. u8 sid = ppid >> 8;
  422. u8 per = ppid & 0xFF;
  423. u8 irq_mask = BIT(id);
  424. writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
  425. if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
  426. (per << 8) + QPNPINT_REG_LATCHED_CLR, &irq_mask, 1))
  427. dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n",
  428. irq_mask, ppid);
  429. if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
  430. (per << 8) + QPNPINT_REG_EN_CLR, &irq_mask, 1))
  431. dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n",
  432. irq_mask, ppid);
  433. }
  434. static void periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid)
  435. {
  436. unsigned int irq;
  437. u32 status, id;
  438. u8 sid = (pmic_arb->apid_data[apid].ppid >> 8) & 0xF;
  439. u8 per = pmic_arb->apid_data[apid].ppid & 0xFF;
  440. status = readl_relaxed(pmic_arb->ver_ops->irq_status(pmic_arb, apid));
  441. while (status) {
  442. id = ffs(status) - 1;
  443. status &= ~BIT(id);
  444. irq = irq_find_mapping(pmic_arb->domain,
  445. spec_to_hwirq(sid, per, id, apid));
  446. if (irq == 0) {
  447. cleanup_irq(pmic_arb, apid, id);
  448. continue;
  449. }
  450. generic_handle_irq(irq);
  451. }
  452. }
  453. static void pmic_arb_chained_irq(struct irq_desc *desc)
  454. {
  455. struct spmi_pmic_arb *pmic_arb = irq_desc_get_handler_data(desc);
  456. const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
  457. struct irq_chip *chip = irq_desc_get_chip(desc);
  458. int first = pmic_arb->min_apid >> 5;
  459. int last = pmic_arb->max_apid >> 5;
  460. u8 ee = pmic_arb->ee;
  461. u32 status, enable;
  462. int i, id, apid;
  463. chained_irq_enter(chip, desc);
  464. for (i = first; i <= last; ++i) {
  465. status = readl_relaxed(
  466. ver_ops->owner_acc_status(pmic_arb, ee, i));
  467. while (status) {
  468. id = ffs(status) - 1;
  469. status &= ~BIT(id);
  470. apid = id + i * 32;
  471. enable = readl_relaxed(
  472. ver_ops->acc_enable(pmic_arb, apid));
  473. if (enable & SPMI_PIC_ACC_ENABLE_BIT)
  474. periph_interrupt(pmic_arb, apid);
  475. }
  476. }
  477. chained_irq_exit(chip, desc);
  478. }
  479. static void qpnpint_irq_ack(struct irq_data *d)
  480. {
  481. struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
  482. u8 irq = hwirq_to_irq(d->hwirq);
  483. u16 apid = hwirq_to_apid(d->hwirq);
  484. u8 data;
  485. writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
  486. data = BIT(irq);
  487. qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
  488. }
  489. static void qpnpint_irq_mask(struct irq_data *d)
  490. {
  491. u8 irq = hwirq_to_irq(d->hwirq);
  492. u8 data = BIT(irq);
  493. qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1);
  494. }
  495. static void qpnpint_irq_unmask(struct irq_data *d)
  496. {
  497. struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
  498. const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
  499. u8 irq = hwirq_to_irq(d->hwirq);
  500. u16 apid = hwirq_to_apid(d->hwirq);
  501. u8 buf[2];
  502. writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT,
  503. ver_ops->acc_enable(pmic_arb, apid));
  504. qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1);
  505. if (!(buf[0] & BIT(irq))) {
  506. /*
  507. * Since the interrupt is currently disabled, write to both the
  508. * LATCHED_CLR and EN_SET registers so that a spurious interrupt
  509. * cannot be triggered when the interrupt is enabled
  510. */
  511. buf[0] = BIT(irq);
  512. buf[1] = BIT(irq);
  513. qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 2);
  514. }
  515. }
  516. static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type)
  517. {
  518. struct spmi_pmic_arb_qpnpint_type type;
  519. irq_flow_handler_t flow_handler;
  520. u8 irq = hwirq_to_irq(d->hwirq);
  521. qpnpint_spmi_read(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
  522. if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
  523. type.type |= BIT(irq);
  524. if (flow_type & IRQF_TRIGGER_RISING)
  525. type.polarity_high |= BIT(irq);
  526. if (flow_type & IRQF_TRIGGER_FALLING)
  527. type.polarity_low |= BIT(irq);
  528. flow_handler = handle_edge_irq;
  529. } else {
  530. if ((flow_type & (IRQF_TRIGGER_HIGH)) &&
  531. (flow_type & (IRQF_TRIGGER_LOW)))
  532. return -EINVAL;
  533. type.type &= ~BIT(irq); /* level trig */
  534. if (flow_type & IRQF_TRIGGER_HIGH)
  535. type.polarity_high |= BIT(irq);
  536. else
  537. type.polarity_low |= BIT(irq);
  538. flow_handler = handle_level_irq;
  539. }
  540. qpnpint_spmi_write(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
  541. irq_set_handler_locked(d, flow_handler);
  542. return 0;
  543. }
  544. static int qpnpint_irq_set_wake(struct irq_data *d, unsigned int on)
  545. {
  546. struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
  547. return irq_set_irq_wake(pmic_arb->irq, on);
  548. }
  549. static int qpnpint_get_irqchip_state(struct irq_data *d,
  550. enum irqchip_irq_state which,
  551. bool *state)
  552. {
  553. u8 irq = hwirq_to_irq(d->hwirq);
  554. u8 status = 0;
  555. if (which != IRQCHIP_STATE_LINE_LEVEL)
  556. return -EINVAL;
  557. qpnpint_spmi_read(d, QPNPINT_REG_RT_STS, &status, 1);
  558. *state = !!(status & BIT(irq));
  559. return 0;
  560. }
  561. static int qpnpint_irq_domain_activate(struct irq_domain *domain,
  562. struct irq_data *d, bool reserve)
  563. {
  564. struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
  565. u16 periph = hwirq_to_per(d->hwirq);
  566. u16 apid = hwirq_to_apid(d->hwirq);
  567. u16 sid = hwirq_to_sid(d->hwirq);
  568. u16 irq = hwirq_to_irq(d->hwirq);
  569. if (pmic_arb->apid_data[apid].irq_ee != pmic_arb->ee) {
  570. dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n",
  571. sid, periph, irq, pmic_arb->ee,
  572. pmic_arb->apid_data[apid].irq_ee);
  573. return -ENODEV;
  574. }
  575. return 0;
  576. }
  577. static struct irq_chip pmic_arb_irqchip = {
  578. .name = "pmic_arb",
  579. .irq_ack = qpnpint_irq_ack,
  580. .irq_mask = qpnpint_irq_mask,
  581. .irq_unmask = qpnpint_irq_unmask,
  582. .irq_set_type = qpnpint_irq_set_type,
  583. .irq_set_wake = qpnpint_irq_set_wake,
  584. .irq_get_irqchip_state = qpnpint_get_irqchip_state,
  585. .flags = IRQCHIP_MASK_ON_SUSPEND,
  586. };
  587. static int qpnpint_irq_domain_translate(struct irq_domain *d,
  588. struct irq_fwspec *fwspec,
  589. unsigned long *out_hwirq,
  590. unsigned int *out_type)
  591. {
  592. struct spmi_pmic_arb *pmic_arb = d->host_data;
  593. u32 *intspec = fwspec->param;
  594. u16 apid, ppid;
  595. int rc;
  596. dev_dbg(&pmic_arb->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
  597. intspec[0], intspec[1], intspec[2]);
  598. if (irq_domain_get_of_node(d) != pmic_arb->spmic->dev.of_node)
  599. return -EINVAL;
  600. if (fwspec->param_count != 4)
  601. return -EINVAL;
  602. if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7)
  603. return -EINVAL;
  604. ppid = intspec[0] << 8 | intspec[1];
  605. rc = pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid);
  606. if (rc < 0) {
  607. dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u rc = %d\n",
  608. intspec[0], intspec[1], intspec[2], rc);
  609. return rc;
  610. }
  611. apid = rc;
  612. /* Keep track of {max,min}_apid for bounding search during interrupt */
  613. if (apid > pmic_arb->max_apid)
  614. pmic_arb->max_apid = apid;
  615. if (apid < pmic_arb->min_apid)
  616. pmic_arb->min_apid = apid;
  617. *out_hwirq = spec_to_hwirq(intspec[0], intspec[1], intspec[2], apid);
  618. *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
  619. dev_dbg(&pmic_arb->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
  620. return 0;
  621. }
  622. static struct lock_class_key qpnpint_irq_lock_class, qpnpint_irq_request_class;
  623. static void qpnpint_irq_domain_map(struct spmi_pmic_arb *pmic_arb,
  624. struct irq_domain *domain, unsigned int virq,
  625. irq_hw_number_t hwirq, unsigned int type)
  626. {
  627. irq_flow_handler_t handler;
  628. dev_dbg(&pmic_arb->spmic->dev, "virq = %u, hwirq = %lu, type = %u\n",
  629. virq, hwirq, type);
  630. if (type & IRQ_TYPE_EDGE_BOTH)
  631. handler = handle_edge_irq;
  632. else
  633. handler = handle_level_irq;
  634. irq_set_lockdep_class(virq, &qpnpint_irq_lock_class,
  635. &qpnpint_irq_request_class);
  636. irq_domain_set_info(domain, virq, hwirq, &pmic_arb_irqchip, pmic_arb,
  637. handler, NULL, NULL);
  638. }
  639. static int qpnpint_irq_domain_alloc(struct irq_domain *domain,
  640. unsigned int virq, unsigned int nr_irqs,
  641. void *data)
  642. {
  643. struct spmi_pmic_arb *pmic_arb = domain->host_data;
  644. struct irq_fwspec *fwspec = data;
  645. irq_hw_number_t hwirq;
  646. unsigned int type;
  647. int ret, i;
  648. ret = qpnpint_irq_domain_translate(domain, fwspec, &hwirq, &type);
  649. if (ret)
  650. return ret;
  651. for (i = 0; i < nr_irqs; i++)
  652. qpnpint_irq_domain_map(pmic_arb, domain, virq + i, hwirq + i,
  653. type);
  654. return 0;
  655. }
  656. static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 ppid)
  657. {
  658. u32 *mapping_table = pmic_arb->mapping_table;
  659. int index = 0, i;
  660. u16 apid_valid;
  661. u16 apid;
  662. u32 data;
  663. apid_valid = pmic_arb->ppid_to_apid[ppid];
  664. if (apid_valid & PMIC_ARB_APID_VALID) {
  665. apid = apid_valid & ~PMIC_ARB_APID_VALID;
  666. return apid;
  667. }
  668. for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) {
  669. if (!test_and_set_bit(index, pmic_arb->mapping_table_valid))
  670. mapping_table[index] = readl_relaxed(pmic_arb->cnfg +
  671. SPMI_MAPPING_TABLE_REG(index));
  672. data = mapping_table[index];
  673. if (ppid & BIT(SPMI_MAPPING_BIT_INDEX(data))) {
  674. if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) {
  675. index = SPMI_MAPPING_BIT_IS_1_RESULT(data);
  676. } else {
  677. apid = SPMI_MAPPING_BIT_IS_1_RESULT(data);
  678. pmic_arb->ppid_to_apid[ppid]
  679. = apid | PMIC_ARB_APID_VALID;
  680. pmic_arb->apid_data[apid].ppid = ppid;
  681. return apid;
  682. }
  683. } else {
  684. if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) {
  685. index = SPMI_MAPPING_BIT_IS_0_RESULT(data);
  686. } else {
  687. apid = SPMI_MAPPING_BIT_IS_0_RESULT(data);
  688. pmic_arb->ppid_to_apid[ppid]
  689. = apid | PMIC_ARB_APID_VALID;
  690. pmic_arb->apid_data[apid].ppid = ppid;
  691. return apid;
  692. }
  693. }
  694. }
  695. return -ENODEV;
  696. }
  697. /* v1 offset per ee */
  698. static int pmic_arb_offset_v1(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
  699. enum pmic_arb_channel ch_type)
  700. {
  701. return 0x800 + 0x80 * pmic_arb->channel;
  702. }
  703. static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid)
  704. {
  705. struct apid_data *apidd = &pmic_arb->apid_data[pmic_arb->last_apid];
  706. u32 regval, offset;
  707. u16 id, apid;
  708. for (apid = pmic_arb->last_apid; ; apid++, apidd++) {
  709. offset = pmic_arb->ver_ops->apid_map_offset(apid);
  710. if (offset >= pmic_arb->core_size)
  711. break;
  712. regval = readl_relaxed(pmic_arb->cnfg +
  713. SPMI_OWNERSHIP_TABLE_REG(apid));
  714. apidd->irq_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
  715. apidd->write_ee = apidd->irq_ee;
  716. regval = readl_relaxed(pmic_arb->core + offset);
  717. if (!regval)
  718. continue;
  719. id = (regval >> 8) & PMIC_ARB_PPID_MASK;
  720. pmic_arb->ppid_to_apid[id] = apid | PMIC_ARB_APID_VALID;
  721. apidd->ppid = id;
  722. if (id == ppid) {
  723. apid |= PMIC_ARB_APID_VALID;
  724. break;
  725. }
  726. }
  727. pmic_arb->last_apid = apid & ~PMIC_ARB_APID_VALID;
  728. return apid;
  729. }
  730. static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pmic_arb, u16 ppid)
  731. {
  732. u16 apid_valid;
  733. apid_valid = pmic_arb->ppid_to_apid[ppid];
  734. if (!(apid_valid & PMIC_ARB_APID_VALID))
  735. apid_valid = pmic_arb_find_apid(pmic_arb, ppid);
  736. if (!(apid_valid & PMIC_ARB_APID_VALID))
  737. return -ENODEV;
  738. return apid_valid & ~PMIC_ARB_APID_VALID;
  739. }
  740. static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
  741. {
  742. struct apid_data *apidd = pmic_arb->apid_data;
  743. struct apid_data *prev_apidd;
  744. u16 i, apid, ppid;
  745. bool valid, is_irq_ee;
  746. u32 regval, offset;
  747. /*
  748. * In order to allow multiple EEs to write to a single PPID in arbiter
  749. * version 5, there is more than one APID mapped to each PPID.
  750. * The owner field for each of these mappings specifies the EE which is
  751. * allowed to write to the APID. The owner of the last (highest) APID
  752. * for a given PPID will receive interrupts from the PPID.
  753. */
  754. for (i = 0; ; i++, apidd++) {
  755. offset = pmic_arb->ver_ops->apid_map_offset(i);
  756. if (offset >= pmic_arb->core_size)
  757. break;
  758. regval = readl_relaxed(pmic_arb->core + offset);
  759. if (!regval)
  760. continue;
  761. ppid = (regval >> 8) & PMIC_ARB_PPID_MASK;
  762. is_irq_ee = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval);
  763. regval = readl_relaxed(pmic_arb->cnfg +
  764. SPMI_OWNERSHIP_TABLE_REG(i));
  765. apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
  766. apidd->irq_ee = is_irq_ee ? apidd->write_ee : INVALID_EE;
  767. valid = pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID;
  768. apid = pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
  769. prev_apidd = &pmic_arb->apid_data[apid];
  770. if (valid && is_irq_ee &&
  771. prev_apidd->write_ee == pmic_arb->ee) {
  772. /*
  773. * Duplicate PPID mapping after the one for this EE;
  774. * override the irq owner
  775. */
  776. prev_apidd->irq_ee = apidd->irq_ee;
  777. } else if (!valid || is_irq_ee) {
  778. /* First PPID mapping or duplicate for another EE */
  779. pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID;
  780. }
  781. apidd->ppid = ppid;
  782. pmic_arb->last_apid = i;
  783. }
  784. /* Dump the mapping table for debug purposes. */
  785. dev_dbg(&pmic_arb->spmic->dev, "PPID APID Write-EE IRQ-EE\n");
  786. for (ppid = 0; ppid < PMIC_ARB_MAX_PPID; ppid++) {
  787. apid = pmic_arb->ppid_to_apid[ppid];
  788. if (apid & PMIC_ARB_APID_VALID) {
  789. apid &= ~PMIC_ARB_APID_VALID;
  790. apidd = &pmic_arb->apid_data[apid];
  791. dev_dbg(&pmic_arb->spmic->dev, "%#03X %3u %2u %2u\n",
  792. ppid, apid, apidd->write_ee, apidd->irq_ee);
  793. }
  794. }
  795. return 0;
  796. }
  797. static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb *pmic_arb, u16 ppid)
  798. {
  799. if (!(pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID))
  800. return -ENODEV;
  801. return pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
  802. }
  803. /* v2 offset per ppid and per ee */
  804. static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
  805. enum pmic_arb_channel ch_type)
  806. {
  807. u16 apid;
  808. u16 ppid;
  809. int rc;
  810. ppid = sid << 8 | ((addr >> 8) & 0xFF);
  811. rc = pmic_arb_ppid_to_apid_v2(pmic_arb, ppid);
  812. if (rc < 0)
  813. return rc;
  814. apid = rc;
  815. return 0x1000 * pmic_arb->ee + 0x8000 * apid;
  816. }
  817. /*
  818. * v5 offset per ee and per apid for observer channels and per apid for
  819. * read/write channels.
  820. */
  821. static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
  822. enum pmic_arb_channel ch_type)
  823. {
  824. u16 apid;
  825. int rc;
  826. u32 offset = 0;
  827. u16 ppid = (sid << 8) | (addr >> 8);
  828. rc = pmic_arb_ppid_to_apid_v5(pmic_arb, ppid);
  829. if (rc < 0)
  830. return rc;
  831. apid = rc;
  832. switch (ch_type) {
  833. case PMIC_ARB_CHANNEL_OBS:
  834. offset = 0x10000 * pmic_arb->ee + 0x80 * apid;
  835. break;
  836. case PMIC_ARB_CHANNEL_RW:
  837. offset = 0x10000 * apid;
  838. break;
  839. }
  840. return offset;
  841. }
  842. static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc)
  843. {
  844. return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7);
  845. }
  846. static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc)
  847. {
  848. return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7);
  849. }
  850. static void __iomem *
  851. pmic_arb_owner_acc_status_v1(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
  852. {
  853. return pmic_arb->intr + 0x20 * m + 0x4 * n;
  854. }
  855. static void __iomem *
  856. pmic_arb_owner_acc_status_v2(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
  857. {
  858. return pmic_arb->intr + 0x100000 + 0x1000 * m + 0x4 * n;
  859. }
  860. static void __iomem *
  861. pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
  862. {
  863. return pmic_arb->intr + 0x200000 + 0x1000 * m + 0x4 * n;
  864. }
  865. static void __iomem *
  866. pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
  867. {
  868. return pmic_arb->intr + 0x10000 * m + 0x4 * n;
  869. }
  870. static void __iomem *
  871. pmic_arb_acc_enable_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
  872. {
  873. return pmic_arb->intr + 0x200 + 0x4 * n;
  874. }
  875. static void __iomem *
  876. pmic_arb_acc_enable_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
  877. {
  878. return pmic_arb->intr + 0x1000 * n;
  879. }
  880. static void __iomem *
  881. pmic_arb_acc_enable_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
  882. {
  883. return pmic_arb->wr_base + 0x100 + 0x10000 * n;
  884. }
  885. static void __iomem *
  886. pmic_arb_irq_status_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
  887. {
  888. return pmic_arb->intr + 0x600 + 0x4 * n;
  889. }
  890. static void __iomem *
  891. pmic_arb_irq_status_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
  892. {
  893. return pmic_arb->intr + 0x4 + 0x1000 * n;
  894. }
  895. static void __iomem *
  896. pmic_arb_irq_status_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
  897. {
  898. return pmic_arb->wr_base + 0x104 + 0x10000 * n;
  899. }
  900. static void __iomem *
  901. pmic_arb_irq_clear_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
  902. {
  903. return pmic_arb->intr + 0xA00 + 0x4 * n;
  904. }
  905. static void __iomem *
  906. pmic_arb_irq_clear_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
  907. {
  908. return pmic_arb->intr + 0x8 + 0x1000 * n;
  909. }
  910. static void __iomem *
  911. pmic_arb_irq_clear_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
  912. {
  913. return pmic_arb->wr_base + 0x108 + 0x10000 * n;
  914. }
  915. static u32 pmic_arb_apid_map_offset_v2(u16 n)
  916. {
  917. return 0x800 + 0x4 * n;
  918. }
  919. static u32 pmic_arb_apid_map_offset_v5(u16 n)
  920. {
  921. return 0x900 + 0x4 * n;
  922. }
  923. static const struct pmic_arb_ver_ops pmic_arb_v1 = {
  924. .ver_str = "v1",
  925. .ppid_to_apid = pmic_arb_ppid_to_apid_v1,
  926. .non_data_cmd = pmic_arb_non_data_cmd_v1,
  927. .offset = pmic_arb_offset_v1,
  928. .fmt_cmd = pmic_arb_fmt_cmd_v1,
  929. .owner_acc_status = pmic_arb_owner_acc_status_v1,
  930. .acc_enable = pmic_arb_acc_enable_v1,
  931. .irq_status = pmic_arb_irq_status_v1,
  932. .irq_clear = pmic_arb_irq_clear_v1,
  933. .apid_map_offset = pmic_arb_apid_map_offset_v2,
  934. };
  935. static const struct pmic_arb_ver_ops pmic_arb_v2 = {
  936. .ver_str = "v2",
  937. .ppid_to_apid = pmic_arb_ppid_to_apid_v2,
  938. .non_data_cmd = pmic_arb_non_data_cmd_v2,
  939. .offset = pmic_arb_offset_v2,
  940. .fmt_cmd = pmic_arb_fmt_cmd_v2,
  941. .owner_acc_status = pmic_arb_owner_acc_status_v2,
  942. .acc_enable = pmic_arb_acc_enable_v2,
  943. .irq_status = pmic_arb_irq_status_v2,
  944. .irq_clear = pmic_arb_irq_clear_v2,
  945. .apid_map_offset = pmic_arb_apid_map_offset_v2,
  946. };
  947. static const struct pmic_arb_ver_ops pmic_arb_v3 = {
  948. .ver_str = "v3",
  949. .ppid_to_apid = pmic_arb_ppid_to_apid_v2,
  950. .non_data_cmd = pmic_arb_non_data_cmd_v2,
  951. .offset = pmic_arb_offset_v2,
  952. .fmt_cmd = pmic_arb_fmt_cmd_v2,
  953. .owner_acc_status = pmic_arb_owner_acc_status_v3,
  954. .acc_enable = pmic_arb_acc_enable_v2,
  955. .irq_status = pmic_arb_irq_status_v2,
  956. .irq_clear = pmic_arb_irq_clear_v2,
  957. .apid_map_offset = pmic_arb_apid_map_offset_v2,
  958. };
  959. static const struct pmic_arb_ver_ops pmic_arb_v5 = {
  960. .ver_str = "v5",
  961. .ppid_to_apid = pmic_arb_ppid_to_apid_v5,
  962. .non_data_cmd = pmic_arb_non_data_cmd_v2,
  963. .offset = pmic_arb_offset_v5,
  964. .fmt_cmd = pmic_arb_fmt_cmd_v2,
  965. .owner_acc_status = pmic_arb_owner_acc_status_v5,
  966. .acc_enable = pmic_arb_acc_enable_v5,
  967. .irq_status = pmic_arb_irq_status_v5,
  968. .irq_clear = pmic_arb_irq_clear_v5,
  969. .apid_map_offset = pmic_arb_apid_map_offset_v5,
  970. };
  971. static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
  972. .activate = qpnpint_irq_domain_activate,
  973. .alloc = qpnpint_irq_domain_alloc,
  974. .free = irq_domain_free_irqs_common,
  975. .translate = qpnpint_irq_domain_translate,
  976. };
  977. static int spmi_pmic_arb_probe(struct platform_device *pdev)
  978. {
  979. struct spmi_pmic_arb *pmic_arb;
  980. struct spmi_controller *ctrl;
  981. struct resource *res;
  982. void __iomem *core;
  983. u32 *mapping_table;
  984. u32 channel, ee, hw_ver;
  985. int err;
  986. ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pmic_arb));
  987. if (!ctrl)
  988. return -ENOMEM;
  989. pmic_arb = spmi_controller_get_drvdata(ctrl);
  990. pmic_arb->spmic = ctrl;
  991. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
  992. core = devm_ioremap_resource(&ctrl->dev, res);
  993. if (IS_ERR(core)) {
  994. err = PTR_ERR(core);
  995. goto err_put_ctrl;
  996. }
  997. pmic_arb->core_size = resource_size(res);
  998. pmic_arb->ppid_to_apid = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PPID,
  999. sizeof(*pmic_arb->ppid_to_apid),
  1000. GFP_KERNEL);
  1001. if (!pmic_arb->ppid_to_apid) {
  1002. err = -ENOMEM;
  1003. goto err_put_ctrl;
  1004. }
  1005. hw_ver = readl_relaxed(core + PMIC_ARB_VERSION);
  1006. if (hw_ver < PMIC_ARB_VERSION_V2_MIN) {
  1007. pmic_arb->ver_ops = &pmic_arb_v1;
  1008. pmic_arb->wr_base = core;
  1009. pmic_arb->rd_base = core;
  1010. } else {
  1011. pmic_arb->core = core;
  1012. if (hw_ver < PMIC_ARB_VERSION_V3_MIN)
  1013. pmic_arb->ver_ops = &pmic_arb_v2;
  1014. else if (hw_ver < PMIC_ARB_VERSION_V5_MIN)
  1015. pmic_arb->ver_ops = &pmic_arb_v3;
  1016. else
  1017. pmic_arb->ver_ops = &pmic_arb_v5;
  1018. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1019. "obsrvr");
  1020. pmic_arb->rd_base = devm_ioremap_resource(&ctrl->dev, res);
  1021. if (IS_ERR(pmic_arb->rd_base)) {
  1022. err = PTR_ERR(pmic_arb->rd_base);
  1023. goto err_put_ctrl;
  1024. }
  1025. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1026. "chnls");
  1027. pmic_arb->wr_base = devm_ioremap_resource(&ctrl->dev, res);
  1028. if (IS_ERR(pmic_arb->wr_base)) {
  1029. err = PTR_ERR(pmic_arb->wr_base);
  1030. goto err_put_ctrl;
  1031. }
  1032. }
  1033. dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n",
  1034. pmic_arb->ver_ops->ver_str, hw_ver);
  1035. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr");
  1036. pmic_arb->intr = devm_ioremap_resource(&ctrl->dev, res);
  1037. if (IS_ERR(pmic_arb->intr)) {
  1038. err = PTR_ERR(pmic_arb->intr);
  1039. goto err_put_ctrl;
  1040. }
  1041. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cnfg");
  1042. pmic_arb->cnfg = devm_ioremap_resource(&ctrl->dev, res);
  1043. if (IS_ERR(pmic_arb->cnfg)) {
  1044. err = PTR_ERR(pmic_arb->cnfg);
  1045. goto err_put_ctrl;
  1046. }
  1047. pmic_arb->irq = platform_get_irq_byname(pdev, "periph_irq");
  1048. if (pmic_arb->irq < 0) {
  1049. err = pmic_arb->irq;
  1050. goto err_put_ctrl;
  1051. }
  1052. err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel);
  1053. if (err) {
  1054. dev_err(&pdev->dev, "channel unspecified.\n");
  1055. goto err_put_ctrl;
  1056. }
  1057. if (channel > 5) {
  1058. dev_err(&pdev->dev, "invalid channel (%u) specified.\n",
  1059. channel);
  1060. err = -EINVAL;
  1061. goto err_put_ctrl;
  1062. }
  1063. pmic_arb->channel = channel;
  1064. err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee);
  1065. if (err) {
  1066. dev_err(&pdev->dev, "EE unspecified.\n");
  1067. goto err_put_ctrl;
  1068. }
  1069. if (ee > 5) {
  1070. dev_err(&pdev->dev, "invalid EE (%u) specified\n", ee);
  1071. err = -EINVAL;
  1072. goto err_put_ctrl;
  1073. }
  1074. pmic_arb->ee = ee;
  1075. mapping_table = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PERIPHS,
  1076. sizeof(*mapping_table), GFP_KERNEL);
  1077. if (!mapping_table) {
  1078. err = -ENOMEM;
  1079. goto err_put_ctrl;
  1080. }
  1081. pmic_arb->mapping_table = mapping_table;
  1082. /* Initialize max_apid/min_apid to the opposite bounds, during
  1083. * the irq domain translation, we are sure to update these */
  1084. pmic_arb->max_apid = 0;
  1085. pmic_arb->min_apid = PMIC_ARB_MAX_PERIPHS - 1;
  1086. platform_set_drvdata(pdev, ctrl);
  1087. raw_spin_lock_init(&pmic_arb->lock);
  1088. ctrl->cmd = pmic_arb_cmd;
  1089. ctrl->read_cmd = pmic_arb_read_cmd;
  1090. ctrl->write_cmd = pmic_arb_write_cmd;
  1091. if (hw_ver >= PMIC_ARB_VERSION_V5_MIN) {
  1092. err = pmic_arb_read_apid_map_v5(pmic_arb);
  1093. if (err) {
  1094. dev_err(&pdev->dev, "could not read APID->PPID mapping table, rc= %d\n",
  1095. err);
  1096. goto err_put_ctrl;
  1097. }
  1098. }
  1099. dev_dbg(&pdev->dev, "adding irq domain\n");
  1100. pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node,
  1101. &pmic_arb_irq_domain_ops, pmic_arb);
  1102. if (!pmic_arb->domain) {
  1103. dev_err(&pdev->dev, "unable to create irq_domain\n");
  1104. err = -ENOMEM;
  1105. goto err_put_ctrl;
  1106. }
  1107. irq_set_chained_handler_and_data(pmic_arb->irq, pmic_arb_chained_irq,
  1108. pmic_arb);
  1109. err = spmi_controller_add(ctrl);
  1110. if (err)
  1111. goto err_domain_remove;
  1112. return 0;
  1113. err_domain_remove:
  1114. irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
  1115. irq_domain_remove(pmic_arb->domain);
  1116. err_put_ctrl:
  1117. spmi_controller_put(ctrl);
  1118. return err;
  1119. }
  1120. static int spmi_pmic_arb_remove(struct platform_device *pdev)
  1121. {
  1122. struct spmi_controller *ctrl = platform_get_drvdata(pdev);
  1123. struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
  1124. spmi_controller_remove(ctrl);
  1125. irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
  1126. irq_domain_remove(pmic_arb->domain);
  1127. spmi_controller_put(ctrl);
  1128. return 0;
  1129. }
  1130. static const struct of_device_id spmi_pmic_arb_match_table[] = {
  1131. { .compatible = "qcom,spmi-pmic-arb", },
  1132. {},
  1133. };
  1134. MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table);
  1135. static struct platform_driver spmi_pmic_arb_driver = {
  1136. .probe = spmi_pmic_arb_probe,
  1137. .remove = spmi_pmic_arb_remove,
  1138. .driver = {
  1139. .name = "spmi_pmic_arb",
  1140. .of_match_table = spmi_pmic_arb_match_table,
  1141. },
  1142. };
  1143. module_platform_driver(spmi_pmic_arb_driver);
  1144. MODULE_LICENSE("GPL v2");
  1145. MODULE_ALIAS("platform:spmi_pmic_arb");