spi-zynq-qspi.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019 Xilinx, Inc.
  4. *
  5. * Author: Naga Sureshkumar Relli <nagasure@xilinx.com>
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/delay.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/io.h>
  11. #include <linux/module.h>
  12. #include <linux/of_irq.h>
  13. #include <linux/of_address.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/spi/spi.h>
  16. #include <linux/workqueue.h>
  17. #include <linux/spi/spi-mem.h>
  18. /* Register offset definitions */
  19. #define ZYNQ_QSPI_CONFIG_OFFSET 0x00 /* Configuration Register, RW */
  20. #define ZYNQ_QSPI_STATUS_OFFSET 0x04 /* Interrupt Status Register, RO */
  21. #define ZYNQ_QSPI_IEN_OFFSET 0x08 /* Interrupt Enable Register, WO */
  22. #define ZYNQ_QSPI_IDIS_OFFSET 0x0C /* Interrupt Disable Reg, WO */
  23. #define ZYNQ_QSPI_IMASK_OFFSET 0x10 /* Interrupt Enabled Mask Reg,RO */
  24. #define ZYNQ_QSPI_ENABLE_OFFSET 0x14 /* Enable/Disable Register, RW */
  25. #define ZYNQ_QSPI_DELAY_OFFSET 0x18 /* Delay Register, RW */
  26. #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */
  27. #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */
  28. #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */
  29. #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */
  30. #define ZYNQ_QSPI_RXD_OFFSET 0x20 /* Data Receive Register, RO */
  31. #define ZYNQ_QSPI_SIC_OFFSET 0x24 /* Slave Idle Count Register, RW */
  32. #define ZYNQ_QSPI_TX_THRESH_OFFSET 0x28 /* TX FIFO Watermark Reg, RW */
  33. #define ZYNQ_QSPI_RX_THRESH_OFFSET 0x2C /* RX FIFO Watermark Reg, RW */
  34. #define ZYNQ_QSPI_GPIO_OFFSET 0x30 /* GPIO Register, RW */
  35. #define ZYNQ_QSPI_LINEAR_CFG_OFFSET 0xA0 /* Linear Adapter Config Ref, RW */
  36. #define ZYNQ_QSPI_MOD_ID_OFFSET 0xFC /* Module ID Register, RO */
  37. /*
  38. * QSPI Configuration Register bit Masks
  39. *
  40. * This register contains various control bits that effect the operation
  41. * of the QSPI controller
  42. */
  43. #define ZYNQ_QSPI_CONFIG_IFMODE_MASK BIT(31) /* Flash Memory Interface */
  44. #define ZYNQ_QSPI_CONFIG_MANSRT_MASK BIT(16) /* Manual TX Start */
  45. #define ZYNQ_QSPI_CONFIG_MANSRTEN_MASK BIT(15) /* Enable Manual TX Mode */
  46. #define ZYNQ_QSPI_CONFIG_SSFORCE_MASK BIT(14) /* Manual Chip Select */
  47. #define ZYNQ_QSPI_CONFIG_BDRATE_MASK GENMASK(5, 3) /* Baud Rate Mask */
  48. #define ZYNQ_QSPI_CONFIG_CPHA_MASK BIT(2) /* Clock Phase Control */
  49. #define ZYNQ_QSPI_CONFIG_CPOL_MASK BIT(1) /* Clock Polarity Control */
  50. #define ZYNQ_QSPI_CONFIG_FWIDTH_MASK GENMASK(7, 6) /* FIFO width */
  51. #define ZYNQ_QSPI_CONFIG_MSTREN_MASK BIT(0) /* Master Mode */
  52. /*
  53. * QSPI Configuration Register - Baud rate and slave select
  54. *
  55. * These are the values used in the calculation of baud rate divisor and
  56. * setting the slave select.
  57. */
  58. #define ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX GENMASK(2, 0) /* Baud rate maximum */
  59. #define ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift */
  60. #define ZYNQ_QSPI_CONFIG_PCS BIT(10) /* Peripheral Chip Select */
  61. /*
  62. * QSPI Interrupt Registers bit Masks
  63. *
  64. * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  65. * bit definitions.
  66. */
  67. #define ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK BIT(0) /* QSPI RX FIFO Overflow */
  68. #define ZYNQ_QSPI_IXR_TXNFULL_MASK BIT(2) /* QSPI TX FIFO Overflow */
  69. #define ZYNQ_QSPI_IXR_TXFULL_MASK BIT(3) /* QSPI TX FIFO is full */
  70. #define ZYNQ_QSPI_IXR_RXNEMTY_MASK BIT(4) /* QSPI RX FIFO Not Empty */
  71. #define ZYNQ_QSPI_IXR_RXF_FULL_MASK BIT(5) /* QSPI RX FIFO is full */
  72. #define ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK BIT(6) /* QSPI TX FIFO Underflow */
  73. #define ZYNQ_QSPI_IXR_ALL_MASK (ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK | \
  74. ZYNQ_QSPI_IXR_TXNFULL_MASK | \
  75. ZYNQ_QSPI_IXR_TXFULL_MASK | \
  76. ZYNQ_QSPI_IXR_RXNEMTY_MASK | \
  77. ZYNQ_QSPI_IXR_RXF_FULL_MASK | \
  78. ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK)
  79. #define ZYNQ_QSPI_IXR_RXTX_MASK (ZYNQ_QSPI_IXR_TXNFULL_MASK | \
  80. ZYNQ_QSPI_IXR_RXNEMTY_MASK)
  81. /*
  82. * QSPI Enable Register bit Masks
  83. *
  84. * This register is used to enable or disable the QSPI controller
  85. */
  86. #define ZYNQ_QSPI_ENABLE_ENABLE_MASK BIT(0) /* QSPI Enable Bit Mask */
  87. /*
  88. * QSPI Linear Configuration Register
  89. *
  90. * It is named Linear Configuration but it controls other modes when not in
  91. * linear mode also.
  92. */
  93. #define ZYNQ_QSPI_LCFG_TWO_MEM BIT(30) /* LQSPI Two memories */
  94. #define ZYNQ_QSPI_LCFG_SEP_BUS BIT(29) /* LQSPI Separate bus */
  95. #define ZYNQ_QSPI_LCFG_U_PAGE BIT(28) /* LQSPI Upper Page */
  96. #define ZYNQ_QSPI_LCFG_DUMMY_SHIFT 8
  97. #define ZYNQ_QSPI_FAST_READ_QOUT_CODE 0x6B /* read instruction code */
  98. #define ZYNQ_QSPI_FIFO_DEPTH 63 /* FIFO depth in words */
  99. #define ZYNQ_QSPI_RX_THRESHOLD 32 /* Rx FIFO threshold level */
  100. #define ZYNQ_QSPI_TX_THRESHOLD 1 /* Tx FIFO threshold level */
  101. /*
  102. * The modebits configurable by the driver to make the SPI support different
  103. * data formats
  104. */
  105. #define ZYNQ_QSPI_MODEBITS (SPI_CPOL | SPI_CPHA)
  106. /* Maximum number of chip selects */
  107. #define ZYNQ_QSPI_MAX_NUM_CS 2
  108. /**
  109. * struct zynq_qspi - Defines qspi driver instance
  110. * @dev: Pointer to the this device's information
  111. * @regs: Virtual address of the QSPI controller registers
  112. * @refclk: Pointer to the peripheral clock
  113. * @pclk: Pointer to the APB clock
  114. * @irq: IRQ number
  115. * @txbuf: Pointer to the TX buffer
  116. * @rxbuf: Pointer to the RX buffer
  117. * @tx_bytes: Number of bytes left to transfer
  118. * @rx_bytes: Number of bytes left to receive
  119. * @data_completion: completion structure
  120. */
  121. struct zynq_qspi {
  122. struct device *dev;
  123. void __iomem *regs;
  124. struct clk *refclk;
  125. struct clk *pclk;
  126. int irq;
  127. u8 *txbuf;
  128. u8 *rxbuf;
  129. int tx_bytes;
  130. int rx_bytes;
  131. struct completion data_completion;
  132. };
  133. /*
  134. * Inline functions for the QSPI controller read/write
  135. */
  136. static inline u32 zynq_qspi_read(struct zynq_qspi *xqspi, u32 offset)
  137. {
  138. return readl_relaxed(xqspi->regs + offset);
  139. }
  140. static inline void zynq_qspi_write(struct zynq_qspi *xqspi, u32 offset,
  141. u32 val)
  142. {
  143. writel_relaxed(val, xqspi->regs + offset);
  144. }
  145. /**
  146. * zynq_qspi_init_hw - Initialize the hardware
  147. * @xqspi: Pointer to the zynq_qspi structure
  148. * @num_cs: Number of connected CS (to enable dual memories if needed)
  149. *
  150. * The default settings of the QSPI controller's configurable parameters on
  151. * reset are
  152. * - Master mode
  153. * - Baud rate divisor is set to 2
  154. * - Tx threshold set to 1l Rx threshold set to 32
  155. * - Flash memory interface mode enabled
  156. * - Size of the word to be transferred as 8 bit
  157. * This function performs the following actions
  158. * - Disable and clear all the interrupts
  159. * - Enable manual slave select
  160. * - Enable manual start
  161. * - Deselect all the chip select lines
  162. * - Set the size of the word to be transferred as 32 bit
  163. * - Set the little endian mode of TX FIFO and
  164. * - Enable the QSPI controller
  165. */
  166. static void zynq_qspi_init_hw(struct zynq_qspi *xqspi, unsigned int num_cs)
  167. {
  168. u32 config_reg;
  169. zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0);
  170. zynq_qspi_write(xqspi, ZYNQ_QSPI_IDIS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK);
  171. /* Disable linear mode as the boot loader may have used it */
  172. config_reg = 0;
  173. /* At the same time, enable dual mode if more than 1 CS is available */
  174. if (num_cs > 1)
  175. config_reg |= ZYNQ_QSPI_LCFG_TWO_MEM;
  176. zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, config_reg);
  177. /* Clear the RX FIFO */
  178. while (zynq_qspi_read(xqspi, ZYNQ_QSPI_STATUS_OFFSET) &
  179. ZYNQ_QSPI_IXR_RXNEMTY_MASK)
  180. zynq_qspi_read(xqspi, ZYNQ_QSPI_RXD_OFFSET);
  181. zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK);
  182. config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);
  183. config_reg &= ~(ZYNQ_QSPI_CONFIG_MSTREN_MASK |
  184. ZYNQ_QSPI_CONFIG_CPOL_MASK |
  185. ZYNQ_QSPI_CONFIG_CPHA_MASK |
  186. ZYNQ_QSPI_CONFIG_BDRATE_MASK |
  187. ZYNQ_QSPI_CONFIG_SSFORCE_MASK |
  188. ZYNQ_QSPI_CONFIG_MANSRTEN_MASK |
  189. ZYNQ_QSPI_CONFIG_MANSRT_MASK);
  190. config_reg |= (ZYNQ_QSPI_CONFIG_MSTREN_MASK |
  191. ZYNQ_QSPI_CONFIG_SSFORCE_MASK |
  192. ZYNQ_QSPI_CONFIG_FWIDTH_MASK |
  193. ZYNQ_QSPI_CONFIG_IFMODE_MASK);
  194. zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
  195. zynq_qspi_write(xqspi, ZYNQ_QSPI_RX_THRESH_OFFSET,
  196. ZYNQ_QSPI_RX_THRESHOLD);
  197. zynq_qspi_write(xqspi, ZYNQ_QSPI_TX_THRESH_OFFSET,
  198. ZYNQ_QSPI_TX_THRESHOLD);
  199. zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET,
  200. ZYNQ_QSPI_ENABLE_ENABLE_MASK);
  201. }
  202. static bool zynq_qspi_supports_op(struct spi_mem *mem,
  203. const struct spi_mem_op *op)
  204. {
  205. if (!spi_mem_default_supports_op(mem, op))
  206. return false;
  207. /*
  208. * The number of address bytes should be equal to or less than 3 bytes.
  209. */
  210. if (op->addr.nbytes > 3)
  211. return false;
  212. return true;
  213. }
  214. /**
  215. * zynq_qspi_rxfifo_op - Read 1..4 bytes from RxFIFO to RX buffer
  216. * @xqspi: Pointer to the zynq_qspi structure
  217. * @size: Number of bytes to be read (1..4)
  218. */
  219. static void zynq_qspi_rxfifo_op(struct zynq_qspi *xqspi, unsigned int size)
  220. {
  221. u32 data;
  222. data = zynq_qspi_read(xqspi, ZYNQ_QSPI_RXD_OFFSET);
  223. if (xqspi->rxbuf) {
  224. memcpy(xqspi->rxbuf, ((u8 *)&data) + 4 - size, size);
  225. xqspi->rxbuf += size;
  226. }
  227. xqspi->rx_bytes -= size;
  228. if (xqspi->rx_bytes < 0)
  229. xqspi->rx_bytes = 0;
  230. }
  231. /**
  232. * zynq_qspi_txfifo_op - Write 1..4 bytes from TX buffer to TxFIFO
  233. * @xqspi: Pointer to the zynq_qspi structure
  234. * @size: Number of bytes to be written (1..4)
  235. */
  236. static void zynq_qspi_txfifo_op(struct zynq_qspi *xqspi, unsigned int size)
  237. {
  238. static const unsigned int offset[4] = {
  239. ZYNQ_QSPI_TXD_00_01_OFFSET, ZYNQ_QSPI_TXD_00_10_OFFSET,
  240. ZYNQ_QSPI_TXD_00_11_OFFSET, ZYNQ_QSPI_TXD_00_00_OFFSET };
  241. u32 data;
  242. if (xqspi->txbuf) {
  243. data = 0xffffffff;
  244. memcpy(&data, xqspi->txbuf, size);
  245. xqspi->txbuf += size;
  246. } else {
  247. data = 0;
  248. }
  249. xqspi->tx_bytes -= size;
  250. zynq_qspi_write(xqspi, offset[size - 1], data);
  251. }
  252. /**
  253. * zynq_qspi_chipselect - Select or deselect the chip select line
  254. * @spi: Pointer to the spi_device structure
  255. * @assert: 1 for select or 0 for deselect the chip select line
  256. */
  257. static void zynq_qspi_chipselect(struct spi_device *spi, bool assert)
  258. {
  259. struct spi_controller *ctlr = spi->master;
  260. struct zynq_qspi *xqspi = spi_controller_get_devdata(ctlr);
  261. u32 config_reg;
  262. /* Select the lower (CS0) or upper (CS1) memory */
  263. if (ctlr->num_chipselect > 1) {
  264. config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET);
  265. if (!spi->chip_select)
  266. config_reg &= ~ZYNQ_QSPI_LCFG_U_PAGE;
  267. else
  268. config_reg |= ZYNQ_QSPI_LCFG_U_PAGE;
  269. zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, config_reg);
  270. }
  271. /* Ground the line to assert the CS */
  272. config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);
  273. if (assert)
  274. config_reg &= ~ZYNQ_QSPI_CONFIG_PCS;
  275. else
  276. config_reg |= ZYNQ_QSPI_CONFIG_PCS;
  277. zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
  278. }
  279. /**
  280. * zynq_qspi_config_op - Configure QSPI controller for specified transfer
  281. * @xqspi: Pointer to the zynq_qspi structure
  282. * @spi: Pointer to the spi_device structure
  283. *
  284. * Sets the operational mode of QSPI controller for the next QSPI transfer and
  285. * sets the requested clock frequency.
  286. *
  287. * Return: 0 on success and -EINVAL on invalid input parameter
  288. *
  289. * Note: If the requested frequency is not an exact match with what can be
  290. * obtained using the prescalar value, the driver sets the clock frequency which
  291. * is lower than the requested frequency (maximum lower) for the transfer. If
  292. * the requested frequency is higher or lower than that is supported by the QSPI
  293. * controller the driver will set the highest or lowest frequency supported by
  294. * controller.
  295. */
  296. static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi)
  297. {
  298. u32 config_reg, baud_rate_val = 0;
  299. /*
  300. * Set the clock frequency
  301. * The baud rate divisor is not a direct mapping to the value written
  302. * into the configuration register (config_reg[5:3])
  303. * i.e. 000 - divide by 2
  304. * 001 - divide by 4
  305. * ----------------
  306. * 111 - divide by 256
  307. */
  308. while ((baud_rate_val < ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX) &&
  309. (clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) >
  310. spi->max_speed_hz)
  311. baud_rate_val++;
  312. config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);
  313. /* Set the QSPI clock phase and clock polarity */
  314. config_reg &= (~ZYNQ_QSPI_CONFIG_CPHA_MASK) &
  315. (~ZYNQ_QSPI_CONFIG_CPOL_MASK);
  316. if (spi->mode & SPI_CPHA)
  317. config_reg |= ZYNQ_QSPI_CONFIG_CPHA_MASK;
  318. if (spi->mode & SPI_CPOL)
  319. config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK;
  320. config_reg &= ~ZYNQ_QSPI_CONFIG_BDRATE_MASK;
  321. config_reg |= (baud_rate_val << ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT);
  322. zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
  323. return 0;
  324. }
  325. /**
  326. * zynq_qspi_setup - Configure the QSPI controller
  327. * @spi: Pointer to the spi_device structure
  328. *
  329. * Sets the operational mode of QSPI controller for the next QSPI transfer, baud
  330. * rate and divisor value to setup the requested qspi clock.
  331. *
  332. * Return: 0 on success and error value on failure
  333. */
  334. static int zynq_qspi_setup_op(struct spi_device *spi)
  335. {
  336. struct spi_controller *ctlr = spi->master;
  337. struct zynq_qspi *qspi = spi_controller_get_devdata(ctlr);
  338. if (ctlr->busy)
  339. return -EBUSY;
  340. clk_enable(qspi->refclk);
  341. clk_enable(qspi->pclk);
  342. zynq_qspi_write(qspi, ZYNQ_QSPI_ENABLE_OFFSET,
  343. ZYNQ_QSPI_ENABLE_ENABLE_MASK);
  344. return 0;
  345. }
  346. /**
  347. * zynq_qspi_write_op - Fills the TX FIFO with as many bytes as possible
  348. * @xqspi: Pointer to the zynq_qspi structure
  349. * @txcount: Maximum number of words to write
  350. * @txempty: Indicates that TxFIFO is empty
  351. */
  352. static void zynq_qspi_write_op(struct zynq_qspi *xqspi, int txcount,
  353. bool txempty)
  354. {
  355. int count, len, k;
  356. len = xqspi->tx_bytes;
  357. if (len && len < 4) {
  358. /*
  359. * We must empty the TxFIFO between accesses to TXD0,
  360. * TXD1, TXD2, TXD3.
  361. */
  362. if (txempty)
  363. zynq_qspi_txfifo_op(xqspi, len);
  364. return;
  365. }
  366. count = len / 4;
  367. if (count > txcount)
  368. count = txcount;
  369. if (xqspi->txbuf) {
  370. iowrite32_rep(xqspi->regs + ZYNQ_QSPI_TXD_00_00_OFFSET,
  371. xqspi->txbuf, count);
  372. xqspi->txbuf += count * 4;
  373. } else {
  374. for (k = 0; k < count; k++)
  375. writel_relaxed(0, xqspi->regs +
  376. ZYNQ_QSPI_TXD_00_00_OFFSET);
  377. }
  378. xqspi->tx_bytes -= count * 4;
  379. }
  380. /**
  381. * zynq_qspi_read_op - Drains the RX FIFO by as many bytes as possible
  382. * @xqspi: Pointer to the zynq_qspi structure
  383. * @rxcount: Maximum number of words to read
  384. */
  385. static void zynq_qspi_read_op(struct zynq_qspi *xqspi, int rxcount)
  386. {
  387. int count, len, k;
  388. len = xqspi->rx_bytes - xqspi->tx_bytes;
  389. count = len / 4;
  390. if (count > rxcount)
  391. count = rxcount;
  392. if (xqspi->rxbuf) {
  393. ioread32_rep(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET,
  394. xqspi->rxbuf, count);
  395. xqspi->rxbuf += count * 4;
  396. } else {
  397. for (k = 0; k < count; k++)
  398. readl_relaxed(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET);
  399. }
  400. xqspi->rx_bytes -= count * 4;
  401. len -= count * 4;
  402. if (len && len < 4 && count < rxcount)
  403. zynq_qspi_rxfifo_op(xqspi, len);
  404. }
  405. /**
  406. * zynq_qspi_irq - Interrupt service routine of the QSPI controller
  407. * @irq: IRQ number
  408. * @dev_id: Pointer to the xqspi structure
  409. *
  410. * This function handles TX empty only.
  411. * On TX empty interrupt this function reads the received data from RX FIFO and
  412. * fills the TX FIFO if there is any data remaining to be transferred.
  413. *
  414. * Return: IRQ_HANDLED when interrupt is handled; IRQ_NONE otherwise.
  415. */
  416. static irqreturn_t zynq_qspi_irq(int irq, void *dev_id)
  417. {
  418. u32 intr_status;
  419. bool txempty;
  420. struct zynq_qspi *xqspi = (struct zynq_qspi *)dev_id;
  421. intr_status = zynq_qspi_read(xqspi, ZYNQ_QSPI_STATUS_OFFSET);
  422. zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, intr_status);
  423. if ((intr_status & ZYNQ_QSPI_IXR_TXNFULL_MASK) ||
  424. (intr_status & ZYNQ_QSPI_IXR_RXNEMTY_MASK)) {
  425. /*
  426. * This bit is set when Tx FIFO has < THRESHOLD entries.
  427. * We have the THRESHOLD value set to 1,
  428. * so this bit indicates Tx FIFO is empty.
  429. */
  430. txempty = !!(intr_status & ZYNQ_QSPI_IXR_TXNFULL_MASK);
  431. /* Read out the data from the RX FIFO */
  432. zynq_qspi_read_op(xqspi, ZYNQ_QSPI_RX_THRESHOLD);
  433. if (xqspi->tx_bytes) {
  434. /* There is more data to send */
  435. zynq_qspi_write_op(xqspi, ZYNQ_QSPI_RX_THRESHOLD,
  436. txempty);
  437. } else {
  438. /*
  439. * If transfer and receive is completed then only send
  440. * complete signal.
  441. */
  442. if (!xqspi->rx_bytes) {
  443. zynq_qspi_write(xqspi,
  444. ZYNQ_QSPI_IDIS_OFFSET,
  445. ZYNQ_QSPI_IXR_RXTX_MASK);
  446. complete(&xqspi->data_completion);
  447. }
  448. }
  449. return IRQ_HANDLED;
  450. }
  451. return IRQ_NONE;
  452. }
  453. /**
  454. * zynq_qspi_exec_mem_op() - Initiates the QSPI transfer
  455. * @mem: the SPI memory
  456. * @op: the memory operation to execute
  457. *
  458. * Executes a memory operation.
  459. *
  460. * This function first selects the chip and starts the memory operation.
  461. *
  462. * Return: 0 in case of success, a negative error code otherwise.
  463. */
  464. static int zynq_qspi_exec_mem_op(struct spi_mem *mem,
  465. const struct spi_mem_op *op)
  466. {
  467. struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->master);
  468. int err = 0, i;
  469. u8 *tmpbuf;
  470. dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
  471. op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
  472. op->dummy.buswidth, op->data.buswidth);
  473. zynq_qspi_chipselect(mem->spi, true);
  474. zynq_qspi_config_op(xqspi, mem->spi);
  475. if (op->cmd.opcode) {
  476. reinit_completion(&xqspi->data_completion);
  477. xqspi->txbuf = (u8 *)&op->cmd.opcode;
  478. xqspi->rxbuf = NULL;
  479. xqspi->tx_bytes = op->cmd.nbytes;
  480. xqspi->rx_bytes = op->cmd.nbytes;
  481. zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
  482. zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
  483. ZYNQ_QSPI_IXR_RXTX_MASK);
  484. if (!wait_for_completion_timeout(&xqspi->data_completion,
  485. msecs_to_jiffies(1000)))
  486. err = -ETIMEDOUT;
  487. }
  488. if (op->addr.nbytes) {
  489. for (i = 0; i < op->addr.nbytes; i++) {
  490. xqspi->txbuf[i] = op->addr.val >>
  491. (8 * (op->addr.nbytes - i - 1));
  492. }
  493. reinit_completion(&xqspi->data_completion);
  494. xqspi->rxbuf = NULL;
  495. xqspi->tx_bytes = op->addr.nbytes;
  496. xqspi->rx_bytes = op->addr.nbytes;
  497. zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
  498. zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
  499. ZYNQ_QSPI_IXR_RXTX_MASK);
  500. if (!wait_for_completion_timeout(&xqspi->data_completion,
  501. msecs_to_jiffies(1000)))
  502. err = -ETIMEDOUT;
  503. }
  504. if (op->dummy.nbytes) {
  505. tmpbuf = kzalloc(op->dummy.nbytes, GFP_KERNEL);
  506. if (!tmpbuf)
  507. return -ENOMEM;
  508. memset(tmpbuf, 0xff, op->dummy.nbytes);
  509. reinit_completion(&xqspi->data_completion);
  510. xqspi->txbuf = tmpbuf;
  511. xqspi->rxbuf = NULL;
  512. xqspi->tx_bytes = op->dummy.nbytes;
  513. xqspi->rx_bytes = op->dummy.nbytes;
  514. zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
  515. zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
  516. ZYNQ_QSPI_IXR_RXTX_MASK);
  517. if (!wait_for_completion_timeout(&xqspi->data_completion,
  518. msecs_to_jiffies(1000)))
  519. err = -ETIMEDOUT;
  520. kfree(tmpbuf);
  521. }
  522. if (op->data.nbytes) {
  523. reinit_completion(&xqspi->data_completion);
  524. if (op->data.dir == SPI_MEM_DATA_OUT) {
  525. xqspi->txbuf = (u8 *)op->data.buf.out;
  526. xqspi->tx_bytes = op->data.nbytes;
  527. xqspi->rxbuf = NULL;
  528. xqspi->rx_bytes = op->data.nbytes;
  529. } else {
  530. xqspi->txbuf = NULL;
  531. xqspi->rxbuf = (u8 *)op->data.buf.in;
  532. xqspi->rx_bytes = op->data.nbytes;
  533. xqspi->tx_bytes = op->data.nbytes;
  534. }
  535. zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
  536. zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
  537. ZYNQ_QSPI_IXR_RXTX_MASK);
  538. if (!wait_for_completion_timeout(&xqspi->data_completion,
  539. msecs_to_jiffies(1000)))
  540. err = -ETIMEDOUT;
  541. }
  542. zynq_qspi_chipselect(mem->spi, false);
  543. return err;
  544. }
  545. static const struct spi_controller_mem_ops zynq_qspi_mem_ops = {
  546. .supports_op = zynq_qspi_supports_op,
  547. .exec_op = zynq_qspi_exec_mem_op,
  548. };
  549. /**
  550. * zynq_qspi_probe - Probe method for the QSPI driver
  551. * @pdev: Pointer to the platform_device structure
  552. *
  553. * This function initializes the driver data structures and the hardware.
  554. *
  555. * Return: 0 on success and error value on failure
  556. */
  557. static int zynq_qspi_probe(struct platform_device *pdev)
  558. {
  559. int ret = 0;
  560. struct spi_controller *ctlr;
  561. struct device *dev = &pdev->dev;
  562. struct device_node *np = dev->of_node;
  563. struct zynq_qspi *xqspi;
  564. u32 num_cs;
  565. ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
  566. if (!ctlr)
  567. return -ENOMEM;
  568. xqspi = spi_controller_get_devdata(ctlr);
  569. xqspi->dev = dev;
  570. platform_set_drvdata(pdev, xqspi);
  571. xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
  572. if (IS_ERR(xqspi->regs)) {
  573. ret = PTR_ERR(xqspi->regs);
  574. goto remove_master;
  575. }
  576. xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
  577. if (IS_ERR(xqspi->pclk)) {
  578. dev_err(&pdev->dev, "pclk clock not found.\n");
  579. ret = PTR_ERR(xqspi->pclk);
  580. goto remove_master;
  581. }
  582. init_completion(&xqspi->data_completion);
  583. xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
  584. if (IS_ERR(xqspi->refclk)) {
  585. dev_err(&pdev->dev, "ref_clk clock not found.\n");
  586. ret = PTR_ERR(xqspi->refclk);
  587. goto remove_master;
  588. }
  589. ret = clk_prepare_enable(xqspi->pclk);
  590. if (ret) {
  591. dev_err(&pdev->dev, "Unable to enable APB clock.\n");
  592. goto remove_master;
  593. }
  594. ret = clk_prepare_enable(xqspi->refclk);
  595. if (ret) {
  596. dev_err(&pdev->dev, "Unable to enable device clock.\n");
  597. goto clk_dis_pclk;
  598. }
  599. xqspi->irq = platform_get_irq(pdev, 0);
  600. if (xqspi->irq <= 0) {
  601. ret = -ENXIO;
  602. goto clk_dis_all;
  603. }
  604. ret = devm_request_irq(&pdev->dev, xqspi->irq, zynq_qspi_irq,
  605. 0, pdev->name, xqspi);
  606. if (ret != 0) {
  607. ret = -ENXIO;
  608. dev_err(&pdev->dev, "request_irq failed\n");
  609. goto clk_dis_all;
  610. }
  611. ret = of_property_read_u32(np, "num-cs",
  612. &num_cs);
  613. if (ret < 0) {
  614. ctlr->num_chipselect = 1;
  615. } else if (num_cs > ZYNQ_QSPI_MAX_NUM_CS) {
  616. ret = -EINVAL;
  617. dev_err(&pdev->dev, "only 2 chip selects are available\n");
  618. goto clk_dis_all;
  619. } else {
  620. ctlr->num_chipselect = num_cs;
  621. }
  622. ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
  623. SPI_TX_DUAL | SPI_TX_QUAD;
  624. ctlr->mem_ops = &zynq_qspi_mem_ops;
  625. ctlr->setup = zynq_qspi_setup_op;
  626. ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
  627. ctlr->dev.of_node = np;
  628. /* QSPI controller initializations */
  629. zynq_qspi_init_hw(xqspi, ctlr->num_chipselect);
  630. ret = devm_spi_register_controller(&pdev->dev, ctlr);
  631. if (ret) {
  632. dev_err(&pdev->dev, "spi_register_master failed\n");
  633. goto clk_dis_all;
  634. }
  635. return ret;
  636. clk_dis_all:
  637. clk_disable_unprepare(xqspi->refclk);
  638. clk_dis_pclk:
  639. clk_disable_unprepare(xqspi->pclk);
  640. remove_master:
  641. spi_controller_put(ctlr);
  642. return ret;
  643. }
  644. /**
  645. * zynq_qspi_remove - Remove method for the QSPI driver
  646. * @pdev: Pointer to the platform_device structure
  647. *
  648. * This function is called if a device is physically removed from the system or
  649. * if the driver module is being unloaded. It frees all resources allocated to
  650. * the device.
  651. *
  652. * Return: 0 on success and error value on failure
  653. */
  654. static int zynq_qspi_remove(struct platform_device *pdev)
  655. {
  656. struct zynq_qspi *xqspi = platform_get_drvdata(pdev);
  657. zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0);
  658. clk_disable_unprepare(xqspi->refclk);
  659. clk_disable_unprepare(xqspi->pclk);
  660. return 0;
  661. }
  662. static const struct of_device_id zynq_qspi_of_match[] = {
  663. { .compatible = "xlnx,zynq-qspi-1.0", },
  664. { /* end of table */ }
  665. };
  666. MODULE_DEVICE_TABLE(of, zynq_qspi_of_match);
  667. /*
  668. * zynq_qspi_driver - This structure defines the QSPI platform driver
  669. */
  670. static struct platform_driver zynq_qspi_driver = {
  671. .probe = zynq_qspi_probe,
  672. .remove = zynq_qspi_remove,
  673. .driver = {
  674. .name = "zynq-qspi",
  675. .of_match_table = zynq_qspi_of_match,
  676. },
  677. };
  678. module_platform_driver(zynq_qspi_driver);
  679. MODULE_AUTHOR("Xilinx, Inc.");
  680. MODULE_DESCRIPTION("Xilinx Zynq QSPI driver");
  681. MODULE_LICENSE("GPL");