spi-xtensa-xtfpga.c 3.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Xtensa xtfpga SPI controller driver
  4. *
  5. * Copyright (c) 2014 Cadence Design Systems Inc.
  6. */
  7. #include <linux/delay.h>
  8. #include <linux/io.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/spi/spi.h>
  13. #include <linux/spi/spi_bitbang.h>
  14. #define XTFPGA_SPI_NAME "xtfpga_spi"
  15. #define XTFPGA_SPI_START 0x0
  16. #define XTFPGA_SPI_BUSY 0x4
  17. #define XTFPGA_SPI_DATA 0x8
  18. #define BUSY_WAIT_US 100
  19. struct xtfpga_spi {
  20. struct spi_bitbang bitbang;
  21. void __iomem *regs;
  22. u32 data;
  23. unsigned data_sz;
  24. };
  25. static inline void xtfpga_spi_write32(const struct xtfpga_spi *spi,
  26. unsigned addr, u32 val)
  27. {
  28. __raw_writel(val, spi->regs + addr);
  29. }
  30. static inline unsigned int xtfpga_spi_read32(const struct xtfpga_spi *spi,
  31. unsigned addr)
  32. {
  33. return __raw_readl(spi->regs + addr);
  34. }
  35. static inline void xtfpga_spi_wait_busy(struct xtfpga_spi *xspi)
  36. {
  37. unsigned i;
  38. for (i = 0; xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY) &&
  39. i < BUSY_WAIT_US; ++i)
  40. udelay(1);
  41. WARN_ON_ONCE(i == BUSY_WAIT_US);
  42. }
  43. static u32 xtfpga_spi_txrx_word(struct spi_device *spi, unsigned nsecs,
  44. u32 v, u8 bits, unsigned flags)
  45. {
  46. struct xtfpga_spi *xspi = spi_master_get_devdata(spi->master);
  47. xspi->data = (xspi->data << bits) | (v & GENMASK(bits - 1, 0));
  48. xspi->data_sz += bits;
  49. if (xspi->data_sz >= 16) {
  50. xtfpga_spi_write32(xspi, XTFPGA_SPI_DATA,
  51. xspi->data >> (xspi->data_sz - 16));
  52. xspi->data_sz -= 16;
  53. xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 1);
  54. xtfpga_spi_wait_busy(xspi);
  55. xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 0);
  56. }
  57. return 0;
  58. }
  59. static void xtfpga_spi_chipselect(struct spi_device *spi, int is_on)
  60. {
  61. struct xtfpga_spi *xspi = spi_master_get_devdata(spi->master);
  62. WARN_ON(xspi->data_sz != 0);
  63. xspi->data_sz = 0;
  64. }
  65. static int xtfpga_spi_probe(struct platform_device *pdev)
  66. {
  67. struct xtfpga_spi *xspi;
  68. int ret;
  69. struct spi_master *master;
  70. master = spi_alloc_master(&pdev->dev, sizeof(struct xtfpga_spi));
  71. if (!master)
  72. return -ENOMEM;
  73. master->flags = SPI_MASTER_NO_RX;
  74. master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
  75. master->bus_num = pdev->dev.id;
  76. master->dev.of_node = pdev->dev.of_node;
  77. xspi = spi_master_get_devdata(master);
  78. xspi->bitbang.master = master;
  79. xspi->bitbang.chipselect = xtfpga_spi_chipselect;
  80. xspi->bitbang.txrx_word[SPI_MODE_0] = xtfpga_spi_txrx_word;
  81. xspi->regs = devm_platform_ioremap_resource(pdev, 0);
  82. if (IS_ERR(xspi->regs)) {
  83. ret = PTR_ERR(xspi->regs);
  84. goto err;
  85. }
  86. xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 0);
  87. usleep_range(1000, 2000);
  88. if (xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY)) {
  89. dev_err(&pdev->dev, "Device stuck in busy state\n");
  90. ret = -EBUSY;
  91. goto err;
  92. }
  93. ret = spi_bitbang_start(&xspi->bitbang);
  94. if (ret < 0) {
  95. dev_err(&pdev->dev, "spi_bitbang_start failed\n");
  96. goto err;
  97. }
  98. platform_set_drvdata(pdev, master);
  99. return 0;
  100. err:
  101. spi_master_put(master);
  102. return ret;
  103. }
  104. static int xtfpga_spi_remove(struct platform_device *pdev)
  105. {
  106. struct spi_master *master = platform_get_drvdata(pdev);
  107. struct xtfpga_spi *xspi = spi_master_get_devdata(master);
  108. spi_bitbang_stop(&xspi->bitbang);
  109. spi_master_put(master);
  110. return 0;
  111. }
  112. MODULE_ALIAS("platform:" XTFPGA_SPI_NAME);
  113. #ifdef CONFIG_OF
  114. static const struct of_device_id xtfpga_spi_of_match[] = {
  115. { .compatible = "cdns,xtfpga-spi", },
  116. {}
  117. };
  118. MODULE_DEVICE_TABLE(of, xtfpga_spi_of_match);
  119. #endif
  120. static struct platform_driver xtfpga_spi_driver = {
  121. .probe = xtfpga_spi_probe,
  122. .remove = xtfpga_spi_remove,
  123. .driver = {
  124. .name = XTFPGA_SPI_NAME,
  125. .of_match_table = of_match_ptr(xtfpga_spi_of_match),
  126. },
  127. };
  128. module_platform_driver(xtfpga_spi_driver);
  129. MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>");
  130. MODULE_DESCRIPTION("xtensa xtfpga SPI driver");
  131. MODULE_LICENSE("GPL");