spi-uniphier.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // spi-uniphier.c - Socionext UniPhier SPI controller driver
  3. // Copyright 2012 Panasonic Corporation
  4. // Copyright 2016-2018 Socionext Inc.
  5. #include <linux/kernel.h>
  6. #include <linux/bitfield.h>
  7. #include <linux/bitops.h>
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/dmaengine.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/io.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/spi/spi.h>
  16. #include <asm/unaligned.h>
  17. #define SSI_TIMEOUT_MS 2000
  18. #define SSI_POLL_TIMEOUT_US 200
  19. #define SSI_MAX_CLK_DIVIDER 254
  20. #define SSI_MIN_CLK_DIVIDER 4
  21. struct uniphier_spi_priv {
  22. void __iomem *base;
  23. dma_addr_t base_dma_addr;
  24. struct clk *clk;
  25. struct spi_master *master;
  26. struct completion xfer_done;
  27. int error;
  28. unsigned int tx_bytes;
  29. unsigned int rx_bytes;
  30. const u8 *tx_buf;
  31. u8 *rx_buf;
  32. atomic_t dma_busy;
  33. bool is_save_param;
  34. u8 bits_per_word;
  35. u16 mode;
  36. u32 speed_hz;
  37. };
  38. #define SSI_CTL 0x00
  39. #define SSI_CTL_EN BIT(0)
  40. #define SSI_CKS 0x04
  41. #define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
  42. #define SSI_CKS_CKPHS BIT(14)
  43. #define SSI_CKS_CKINIT BIT(13)
  44. #define SSI_CKS_CKDLY BIT(12)
  45. #define SSI_TXWDS 0x08
  46. #define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
  47. #define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
  48. #define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
  49. #define SSI_RXWDS 0x0c
  50. #define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
  51. #define SSI_FPS 0x10
  52. #define SSI_FPS_FSPOL BIT(15)
  53. #define SSI_FPS_FSTRT BIT(14)
  54. #define SSI_SR 0x14
  55. #define SSI_SR_BUSY BIT(7)
  56. #define SSI_SR_RNE BIT(0)
  57. #define SSI_IE 0x18
  58. #define SSI_IE_TCIE BIT(4)
  59. #define SSI_IE_RCIE BIT(3)
  60. #define SSI_IE_TXRE BIT(2)
  61. #define SSI_IE_RXRE BIT(1)
  62. #define SSI_IE_RORIE BIT(0)
  63. #define SSI_IE_ALL_MASK GENMASK(4, 0)
  64. #define SSI_IS 0x1c
  65. #define SSI_IS_RXRS BIT(9)
  66. #define SSI_IS_RCID BIT(3)
  67. #define SSI_IS_RORID BIT(0)
  68. #define SSI_IC 0x1c
  69. #define SSI_IC_TCIC BIT(4)
  70. #define SSI_IC_RCIC BIT(3)
  71. #define SSI_IC_RORIC BIT(0)
  72. #define SSI_FC 0x20
  73. #define SSI_FC_TXFFL BIT(12)
  74. #define SSI_FC_TXFTH_MASK GENMASK(11, 8)
  75. #define SSI_FC_RXFFL BIT(4)
  76. #define SSI_FC_RXFTH_MASK GENMASK(3, 0)
  77. #define SSI_TXDR 0x24
  78. #define SSI_RXDR 0x24
  79. #define SSI_FIFO_DEPTH 8U
  80. #define SSI_FIFO_BURST_NUM 1
  81. #define SSI_DMA_RX_BUSY BIT(1)
  82. #define SSI_DMA_TX_BUSY BIT(0)
  83. static inline unsigned int bytes_per_word(unsigned int bits)
  84. {
  85. return bits <= 8 ? 1 : (bits <= 16 ? 2 : 4);
  86. }
  87. static inline void uniphier_spi_irq_enable(struct uniphier_spi_priv *priv,
  88. u32 mask)
  89. {
  90. u32 val;
  91. val = readl(priv->base + SSI_IE);
  92. val |= mask;
  93. writel(val, priv->base + SSI_IE);
  94. }
  95. static inline void uniphier_spi_irq_disable(struct uniphier_spi_priv *priv,
  96. u32 mask)
  97. {
  98. u32 val;
  99. val = readl(priv->base + SSI_IE);
  100. val &= ~mask;
  101. writel(val, priv->base + SSI_IE);
  102. }
  103. static void uniphier_spi_set_mode(struct spi_device *spi)
  104. {
  105. struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
  106. u32 val1, val2;
  107. /*
  108. * clock setting
  109. * CKPHS capture timing. 0:rising edge, 1:falling edge
  110. * CKINIT clock initial level. 0:low, 1:high
  111. * CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT
  112. * (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock)
  113. *
  114. * frame setting
  115. * FSPOL frame signal porarity. 0: low, 1: high
  116. * FSTRT start frame timing
  117. * 0: rising edge of clock, 1: falling edge of clock
  118. */
  119. switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
  120. case SPI_MODE_0:
  121. /* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */
  122. val1 = SSI_CKS_CKPHS | SSI_CKS_CKDLY;
  123. val2 = 0;
  124. break;
  125. case SPI_MODE_1:
  126. /* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */
  127. val1 = 0;
  128. val2 = SSI_FPS_FSTRT;
  129. break;
  130. case SPI_MODE_2:
  131. /* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */
  132. val1 = SSI_CKS_CKINIT | SSI_CKS_CKDLY;
  133. val2 = SSI_FPS_FSTRT;
  134. break;
  135. case SPI_MODE_3:
  136. /* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */
  137. val1 = SSI_CKS_CKPHS | SSI_CKS_CKINIT;
  138. val2 = 0;
  139. break;
  140. }
  141. if (!(spi->mode & SPI_CS_HIGH))
  142. val2 |= SSI_FPS_FSPOL;
  143. writel(val1, priv->base + SSI_CKS);
  144. writel(val2, priv->base + SSI_FPS);
  145. val1 = 0;
  146. if (spi->mode & SPI_LSB_FIRST)
  147. val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1);
  148. writel(val1, priv->base + SSI_TXWDS);
  149. writel(val1, priv->base + SSI_RXWDS);
  150. }
  151. static void uniphier_spi_set_transfer_size(struct spi_device *spi, int size)
  152. {
  153. struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
  154. u32 val;
  155. val = readl(priv->base + SSI_TXWDS);
  156. val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK);
  157. val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size);
  158. val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size);
  159. writel(val, priv->base + SSI_TXWDS);
  160. val = readl(priv->base + SSI_RXWDS);
  161. val &= ~SSI_RXWDS_DTLEN_MASK;
  162. val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size);
  163. writel(val, priv->base + SSI_RXWDS);
  164. }
  165. static void uniphier_spi_set_baudrate(struct spi_device *spi,
  166. unsigned int speed)
  167. {
  168. struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
  169. u32 val, ckdiv;
  170. /*
  171. * the supported rates are even numbers from 4 to 254. (4,6,8...254)
  172. * round up as we look for equal or less speed
  173. */
  174. ckdiv = DIV_ROUND_UP(clk_get_rate(priv->clk), speed);
  175. ckdiv = round_up(ckdiv, 2);
  176. val = readl(priv->base + SSI_CKS);
  177. val &= ~SSI_CKS_CKRAT_MASK;
  178. val |= ckdiv & SSI_CKS_CKRAT_MASK;
  179. writel(val, priv->base + SSI_CKS);
  180. }
  181. static void uniphier_spi_setup_transfer(struct spi_device *spi,
  182. struct spi_transfer *t)
  183. {
  184. struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
  185. u32 val;
  186. priv->error = 0;
  187. priv->tx_buf = t->tx_buf;
  188. priv->rx_buf = t->rx_buf;
  189. priv->tx_bytes = priv->rx_bytes = t->len;
  190. if (!priv->is_save_param || priv->mode != spi->mode) {
  191. uniphier_spi_set_mode(spi);
  192. priv->mode = spi->mode;
  193. priv->is_save_param = false;
  194. }
  195. if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) {
  196. uniphier_spi_set_transfer_size(spi, t->bits_per_word);
  197. priv->bits_per_word = t->bits_per_word;
  198. }
  199. if (!priv->is_save_param || priv->speed_hz != t->speed_hz) {
  200. uniphier_spi_set_baudrate(spi, t->speed_hz);
  201. priv->speed_hz = t->speed_hz;
  202. }
  203. priv->is_save_param = true;
  204. /* reset FIFOs */
  205. val = SSI_FC_TXFFL | SSI_FC_RXFFL;
  206. writel(val, priv->base + SSI_FC);
  207. }
  208. static void uniphier_spi_send(struct uniphier_spi_priv *priv)
  209. {
  210. int wsize;
  211. u32 val = 0;
  212. wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
  213. priv->tx_bytes -= wsize;
  214. if (priv->tx_buf) {
  215. switch (wsize) {
  216. case 1:
  217. val = *priv->tx_buf;
  218. break;
  219. case 2:
  220. val = get_unaligned_le16(priv->tx_buf);
  221. break;
  222. case 4:
  223. val = get_unaligned_le32(priv->tx_buf);
  224. break;
  225. }
  226. priv->tx_buf += wsize;
  227. }
  228. writel(val, priv->base + SSI_TXDR);
  229. }
  230. static void uniphier_spi_recv(struct uniphier_spi_priv *priv)
  231. {
  232. int rsize;
  233. u32 val;
  234. rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes);
  235. priv->rx_bytes -= rsize;
  236. val = readl(priv->base + SSI_RXDR);
  237. if (priv->rx_buf) {
  238. switch (rsize) {
  239. case 1:
  240. *priv->rx_buf = val;
  241. break;
  242. case 2:
  243. put_unaligned_le16(val, priv->rx_buf);
  244. break;
  245. case 4:
  246. put_unaligned_le32(val, priv->rx_buf);
  247. break;
  248. }
  249. priv->rx_buf += rsize;
  250. }
  251. }
  252. static void uniphier_spi_set_fifo_threshold(struct uniphier_spi_priv *priv,
  253. unsigned int threshold)
  254. {
  255. u32 val;
  256. val = readl(priv->base + SSI_FC);
  257. val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);
  258. val |= FIELD_PREP(SSI_FC_TXFTH_MASK, SSI_FIFO_DEPTH - threshold);
  259. val |= FIELD_PREP(SSI_FC_RXFTH_MASK, threshold);
  260. writel(val, priv->base + SSI_FC);
  261. }
  262. static void uniphier_spi_fill_tx_fifo(struct uniphier_spi_priv *priv)
  263. {
  264. unsigned int fifo_threshold, fill_words;
  265. unsigned int bpw = bytes_per_word(priv->bits_per_word);
  266. fifo_threshold = DIV_ROUND_UP(priv->rx_bytes, bpw);
  267. fifo_threshold = min(fifo_threshold, SSI_FIFO_DEPTH);
  268. uniphier_spi_set_fifo_threshold(priv, fifo_threshold);
  269. fill_words = fifo_threshold -
  270. DIV_ROUND_UP(priv->rx_bytes - priv->tx_bytes, bpw);
  271. while (fill_words--)
  272. uniphier_spi_send(priv);
  273. }
  274. static void uniphier_spi_set_cs(struct spi_device *spi, bool enable)
  275. {
  276. struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
  277. u32 val;
  278. val = readl(priv->base + SSI_FPS);
  279. if (enable)
  280. val |= SSI_FPS_FSPOL;
  281. else
  282. val &= ~SSI_FPS_FSPOL;
  283. writel(val, priv->base + SSI_FPS);
  284. }
  285. static bool uniphier_spi_can_dma(struct spi_master *master,
  286. struct spi_device *spi,
  287. struct spi_transfer *t)
  288. {
  289. struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
  290. unsigned int bpw = bytes_per_word(priv->bits_per_word);
  291. if ((!master->dma_tx && !master->dma_rx)
  292. || (!master->dma_tx && t->tx_buf)
  293. || (!master->dma_rx && t->rx_buf))
  294. return false;
  295. return DIV_ROUND_UP(t->len, bpw) > SSI_FIFO_DEPTH;
  296. }
  297. static void uniphier_spi_dma_rxcb(void *data)
  298. {
  299. struct spi_master *master = data;
  300. struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
  301. int state = atomic_fetch_andnot(SSI_DMA_RX_BUSY, &priv->dma_busy);
  302. uniphier_spi_irq_disable(priv, SSI_IE_RXRE);
  303. if (!(state & SSI_DMA_TX_BUSY))
  304. spi_finalize_current_transfer(master);
  305. }
  306. static void uniphier_spi_dma_txcb(void *data)
  307. {
  308. struct spi_master *master = data;
  309. struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
  310. int state = atomic_fetch_andnot(SSI_DMA_TX_BUSY, &priv->dma_busy);
  311. uniphier_spi_irq_disable(priv, SSI_IE_TXRE);
  312. if (!(state & SSI_DMA_RX_BUSY))
  313. spi_finalize_current_transfer(master);
  314. }
  315. static int uniphier_spi_transfer_one_dma(struct spi_master *master,
  316. struct spi_device *spi,
  317. struct spi_transfer *t)
  318. {
  319. struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
  320. struct dma_async_tx_descriptor *rxdesc = NULL, *txdesc = NULL;
  321. int buswidth;
  322. atomic_set(&priv->dma_busy, 0);
  323. uniphier_spi_set_fifo_threshold(priv, SSI_FIFO_BURST_NUM);
  324. if (priv->bits_per_word <= 8)
  325. buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
  326. else if (priv->bits_per_word <= 16)
  327. buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
  328. else
  329. buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
  330. if (priv->rx_buf) {
  331. struct dma_slave_config rxconf = {
  332. .direction = DMA_DEV_TO_MEM,
  333. .src_addr = priv->base_dma_addr + SSI_RXDR,
  334. .src_addr_width = buswidth,
  335. .src_maxburst = SSI_FIFO_BURST_NUM,
  336. };
  337. dmaengine_slave_config(master->dma_rx, &rxconf);
  338. rxdesc = dmaengine_prep_slave_sg(
  339. master->dma_rx,
  340. t->rx_sg.sgl, t->rx_sg.nents,
  341. DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  342. if (!rxdesc)
  343. goto out_err_prep;
  344. rxdesc->callback = uniphier_spi_dma_rxcb;
  345. rxdesc->callback_param = master;
  346. uniphier_spi_irq_enable(priv, SSI_IE_RXRE);
  347. atomic_or(SSI_DMA_RX_BUSY, &priv->dma_busy);
  348. dmaengine_submit(rxdesc);
  349. dma_async_issue_pending(master->dma_rx);
  350. }
  351. if (priv->tx_buf) {
  352. struct dma_slave_config txconf = {
  353. .direction = DMA_MEM_TO_DEV,
  354. .dst_addr = priv->base_dma_addr + SSI_TXDR,
  355. .dst_addr_width = buswidth,
  356. .dst_maxburst = SSI_FIFO_BURST_NUM,
  357. };
  358. dmaengine_slave_config(master->dma_tx, &txconf);
  359. txdesc = dmaengine_prep_slave_sg(
  360. master->dma_tx,
  361. t->tx_sg.sgl, t->tx_sg.nents,
  362. DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  363. if (!txdesc)
  364. goto out_err_prep;
  365. txdesc->callback = uniphier_spi_dma_txcb;
  366. txdesc->callback_param = master;
  367. uniphier_spi_irq_enable(priv, SSI_IE_TXRE);
  368. atomic_or(SSI_DMA_TX_BUSY, &priv->dma_busy);
  369. dmaengine_submit(txdesc);
  370. dma_async_issue_pending(master->dma_tx);
  371. }
  372. /* signal that we need to wait for completion */
  373. return (priv->tx_buf || priv->rx_buf);
  374. out_err_prep:
  375. if (rxdesc)
  376. dmaengine_terminate_sync(master->dma_rx);
  377. return -EINVAL;
  378. }
  379. static int uniphier_spi_transfer_one_irq(struct spi_master *master,
  380. struct spi_device *spi,
  381. struct spi_transfer *t)
  382. {
  383. struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
  384. struct device *dev = master->dev.parent;
  385. unsigned long time_left;
  386. reinit_completion(&priv->xfer_done);
  387. uniphier_spi_fill_tx_fifo(priv);
  388. uniphier_spi_irq_enable(priv, SSI_IE_RCIE | SSI_IE_RORIE);
  389. time_left = wait_for_completion_timeout(&priv->xfer_done,
  390. msecs_to_jiffies(SSI_TIMEOUT_MS));
  391. uniphier_spi_irq_disable(priv, SSI_IE_RCIE | SSI_IE_RORIE);
  392. if (!time_left) {
  393. dev_err(dev, "transfer timeout.\n");
  394. return -ETIMEDOUT;
  395. }
  396. return priv->error;
  397. }
  398. static int uniphier_spi_transfer_one_poll(struct spi_master *master,
  399. struct spi_device *spi,
  400. struct spi_transfer *t)
  401. {
  402. struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
  403. int loop = SSI_POLL_TIMEOUT_US * 10;
  404. while (priv->tx_bytes) {
  405. uniphier_spi_fill_tx_fifo(priv);
  406. while ((priv->rx_bytes - priv->tx_bytes) > 0) {
  407. while (!(readl(priv->base + SSI_SR) & SSI_SR_RNE)
  408. && loop--)
  409. ndelay(100);
  410. if (loop == -1)
  411. goto irq_transfer;
  412. uniphier_spi_recv(priv);
  413. }
  414. }
  415. return 0;
  416. irq_transfer:
  417. return uniphier_spi_transfer_one_irq(master, spi, t);
  418. }
  419. static int uniphier_spi_transfer_one(struct spi_master *master,
  420. struct spi_device *spi,
  421. struct spi_transfer *t)
  422. {
  423. struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
  424. unsigned long threshold;
  425. bool use_dma;
  426. /* Terminate and return success for 0 byte length transfer */
  427. if (!t->len)
  428. return 0;
  429. uniphier_spi_setup_transfer(spi, t);
  430. use_dma = master->can_dma ? master->can_dma(master, spi, t) : false;
  431. if (use_dma)
  432. return uniphier_spi_transfer_one_dma(master, spi, t);
  433. /*
  434. * If the transfer operation will take longer than
  435. * SSI_POLL_TIMEOUT_US, it should use irq.
  436. */
  437. threshold = DIV_ROUND_UP(SSI_POLL_TIMEOUT_US * priv->speed_hz,
  438. USEC_PER_SEC * BITS_PER_BYTE);
  439. if (t->len > threshold)
  440. return uniphier_spi_transfer_one_irq(master, spi, t);
  441. else
  442. return uniphier_spi_transfer_one_poll(master, spi, t);
  443. }
  444. static int uniphier_spi_prepare_transfer_hardware(struct spi_master *master)
  445. {
  446. struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
  447. writel(SSI_CTL_EN, priv->base + SSI_CTL);
  448. return 0;
  449. }
  450. static int uniphier_spi_unprepare_transfer_hardware(struct spi_master *master)
  451. {
  452. struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
  453. writel(0, priv->base + SSI_CTL);
  454. return 0;
  455. }
  456. static void uniphier_spi_handle_err(struct spi_master *master,
  457. struct spi_message *msg)
  458. {
  459. struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
  460. u32 val;
  461. /* stop running spi transfer */
  462. writel(0, priv->base + SSI_CTL);
  463. /* reset FIFOs */
  464. val = SSI_FC_TXFFL | SSI_FC_RXFFL;
  465. writel(val, priv->base + SSI_FC);
  466. uniphier_spi_irq_disable(priv, SSI_IE_ALL_MASK);
  467. if (atomic_read(&priv->dma_busy) & SSI_DMA_TX_BUSY) {
  468. dmaengine_terminate_async(master->dma_tx);
  469. atomic_andnot(SSI_DMA_TX_BUSY, &priv->dma_busy);
  470. }
  471. if (atomic_read(&priv->dma_busy) & SSI_DMA_RX_BUSY) {
  472. dmaengine_terminate_async(master->dma_rx);
  473. atomic_andnot(SSI_DMA_RX_BUSY, &priv->dma_busy);
  474. }
  475. }
  476. static irqreturn_t uniphier_spi_handler(int irq, void *dev_id)
  477. {
  478. struct uniphier_spi_priv *priv = dev_id;
  479. u32 val, stat;
  480. stat = readl(priv->base + SSI_IS);
  481. val = SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC;
  482. writel(val, priv->base + SSI_IC);
  483. /* rx fifo overrun */
  484. if (stat & SSI_IS_RORID) {
  485. priv->error = -EIO;
  486. goto done;
  487. }
  488. /* rx complete */
  489. if ((stat & SSI_IS_RCID) && (stat & SSI_IS_RXRS)) {
  490. while ((readl(priv->base + SSI_SR) & SSI_SR_RNE) &&
  491. (priv->rx_bytes - priv->tx_bytes) > 0)
  492. uniphier_spi_recv(priv);
  493. if ((readl(priv->base + SSI_SR) & SSI_SR_RNE) ||
  494. (priv->rx_bytes != priv->tx_bytes)) {
  495. priv->error = -EIO;
  496. goto done;
  497. } else if (priv->rx_bytes == 0)
  498. goto done;
  499. /* next tx transfer */
  500. uniphier_spi_fill_tx_fifo(priv);
  501. return IRQ_HANDLED;
  502. }
  503. return IRQ_NONE;
  504. done:
  505. complete(&priv->xfer_done);
  506. return IRQ_HANDLED;
  507. }
  508. static int uniphier_spi_probe(struct platform_device *pdev)
  509. {
  510. struct uniphier_spi_priv *priv;
  511. struct spi_master *master;
  512. struct resource *res;
  513. struct dma_slave_caps caps;
  514. u32 dma_tx_burst = 0, dma_rx_burst = 0;
  515. unsigned long clk_rate;
  516. int irq;
  517. int ret;
  518. master = spi_alloc_master(&pdev->dev, sizeof(*priv));
  519. if (!master)
  520. return -ENOMEM;
  521. platform_set_drvdata(pdev, master);
  522. priv = spi_master_get_devdata(master);
  523. priv->master = master;
  524. priv->is_save_param = false;
  525. priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
  526. if (IS_ERR(priv->base)) {
  527. ret = PTR_ERR(priv->base);
  528. goto out_master_put;
  529. }
  530. priv->base_dma_addr = res->start;
  531. priv->clk = devm_clk_get(&pdev->dev, NULL);
  532. if (IS_ERR(priv->clk)) {
  533. dev_err(&pdev->dev, "failed to get clock\n");
  534. ret = PTR_ERR(priv->clk);
  535. goto out_master_put;
  536. }
  537. ret = clk_prepare_enable(priv->clk);
  538. if (ret)
  539. goto out_master_put;
  540. irq = platform_get_irq(pdev, 0);
  541. if (irq < 0) {
  542. ret = irq;
  543. goto out_disable_clk;
  544. }
  545. ret = devm_request_irq(&pdev->dev, irq, uniphier_spi_handler,
  546. 0, "uniphier-spi", priv);
  547. if (ret) {
  548. dev_err(&pdev->dev, "failed to request IRQ\n");
  549. goto out_disable_clk;
  550. }
  551. init_completion(&priv->xfer_done);
  552. clk_rate = clk_get_rate(priv->clk);
  553. master->max_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MIN_CLK_DIVIDER);
  554. master->min_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MAX_CLK_DIVIDER);
  555. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
  556. master->dev.of_node = pdev->dev.of_node;
  557. master->bus_num = pdev->id;
  558. master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
  559. master->set_cs = uniphier_spi_set_cs;
  560. master->transfer_one = uniphier_spi_transfer_one;
  561. master->prepare_transfer_hardware
  562. = uniphier_spi_prepare_transfer_hardware;
  563. master->unprepare_transfer_hardware
  564. = uniphier_spi_unprepare_transfer_hardware;
  565. master->handle_err = uniphier_spi_handle_err;
  566. master->can_dma = uniphier_spi_can_dma;
  567. master->num_chipselect = 1;
  568. master->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
  569. master->dma_tx = dma_request_chan(&pdev->dev, "tx");
  570. if (IS_ERR_OR_NULL(master->dma_tx)) {
  571. if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) {
  572. ret = -EPROBE_DEFER;
  573. goto out_disable_clk;
  574. }
  575. master->dma_tx = NULL;
  576. dma_tx_burst = INT_MAX;
  577. } else {
  578. ret = dma_get_slave_caps(master->dma_tx, &caps);
  579. if (ret) {
  580. dev_err(&pdev->dev, "failed to get TX DMA capacities: %d\n",
  581. ret);
  582. goto out_release_dma;
  583. }
  584. dma_tx_burst = caps.max_burst;
  585. }
  586. master->dma_rx = dma_request_chan(&pdev->dev, "rx");
  587. if (IS_ERR_OR_NULL(master->dma_rx)) {
  588. if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) {
  589. ret = -EPROBE_DEFER;
  590. goto out_release_dma;
  591. }
  592. master->dma_rx = NULL;
  593. dma_rx_burst = INT_MAX;
  594. } else {
  595. ret = dma_get_slave_caps(master->dma_rx, &caps);
  596. if (ret) {
  597. dev_err(&pdev->dev, "failed to get RX DMA capacities: %d\n",
  598. ret);
  599. goto out_release_dma;
  600. }
  601. dma_rx_burst = caps.max_burst;
  602. }
  603. master->max_dma_len = min(dma_tx_burst, dma_rx_burst);
  604. ret = devm_spi_register_master(&pdev->dev, master);
  605. if (ret)
  606. goto out_release_dma;
  607. return 0;
  608. out_release_dma:
  609. if (!IS_ERR_OR_NULL(master->dma_rx)) {
  610. dma_release_channel(master->dma_rx);
  611. master->dma_rx = NULL;
  612. }
  613. if (!IS_ERR_OR_NULL(master->dma_tx)) {
  614. dma_release_channel(master->dma_tx);
  615. master->dma_tx = NULL;
  616. }
  617. out_disable_clk:
  618. clk_disable_unprepare(priv->clk);
  619. out_master_put:
  620. spi_master_put(master);
  621. return ret;
  622. }
  623. static int uniphier_spi_remove(struct platform_device *pdev)
  624. {
  625. struct spi_master *master = platform_get_drvdata(pdev);
  626. struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
  627. if (master->dma_tx)
  628. dma_release_channel(master->dma_tx);
  629. if (master->dma_rx)
  630. dma_release_channel(master->dma_rx);
  631. clk_disable_unprepare(priv->clk);
  632. return 0;
  633. }
  634. static const struct of_device_id uniphier_spi_match[] = {
  635. { .compatible = "socionext,uniphier-scssi" },
  636. { /* sentinel */ }
  637. };
  638. MODULE_DEVICE_TABLE(of, uniphier_spi_match);
  639. static struct platform_driver uniphier_spi_driver = {
  640. .probe = uniphier_spi_probe,
  641. .remove = uniphier_spi_remove,
  642. .driver = {
  643. .name = "uniphier-spi",
  644. .of_match_table = uniphier_spi_match,
  645. },
  646. };
  647. module_platform_driver(uniphier_spi_driver);
  648. MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
  649. MODULE_AUTHOR("Keiji Hayashibara <hayashibara.keiji@socionext.com>");
  650. MODULE_DESCRIPTION("Socionext UniPhier SPI controller driver");
  651. MODULE_LICENSE("GPL v2");