spi-txx9.c 13 KB

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  1. /*
  2. * TXx9 SPI controller driver.
  3. *
  4. * Based on linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
  5. * Copyright (C) 2000-2001 Toshiba Corporation
  6. *
  7. * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
  8. * terms of the GNU General Public License version 2. This program is
  9. * licensed "as is" without any warranty of any kind, whether express
  10. * or implied.
  11. *
  12. * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  13. *
  14. * Convert to generic SPI framework - Atsushi Nemoto (anemo@mba.ocn.ne.jp)
  15. */
  16. #include <linux/init.h>
  17. #include <linux/delay.h>
  18. #include <linux/errno.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/sched.h>
  22. #include <linux/spinlock.h>
  23. #include <linux/workqueue.h>
  24. #include <linux/spi/spi.h>
  25. #include <linux/err.h>
  26. #include <linux/clk.h>
  27. #include <linux/io.h>
  28. #include <linux/module.h>
  29. #include <linux/gpio/machine.h>
  30. #include <linux/gpio/consumer.h>
  31. #define SPI_FIFO_SIZE 4
  32. #define SPI_MAX_DIVIDER 0xff /* Max. value for SPCR1.SER */
  33. #define SPI_MIN_DIVIDER 1 /* Min. value for SPCR1.SER */
  34. #define TXx9_SPMCR 0x00
  35. #define TXx9_SPCR0 0x04
  36. #define TXx9_SPCR1 0x08
  37. #define TXx9_SPFS 0x0c
  38. #define TXx9_SPSR 0x14
  39. #define TXx9_SPDR 0x18
  40. /* SPMCR : SPI Master Control */
  41. #define TXx9_SPMCR_OPMODE 0xc0
  42. #define TXx9_SPMCR_CONFIG 0x40
  43. #define TXx9_SPMCR_ACTIVE 0x80
  44. #define TXx9_SPMCR_SPSTP 0x02
  45. #define TXx9_SPMCR_BCLR 0x01
  46. /* SPCR0 : SPI Control 0 */
  47. #define TXx9_SPCR0_TXIFL_MASK 0xc000
  48. #define TXx9_SPCR0_RXIFL_MASK 0x3000
  49. #define TXx9_SPCR0_SIDIE 0x0800
  50. #define TXx9_SPCR0_SOEIE 0x0400
  51. #define TXx9_SPCR0_RBSIE 0x0200
  52. #define TXx9_SPCR0_TBSIE 0x0100
  53. #define TXx9_SPCR0_IFSPSE 0x0010
  54. #define TXx9_SPCR0_SBOS 0x0004
  55. #define TXx9_SPCR0_SPHA 0x0002
  56. #define TXx9_SPCR0_SPOL 0x0001
  57. /* SPSR : SPI Status */
  58. #define TXx9_SPSR_TBSI 0x8000
  59. #define TXx9_SPSR_RBSI 0x4000
  60. #define TXx9_SPSR_TBS_MASK 0x3800
  61. #define TXx9_SPSR_RBS_MASK 0x0700
  62. #define TXx9_SPSR_SPOE 0x0080
  63. #define TXx9_SPSR_IFSD 0x0008
  64. #define TXx9_SPSR_SIDLE 0x0004
  65. #define TXx9_SPSR_STRDY 0x0002
  66. #define TXx9_SPSR_SRRDY 0x0001
  67. struct txx9spi {
  68. struct work_struct work;
  69. spinlock_t lock; /* protect 'queue' */
  70. struct list_head queue;
  71. wait_queue_head_t waitq;
  72. void __iomem *membase;
  73. int baseclk;
  74. struct clk *clk;
  75. struct gpio_desc *last_chipselect;
  76. int last_chipselect_val;
  77. };
  78. static u32 txx9spi_rd(struct txx9spi *c, int reg)
  79. {
  80. return __raw_readl(c->membase + reg);
  81. }
  82. static void txx9spi_wr(struct txx9spi *c, u32 val, int reg)
  83. {
  84. __raw_writel(val, c->membase + reg);
  85. }
  86. static void txx9spi_cs_func(struct spi_device *spi, struct txx9spi *c,
  87. int on, unsigned int cs_delay)
  88. {
  89. /*
  90. * The GPIO descriptor will track polarity inversion inside
  91. * gpiolib.
  92. */
  93. if (on) {
  94. /* deselect the chip with cs_change hint in last transfer */
  95. if (c->last_chipselect)
  96. gpiod_set_value(c->last_chipselect,
  97. !c->last_chipselect_val);
  98. c->last_chipselect = spi->cs_gpiod;
  99. c->last_chipselect_val = on;
  100. } else {
  101. c->last_chipselect = NULL;
  102. ndelay(cs_delay); /* CS Hold Time */
  103. }
  104. gpiod_set_value(spi->cs_gpiod, on);
  105. ndelay(cs_delay); /* CS Setup Time / CS Recovery Time */
  106. }
  107. static int txx9spi_setup(struct spi_device *spi)
  108. {
  109. struct txx9spi *c = spi_master_get_devdata(spi->master);
  110. if (!spi->max_speed_hz)
  111. return -EINVAL;
  112. /* deselect chip */
  113. spin_lock(&c->lock);
  114. txx9spi_cs_func(spi, c, 0, (NSEC_PER_SEC / 2) / spi->max_speed_hz);
  115. spin_unlock(&c->lock);
  116. return 0;
  117. }
  118. static irqreturn_t txx9spi_interrupt(int irq, void *dev_id)
  119. {
  120. struct txx9spi *c = dev_id;
  121. /* disable rx intr */
  122. txx9spi_wr(c, txx9spi_rd(c, TXx9_SPCR0) & ~TXx9_SPCR0_RBSIE,
  123. TXx9_SPCR0);
  124. wake_up(&c->waitq);
  125. return IRQ_HANDLED;
  126. }
  127. static void txx9spi_work_one(struct txx9spi *c, struct spi_message *m)
  128. {
  129. struct spi_device *spi = m->spi;
  130. struct spi_transfer *t;
  131. unsigned int cs_delay;
  132. unsigned int cs_change = 1;
  133. int status = 0;
  134. u32 mcr;
  135. u32 prev_speed_hz = 0;
  136. u8 prev_bits_per_word = 0;
  137. /* CS setup/hold/recovery time in nsec */
  138. cs_delay = 100 + (NSEC_PER_SEC / 2) / spi->max_speed_hz;
  139. mcr = txx9spi_rd(c, TXx9_SPMCR);
  140. if (unlikely((mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE)) {
  141. dev_err(&spi->dev, "Bad mode.\n");
  142. status = -EIO;
  143. goto exit;
  144. }
  145. mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);
  146. /* enter config mode */
  147. txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
  148. txx9spi_wr(c, TXx9_SPCR0_SBOS
  149. | ((spi->mode & SPI_CPOL) ? TXx9_SPCR0_SPOL : 0)
  150. | ((spi->mode & SPI_CPHA) ? TXx9_SPCR0_SPHA : 0)
  151. | 0x08,
  152. TXx9_SPCR0);
  153. list_for_each_entry(t, &m->transfers, transfer_list) {
  154. const void *txbuf = t->tx_buf;
  155. void *rxbuf = t->rx_buf;
  156. u32 data;
  157. unsigned int len = t->len;
  158. unsigned int wsize;
  159. u32 speed_hz = t->speed_hz;
  160. u8 bits_per_word = t->bits_per_word;
  161. wsize = bits_per_word >> 3; /* in bytes */
  162. if (prev_speed_hz != speed_hz
  163. || prev_bits_per_word != bits_per_word) {
  164. int n = DIV_ROUND_UP(c->baseclk, speed_hz) - 1;
  165. n = clamp(n, SPI_MIN_DIVIDER, SPI_MAX_DIVIDER);
  166. /* enter config mode */
  167. txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR,
  168. TXx9_SPMCR);
  169. txx9spi_wr(c, (n << 8) | bits_per_word, TXx9_SPCR1);
  170. /* enter active mode */
  171. txx9spi_wr(c, mcr | TXx9_SPMCR_ACTIVE, TXx9_SPMCR);
  172. prev_speed_hz = speed_hz;
  173. prev_bits_per_word = bits_per_word;
  174. }
  175. if (cs_change)
  176. txx9spi_cs_func(spi, c, 1, cs_delay);
  177. cs_change = t->cs_change;
  178. while (len) {
  179. unsigned int count = SPI_FIFO_SIZE;
  180. int i;
  181. u32 cr0;
  182. if (len < count * wsize)
  183. count = len / wsize;
  184. /* now tx must be idle... */
  185. while (!(txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_SIDLE))
  186. cpu_relax();
  187. cr0 = txx9spi_rd(c, TXx9_SPCR0);
  188. cr0 &= ~TXx9_SPCR0_RXIFL_MASK;
  189. cr0 |= (count - 1) << 12;
  190. /* enable rx intr */
  191. cr0 |= TXx9_SPCR0_RBSIE;
  192. txx9spi_wr(c, cr0, TXx9_SPCR0);
  193. /* send */
  194. for (i = 0; i < count; i++) {
  195. if (txbuf) {
  196. data = (wsize == 1)
  197. ? *(const u8 *)txbuf
  198. : *(const u16 *)txbuf;
  199. txx9spi_wr(c, data, TXx9_SPDR);
  200. txbuf += wsize;
  201. } else
  202. txx9spi_wr(c, 0, TXx9_SPDR);
  203. }
  204. /* wait all rx data */
  205. wait_event(c->waitq,
  206. txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_RBSI);
  207. /* receive */
  208. for (i = 0; i < count; i++) {
  209. data = txx9spi_rd(c, TXx9_SPDR);
  210. if (rxbuf) {
  211. if (wsize == 1)
  212. *(u8 *)rxbuf = data;
  213. else
  214. *(u16 *)rxbuf = data;
  215. rxbuf += wsize;
  216. }
  217. }
  218. len -= count * wsize;
  219. }
  220. m->actual_length += t->len;
  221. spi_transfer_delay_exec(t);
  222. if (!cs_change)
  223. continue;
  224. if (t->transfer_list.next == &m->transfers)
  225. break;
  226. /* sometimes a short mid-message deselect of the chip
  227. * may be needed to terminate a mode or command
  228. */
  229. txx9spi_cs_func(spi, c, 0, cs_delay);
  230. }
  231. exit:
  232. m->status = status;
  233. if (m->complete)
  234. m->complete(m->context);
  235. /* normally deactivate chipselect ... unless no error and
  236. * cs_change has hinted that the next message will probably
  237. * be for this chip too.
  238. */
  239. if (!(status == 0 && cs_change))
  240. txx9spi_cs_func(spi, c, 0, cs_delay);
  241. /* enter config mode */
  242. txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
  243. }
  244. static void txx9spi_work(struct work_struct *work)
  245. {
  246. struct txx9spi *c = container_of(work, struct txx9spi, work);
  247. unsigned long flags;
  248. spin_lock_irqsave(&c->lock, flags);
  249. while (!list_empty(&c->queue)) {
  250. struct spi_message *m;
  251. m = container_of(c->queue.next, struct spi_message, queue);
  252. list_del_init(&m->queue);
  253. spin_unlock_irqrestore(&c->lock, flags);
  254. txx9spi_work_one(c, m);
  255. spin_lock_irqsave(&c->lock, flags);
  256. }
  257. spin_unlock_irqrestore(&c->lock, flags);
  258. }
  259. static int txx9spi_transfer(struct spi_device *spi, struct spi_message *m)
  260. {
  261. struct spi_master *master = spi->master;
  262. struct txx9spi *c = spi_master_get_devdata(master);
  263. struct spi_transfer *t;
  264. unsigned long flags;
  265. m->actual_length = 0;
  266. /* check each transfer's parameters */
  267. list_for_each_entry(t, &m->transfers, transfer_list) {
  268. if (!t->tx_buf && !t->rx_buf && t->len)
  269. return -EINVAL;
  270. }
  271. spin_lock_irqsave(&c->lock, flags);
  272. list_add_tail(&m->queue, &c->queue);
  273. schedule_work(&c->work);
  274. spin_unlock_irqrestore(&c->lock, flags);
  275. return 0;
  276. }
  277. /*
  278. * Chip select uses GPIO only, further the driver is using the chip select
  279. * numer (from the device tree "reg" property, and this can only come from
  280. * device tree since this i MIPS and there is no way to pass platform data) as
  281. * the GPIO number. As the platform has only one GPIO controller (the txx9 GPIO
  282. * chip) it is thus using the chip select number as an offset into that chip.
  283. * This chip has a maximum of 16 GPIOs 0..15 and this is what all platforms
  284. * register.
  285. *
  286. * We modernized this behaviour by explicitly converting that offset to an
  287. * offset on the GPIO chip using a GPIO descriptor machine table of the same
  288. * size as the txx9 GPIO chip with a 1-to-1 mapping of chip select to GPIO
  289. * offset.
  290. *
  291. * This is admittedly a hack, but it is countering the hack of using "reg" to
  292. * contain a GPIO offset when it should be using "cs-gpios" as the SPI bindings
  293. * state.
  294. */
  295. static struct gpiod_lookup_table txx9spi_cs_gpio_table = {
  296. .dev_id = "spi0",
  297. .table = {
  298. GPIO_LOOKUP_IDX("TXx9", 0, "cs", 0, GPIO_ACTIVE_LOW),
  299. GPIO_LOOKUP_IDX("TXx9", 1, "cs", 1, GPIO_ACTIVE_LOW),
  300. GPIO_LOOKUP_IDX("TXx9", 2, "cs", 2, GPIO_ACTIVE_LOW),
  301. GPIO_LOOKUP_IDX("TXx9", 3, "cs", 3, GPIO_ACTIVE_LOW),
  302. GPIO_LOOKUP_IDX("TXx9", 4, "cs", 4, GPIO_ACTIVE_LOW),
  303. GPIO_LOOKUP_IDX("TXx9", 5, "cs", 5, GPIO_ACTIVE_LOW),
  304. GPIO_LOOKUP_IDX("TXx9", 6, "cs", 6, GPIO_ACTIVE_LOW),
  305. GPIO_LOOKUP_IDX("TXx9", 7, "cs", 7, GPIO_ACTIVE_LOW),
  306. GPIO_LOOKUP_IDX("TXx9", 8, "cs", 8, GPIO_ACTIVE_LOW),
  307. GPIO_LOOKUP_IDX("TXx9", 9, "cs", 9, GPIO_ACTIVE_LOW),
  308. GPIO_LOOKUP_IDX("TXx9", 10, "cs", 10, GPIO_ACTIVE_LOW),
  309. GPIO_LOOKUP_IDX("TXx9", 11, "cs", 11, GPIO_ACTIVE_LOW),
  310. GPIO_LOOKUP_IDX("TXx9", 12, "cs", 12, GPIO_ACTIVE_LOW),
  311. GPIO_LOOKUP_IDX("TXx9", 13, "cs", 13, GPIO_ACTIVE_LOW),
  312. GPIO_LOOKUP_IDX("TXx9", 14, "cs", 14, GPIO_ACTIVE_LOW),
  313. GPIO_LOOKUP_IDX("TXx9", 15, "cs", 15, GPIO_ACTIVE_LOW),
  314. { },
  315. },
  316. };
  317. static int txx9spi_probe(struct platform_device *dev)
  318. {
  319. struct spi_master *master;
  320. struct txx9spi *c;
  321. struct resource *res;
  322. int ret = -ENODEV;
  323. u32 mcr;
  324. int irq;
  325. master = spi_alloc_master(&dev->dev, sizeof(*c));
  326. if (!master)
  327. return ret;
  328. c = spi_master_get_devdata(master);
  329. platform_set_drvdata(dev, master);
  330. INIT_WORK(&c->work, txx9spi_work);
  331. spin_lock_init(&c->lock);
  332. INIT_LIST_HEAD(&c->queue);
  333. init_waitqueue_head(&c->waitq);
  334. c->clk = devm_clk_get(&dev->dev, "spi-baseclk");
  335. if (IS_ERR(c->clk)) {
  336. ret = PTR_ERR(c->clk);
  337. c->clk = NULL;
  338. goto exit;
  339. }
  340. ret = clk_prepare_enable(c->clk);
  341. if (ret) {
  342. c->clk = NULL;
  343. goto exit;
  344. }
  345. c->baseclk = clk_get_rate(c->clk);
  346. master->min_speed_hz = DIV_ROUND_UP(c->baseclk, SPI_MAX_DIVIDER + 1);
  347. master->max_speed_hz = c->baseclk / (SPI_MIN_DIVIDER + 1);
  348. res = platform_get_resource(dev, IORESOURCE_MEM, 0);
  349. c->membase = devm_ioremap_resource(&dev->dev, res);
  350. if (IS_ERR(c->membase))
  351. goto exit_busy;
  352. /* enter config mode */
  353. mcr = txx9spi_rd(c, TXx9_SPMCR);
  354. mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);
  355. txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
  356. irq = platform_get_irq(dev, 0);
  357. if (irq < 0)
  358. goto exit_busy;
  359. ret = devm_request_irq(&dev->dev, irq, txx9spi_interrupt, 0,
  360. "spi_txx9", c);
  361. if (ret)
  362. goto exit;
  363. c->last_chipselect = NULL;
  364. dev_info(&dev->dev, "at %#llx, irq %d, %dMHz\n",
  365. (unsigned long long)res->start, irq,
  366. (c->baseclk + 500000) / 1000000);
  367. gpiod_add_lookup_table(&txx9spi_cs_gpio_table);
  368. /* the spi->mode bits understood by this driver: */
  369. master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
  370. master->bus_num = dev->id;
  371. master->setup = txx9spi_setup;
  372. master->transfer = txx9spi_transfer;
  373. master->num_chipselect = (u16)UINT_MAX; /* any GPIO numbers */
  374. master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
  375. master->use_gpio_descriptors = true;
  376. ret = devm_spi_register_master(&dev->dev, master);
  377. if (ret)
  378. goto exit;
  379. return 0;
  380. exit_busy:
  381. ret = -EBUSY;
  382. exit:
  383. clk_disable_unprepare(c->clk);
  384. spi_master_put(master);
  385. return ret;
  386. }
  387. static int txx9spi_remove(struct platform_device *dev)
  388. {
  389. struct spi_master *master = platform_get_drvdata(dev);
  390. struct txx9spi *c = spi_master_get_devdata(master);
  391. flush_work(&c->work);
  392. clk_disable_unprepare(c->clk);
  393. return 0;
  394. }
  395. /* work with hotplug and coldplug */
  396. MODULE_ALIAS("platform:spi_txx9");
  397. static struct platform_driver txx9spi_driver = {
  398. .probe = txx9spi_probe,
  399. .remove = txx9spi_remove,
  400. .driver = {
  401. .name = "spi_txx9",
  402. },
  403. };
  404. static int __init txx9spi_init(void)
  405. {
  406. return platform_driver_register(&txx9spi_driver);
  407. }
  408. subsys_initcall(txx9spi_init);
  409. static void __exit txx9spi_exit(void)
  410. {
  411. platform_driver_unregister(&txx9spi_driver);
  412. }
  413. module_exit(txx9spi_exit);
  414. MODULE_DESCRIPTION("TXx9 SPI Driver");
  415. MODULE_LICENSE("GPL");