spi-tegra20-slink.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller.
  4. *
  5. * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/completion.h>
  9. #include <linux/delay.h>
  10. #include <linux/dmaengine.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/dmapool.h>
  13. #include <linux/err.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/kernel.h>
  17. #include <linux/kthread.h>
  18. #include <linux/module.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/of.h>
  22. #include <linux/of_device.h>
  23. #include <linux/reset.h>
  24. #include <linux/spi/spi.h>
  25. #define SLINK_COMMAND 0x000
  26. #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
  27. #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5)
  28. #define SLINK_BOTH_EN (1 << 10)
  29. #define SLINK_CS_SW (1 << 11)
  30. #define SLINK_CS_VALUE (1 << 12)
  31. #define SLINK_CS_POLARITY (1 << 13)
  32. #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16)
  33. #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16)
  34. #define SLINK_IDLE_SDA_PULL_LOW (2 << 16)
  35. #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16)
  36. #define SLINK_IDLE_SDA_MASK (3 << 16)
  37. #define SLINK_CS_POLARITY1 (1 << 20)
  38. #define SLINK_CK_SDA (1 << 21)
  39. #define SLINK_CS_POLARITY2 (1 << 22)
  40. #define SLINK_CS_POLARITY3 (1 << 23)
  41. #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24)
  42. #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24)
  43. #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24)
  44. #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24)
  45. #define SLINK_IDLE_SCLK_MASK (3 << 24)
  46. #define SLINK_M_S (1 << 28)
  47. #define SLINK_WAIT (1 << 29)
  48. #define SLINK_GO (1 << 30)
  49. #define SLINK_ENB (1 << 31)
  50. #define SLINK_MODES (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA)
  51. #define SLINK_COMMAND2 0x004
  52. #define SLINK_LSBFE (1 << 0)
  53. #define SLINK_SSOE (1 << 1)
  54. #define SLINK_SPIE (1 << 4)
  55. #define SLINK_BIDIROE (1 << 6)
  56. #define SLINK_MODFEN (1 << 7)
  57. #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8)
  58. #define SLINK_CS_ACTIVE_BETWEEN (1 << 17)
  59. #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18)
  60. #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20)
  61. #define SLINK_FIFO_REFILLS_0 (0 << 22)
  62. #define SLINK_FIFO_REFILLS_1 (1 << 22)
  63. #define SLINK_FIFO_REFILLS_2 (2 << 22)
  64. #define SLINK_FIFO_REFILLS_3 (3 << 22)
  65. #define SLINK_FIFO_REFILLS_MASK (3 << 22)
  66. #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26)
  67. #define SLINK_SPC0 (1 << 29)
  68. #define SLINK_TXEN (1 << 30)
  69. #define SLINK_RXEN (1 << 31)
  70. #define SLINK_STATUS 0x008
  71. #define SLINK_COUNT(val) (((val) >> 0) & 0x1f)
  72. #define SLINK_WORD(val) (((val) >> 5) & 0x1f)
  73. #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff)
  74. #define SLINK_MODF (1 << 16)
  75. #define SLINK_RX_UNF (1 << 18)
  76. #define SLINK_TX_OVF (1 << 19)
  77. #define SLINK_TX_FULL (1 << 20)
  78. #define SLINK_TX_EMPTY (1 << 21)
  79. #define SLINK_RX_FULL (1 << 22)
  80. #define SLINK_RX_EMPTY (1 << 23)
  81. #define SLINK_TX_UNF (1 << 24)
  82. #define SLINK_RX_OVF (1 << 25)
  83. #define SLINK_TX_FLUSH (1 << 26)
  84. #define SLINK_RX_FLUSH (1 << 27)
  85. #define SLINK_SCLK (1 << 28)
  86. #define SLINK_ERR (1 << 29)
  87. #define SLINK_RDY (1 << 30)
  88. #define SLINK_BSY (1 << 31)
  89. #define SLINK_FIFO_ERROR (SLINK_TX_OVF | SLINK_RX_UNF | \
  90. SLINK_TX_UNF | SLINK_RX_OVF)
  91. #define SLINK_FIFO_EMPTY (SLINK_TX_EMPTY | SLINK_RX_EMPTY)
  92. #define SLINK_MAS_DATA 0x010
  93. #define SLINK_SLAVE_DATA 0x014
  94. #define SLINK_DMA_CTL 0x018
  95. #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0)
  96. #define SLINK_TX_TRIG_1 (0 << 16)
  97. #define SLINK_TX_TRIG_4 (1 << 16)
  98. #define SLINK_TX_TRIG_8 (2 << 16)
  99. #define SLINK_TX_TRIG_16 (3 << 16)
  100. #define SLINK_TX_TRIG_MASK (3 << 16)
  101. #define SLINK_RX_TRIG_1 (0 << 18)
  102. #define SLINK_RX_TRIG_4 (1 << 18)
  103. #define SLINK_RX_TRIG_8 (2 << 18)
  104. #define SLINK_RX_TRIG_16 (3 << 18)
  105. #define SLINK_RX_TRIG_MASK (3 << 18)
  106. #define SLINK_PACKED (1 << 20)
  107. #define SLINK_PACK_SIZE_4 (0 << 21)
  108. #define SLINK_PACK_SIZE_8 (1 << 21)
  109. #define SLINK_PACK_SIZE_16 (2 << 21)
  110. #define SLINK_PACK_SIZE_32 (3 << 21)
  111. #define SLINK_PACK_SIZE_MASK (3 << 21)
  112. #define SLINK_IE_TXC (1 << 26)
  113. #define SLINK_IE_RXC (1 << 27)
  114. #define SLINK_DMA_EN (1 << 31)
  115. #define SLINK_STATUS2 0x01c
  116. #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0)
  117. #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16)
  118. #define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6)
  119. #define SLINK_TX_FIFO 0x100
  120. #define SLINK_RX_FIFO 0x180
  121. #define DATA_DIR_TX (1 << 0)
  122. #define DATA_DIR_RX (1 << 1)
  123. #define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000))
  124. #define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
  125. #define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20)
  126. #define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0)
  127. #define SLINK_STATUS2_RESET \
  128. (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16)
  129. #define MAX_CHIP_SELECT 4
  130. #define SLINK_FIFO_DEPTH 32
  131. struct tegra_slink_chip_data {
  132. bool cs_hold_time;
  133. };
  134. struct tegra_slink_data {
  135. struct device *dev;
  136. struct spi_master *master;
  137. const struct tegra_slink_chip_data *chip_data;
  138. spinlock_t lock;
  139. struct clk *clk;
  140. struct reset_control *rst;
  141. void __iomem *base;
  142. phys_addr_t phys;
  143. unsigned irq;
  144. u32 cur_speed;
  145. struct spi_device *cur_spi;
  146. unsigned cur_pos;
  147. unsigned cur_len;
  148. unsigned words_per_32bit;
  149. unsigned bytes_per_word;
  150. unsigned curr_dma_words;
  151. unsigned cur_direction;
  152. unsigned cur_rx_pos;
  153. unsigned cur_tx_pos;
  154. unsigned dma_buf_size;
  155. unsigned max_buf_size;
  156. bool is_curr_dma_xfer;
  157. struct completion rx_dma_complete;
  158. struct completion tx_dma_complete;
  159. u32 tx_status;
  160. u32 rx_status;
  161. u32 status_reg;
  162. bool is_packed;
  163. u32 packed_size;
  164. u32 command_reg;
  165. u32 command2_reg;
  166. u32 dma_control_reg;
  167. u32 def_command_reg;
  168. u32 def_command2_reg;
  169. struct completion xfer_completion;
  170. struct spi_transfer *curr_xfer;
  171. struct dma_chan *rx_dma_chan;
  172. u32 *rx_dma_buf;
  173. dma_addr_t rx_dma_phys;
  174. struct dma_async_tx_descriptor *rx_dma_desc;
  175. struct dma_chan *tx_dma_chan;
  176. u32 *tx_dma_buf;
  177. dma_addr_t tx_dma_phys;
  178. struct dma_async_tx_descriptor *tx_dma_desc;
  179. };
  180. static int tegra_slink_runtime_suspend(struct device *dev);
  181. static int tegra_slink_runtime_resume(struct device *dev);
  182. static inline u32 tegra_slink_readl(struct tegra_slink_data *tspi,
  183. unsigned long reg)
  184. {
  185. return readl(tspi->base + reg);
  186. }
  187. static inline void tegra_slink_writel(struct tegra_slink_data *tspi,
  188. u32 val, unsigned long reg)
  189. {
  190. writel(val, tspi->base + reg);
  191. /* Read back register to make sure that register writes completed */
  192. if (reg != SLINK_TX_FIFO)
  193. readl(tspi->base + SLINK_MAS_DATA);
  194. }
  195. static void tegra_slink_clear_status(struct tegra_slink_data *tspi)
  196. {
  197. u32 val_write;
  198. tegra_slink_readl(tspi, SLINK_STATUS);
  199. /* Write 1 to clear status register */
  200. val_write = SLINK_RDY | SLINK_FIFO_ERROR;
  201. tegra_slink_writel(tspi, val_write, SLINK_STATUS);
  202. }
  203. static u32 tegra_slink_get_packed_size(struct tegra_slink_data *tspi,
  204. struct spi_transfer *t)
  205. {
  206. switch (tspi->bytes_per_word) {
  207. case 0:
  208. return SLINK_PACK_SIZE_4;
  209. case 1:
  210. return SLINK_PACK_SIZE_8;
  211. case 2:
  212. return SLINK_PACK_SIZE_16;
  213. case 4:
  214. return SLINK_PACK_SIZE_32;
  215. default:
  216. return 0;
  217. }
  218. }
  219. static unsigned tegra_slink_calculate_curr_xfer_param(
  220. struct spi_device *spi, struct tegra_slink_data *tspi,
  221. struct spi_transfer *t)
  222. {
  223. unsigned remain_len = t->len - tspi->cur_pos;
  224. unsigned max_word;
  225. unsigned bits_per_word;
  226. unsigned max_len;
  227. unsigned total_fifo_words;
  228. bits_per_word = t->bits_per_word;
  229. tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
  230. if (bits_per_word == 8 || bits_per_word == 16) {
  231. tspi->is_packed = true;
  232. tspi->words_per_32bit = 32/bits_per_word;
  233. } else {
  234. tspi->is_packed = false;
  235. tspi->words_per_32bit = 1;
  236. }
  237. tspi->packed_size = tegra_slink_get_packed_size(tspi, t);
  238. if (tspi->is_packed) {
  239. max_len = min(remain_len, tspi->max_buf_size);
  240. tspi->curr_dma_words = max_len/tspi->bytes_per_word;
  241. total_fifo_words = max_len/4;
  242. } else {
  243. max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
  244. max_word = min(max_word, tspi->max_buf_size/4);
  245. tspi->curr_dma_words = max_word;
  246. total_fifo_words = max_word;
  247. }
  248. return total_fifo_words;
  249. }
  250. static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
  251. struct tegra_slink_data *tspi, struct spi_transfer *t)
  252. {
  253. unsigned nbytes;
  254. unsigned tx_empty_count;
  255. u32 fifo_status;
  256. unsigned max_n_32bit;
  257. unsigned i, count;
  258. unsigned int written_words;
  259. unsigned fifo_words_left;
  260. u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
  261. fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
  262. tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status);
  263. if (tspi->is_packed) {
  264. fifo_words_left = tx_empty_count * tspi->words_per_32bit;
  265. written_words = min(fifo_words_left, tspi->curr_dma_words);
  266. nbytes = written_words * tspi->bytes_per_word;
  267. max_n_32bit = DIV_ROUND_UP(nbytes, 4);
  268. for (count = 0; count < max_n_32bit; count++) {
  269. u32 x = 0;
  270. for (i = 0; (i < 4) && nbytes; i++, nbytes--)
  271. x |= (u32)(*tx_buf++) << (i * 8);
  272. tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
  273. }
  274. } else {
  275. max_n_32bit = min(tspi->curr_dma_words, tx_empty_count);
  276. written_words = max_n_32bit;
  277. nbytes = written_words * tspi->bytes_per_word;
  278. for (count = 0; count < max_n_32bit; count++) {
  279. u32 x = 0;
  280. for (i = 0; nbytes && (i < tspi->bytes_per_word);
  281. i++, nbytes--)
  282. x |= (u32)(*tx_buf++) << (i * 8);
  283. tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
  284. }
  285. }
  286. tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
  287. return written_words;
  288. }
  289. static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
  290. struct tegra_slink_data *tspi, struct spi_transfer *t)
  291. {
  292. unsigned rx_full_count;
  293. u32 fifo_status;
  294. unsigned i, count;
  295. unsigned int read_words = 0;
  296. unsigned len;
  297. u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
  298. fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
  299. rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status);
  300. if (tspi->is_packed) {
  301. len = tspi->curr_dma_words * tspi->bytes_per_word;
  302. for (count = 0; count < rx_full_count; count++) {
  303. u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
  304. for (i = 0; len && (i < 4); i++, len--)
  305. *rx_buf++ = (x >> i*8) & 0xFF;
  306. }
  307. tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
  308. read_words += tspi->curr_dma_words;
  309. } else {
  310. for (count = 0; count < rx_full_count; count++) {
  311. u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
  312. for (i = 0; (i < tspi->bytes_per_word); i++)
  313. *rx_buf++ = (x >> (i*8)) & 0xFF;
  314. }
  315. tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
  316. read_words += rx_full_count;
  317. }
  318. return read_words;
  319. }
  320. static void tegra_slink_copy_client_txbuf_to_spi_txbuf(
  321. struct tegra_slink_data *tspi, struct spi_transfer *t)
  322. {
  323. /* Make the dma buffer to read by cpu */
  324. dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
  325. tspi->dma_buf_size, DMA_TO_DEVICE);
  326. if (tspi->is_packed) {
  327. unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
  328. memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
  329. } else {
  330. unsigned int i;
  331. unsigned int count;
  332. u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
  333. unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
  334. for (count = 0; count < tspi->curr_dma_words; count++) {
  335. u32 x = 0;
  336. for (i = 0; consume && (i < tspi->bytes_per_word);
  337. i++, consume--)
  338. x |= (u32)(*tx_buf++) << (i * 8);
  339. tspi->tx_dma_buf[count] = x;
  340. }
  341. }
  342. tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
  343. /* Make the dma buffer to read by dma */
  344. dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
  345. tspi->dma_buf_size, DMA_TO_DEVICE);
  346. }
  347. static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf(
  348. struct tegra_slink_data *tspi, struct spi_transfer *t)
  349. {
  350. unsigned len;
  351. /* Make the dma buffer to read by cpu */
  352. dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
  353. tspi->dma_buf_size, DMA_FROM_DEVICE);
  354. if (tspi->is_packed) {
  355. len = tspi->curr_dma_words * tspi->bytes_per_word;
  356. memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
  357. } else {
  358. unsigned int i;
  359. unsigned int count;
  360. unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
  361. u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
  362. for (count = 0; count < tspi->curr_dma_words; count++) {
  363. u32 x = tspi->rx_dma_buf[count] & rx_mask;
  364. for (i = 0; (i < tspi->bytes_per_word); i++)
  365. *rx_buf++ = (x >> (i*8)) & 0xFF;
  366. }
  367. }
  368. tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
  369. /* Make the dma buffer to read by dma */
  370. dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
  371. tspi->dma_buf_size, DMA_FROM_DEVICE);
  372. }
  373. static void tegra_slink_dma_complete(void *args)
  374. {
  375. struct completion *dma_complete = args;
  376. complete(dma_complete);
  377. }
  378. static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len)
  379. {
  380. reinit_completion(&tspi->tx_dma_complete);
  381. tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
  382. tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
  383. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  384. if (!tspi->tx_dma_desc) {
  385. dev_err(tspi->dev, "Not able to get desc for Tx\n");
  386. return -EIO;
  387. }
  388. tspi->tx_dma_desc->callback = tegra_slink_dma_complete;
  389. tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
  390. dmaengine_submit(tspi->tx_dma_desc);
  391. dma_async_issue_pending(tspi->tx_dma_chan);
  392. return 0;
  393. }
  394. static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len)
  395. {
  396. reinit_completion(&tspi->rx_dma_complete);
  397. tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
  398. tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
  399. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  400. if (!tspi->rx_dma_desc) {
  401. dev_err(tspi->dev, "Not able to get desc for Rx\n");
  402. return -EIO;
  403. }
  404. tspi->rx_dma_desc->callback = tegra_slink_dma_complete;
  405. tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
  406. dmaengine_submit(tspi->rx_dma_desc);
  407. dma_async_issue_pending(tspi->rx_dma_chan);
  408. return 0;
  409. }
  410. static int tegra_slink_start_dma_based_transfer(
  411. struct tegra_slink_data *tspi, struct spi_transfer *t)
  412. {
  413. u32 val;
  414. unsigned int len;
  415. int ret = 0;
  416. u32 status;
  417. /* Make sure that Rx and Tx fifo are empty */
  418. status = tegra_slink_readl(tspi, SLINK_STATUS);
  419. if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) {
  420. dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n",
  421. (unsigned)status);
  422. return -EIO;
  423. }
  424. val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1);
  425. val |= tspi->packed_size;
  426. if (tspi->is_packed)
  427. len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
  428. 4) * 4;
  429. else
  430. len = tspi->curr_dma_words * 4;
  431. /* Set attention level based on length of transfer */
  432. if (len & 0xF)
  433. val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1;
  434. else if (((len) >> 4) & 0x1)
  435. val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4;
  436. else
  437. val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8;
  438. if (tspi->cur_direction & DATA_DIR_TX)
  439. val |= SLINK_IE_TXC;
  440. if (tspi->cur_direction & DATA_DIR_RX)
  441. val |= SLINK_IE_RXC;
  442. tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
  443. tspi->dma_control_reg = val;
  444. if (tspi->cur_direction & DATA_DIR_TX) {
  445. tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t);
  446. wmb();
  447. ret = tegra_slink_start_tx_dma(tspi, len);
  448. if (ret < 0) {
  449. dev_err(tspi->dev,
  450. "Starting tx dma failed, err %d\n", ret);
  451. return ret;
  452. }
  453. /* Wait for tx fifo to be fill before starting slink */
  454. status = tegra_slink_readl(tspi, SLINK_STATUS);
  455. while (!(status & SLINK_TX_FULL))
  456. status = tegra_slink_readl(tspi, SLINK_STATUS);
  457. }
  458. if (tspi->cur_direction & DATA_DIR_RX) {
  459. /* Make the dma buffer to read by dma */
  460. dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
  461. tspi->dma_buf_size, DMA_FROM_DEVICE);
  462. ret = tegra_slink_start_rx_dma(tspi, len);
  463. if (ret < 0) {
  464. dev_err(tspi->dev,
  465. "Starting rx dma failed, err %d\n", ret);
  466. if (tspi->cur_direction & DATA_DIR_TX)
  467. dmaengine_terminate_all(tspi->tx_dma_chan);
  468. return ret;
  469. }
  470. }
  471. tspi->is_curr_dma_xfer = true;
  472. if (tspi->is_packed) {
  473. val |= SLINK_PACKED;
  474. tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
  475. /* HW need small delay after settign Packed mode */
  476. udelay(1);
  477. }
  478. tspi->dma_control_reg = val;
  479. val |= SLINK_DMA_EN;
  480. tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
  481. return ret;
  482. }
  483. static int tegra_slink_start_cpu_based_transfer(
  484. struct tegra_slink_data *tspi, struct spi_transfer *t)
  485. {
  486. u32 val;
  487. unsigned cur_words;
  488. val = tspi->packed_size;
  489. if (tspi->cur_direction & DATA_DIR_TX)
  490. val |= SLINK_IE_TXC;
  491. if (tspi->cur_direction & DATA_DIR_RX)
  492. val |= SLINK_IE_RXC;
  493. tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
  494. tspi->dma_control_reg = val;
  495. if (tspi->cur_direction & DATA_DIR_TX)
  496. cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t);
  497. else
  498. cur_words = tspi->curr_dma_words;
  499. val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1);
  500. tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
  501. tspi->dma_control_reg = val;
  502. tspi->is_curr_dma_xfer = false;
  503. if (tspi->is_packed) {
  504. val |= SLINK_PACKED;
  505. tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
  506. udelay(1);
  507. wmb();
  508. }
  509. tspi->dma_control_reg = val;
  510. val |= SLINK_DMA_EN;
  511. tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
  512. return 0;
  513. }
  514. static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi,
  515. bool dma_to_memory)
  516. {
  517. struct dma_chan *dma_chan;
  518. u32 *dma_buf;
  519. dma_addr_t dma_phys;
  520. int ret;
  521. struct dma_slave_config dma_sconfig;
  522. dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx");
  523. if (IS_ERR(dma_chan))
  524. return dev_err_probe(tspi->dev, PTR_ERR(dma_chan),
  525. "Dma channel is not available\n");
  526. dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
  527. &dma_phys, GFP_KERNEL);
  528. if (!dma_buf) {
  529. dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
  530. dma_release_channel(dma_chan);
  531. return -ENOMEM;
  532. }
  533. if (dma_to_memory) {
  534. dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
  535. dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  536. dma_sconfig.src_maxburst = 0;
  537. } else {
  538. dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO;
  539. dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  540. dma_sconfig.dst_maxburst = 0;
  541. }
  542. ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
  543. if (ret)
  544. goto scrub;
  545. if (dma_to_memory) {
  546. tspi->rx_dma_chan = dma_chan;
  547. tspi->rx_dma_buf = dma_buf;
  548. tspi->rx_dma_phys = dma_phys;
  549. } else {
  550. tspi->tx_dma_chan = dma_chan;
  551. tspi->tx_dma_buf = dma_buf;
  552. tspi->tx_dma_phys = dma_phys;
  553. }
  554. return 0;
  555. scrub:
  556. dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
  557. dma_release_channel(dma_chan);
  558. return ret;
  559. }
  560. static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi,
  561. bool dma_to_memory)
  562. {
  563. u32 *dma_buf;
  564. dma_addr_t dma_phys;
  565. struct dma_chan *dma_chan;
  566. if (dma_to_memory) {
  567. dma_buf = tspi->rx_dma_buf;
  568. dma_chan = tspi->rx_dma_chan;
  569. dma_phys = tspi->rx_dma_phys;
  570. tspi->rx_dma_chan = NULL;
  571. tspi->rx_dma_buf = NULL;
  572. } else {
  573. dma_buf = tspi->tx_dma_buf;
  574. dma_chan = tspi->tx_dma_chan;
  575. dma_phys = tspi->tx_dma_phys;
  576. tspi->tx_dma_buf = NULL;
  577. tspi->tx_dma_chan = NULL;
  578. }
  579. if (!dma_chan)
  580. return;
  581. dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
  582. dma_release_channel(dma_chan);
  583. }
  584. static int tegra_slink_start_transfer_one(struct spi_device *spi,
  585. struct spi_transfer *t)
  586. {
  587. struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
  588. u32 speed;
  589. u8 bits_per_word;
  590. unsigned total_fifo_words;
  591. int ret;
  592. u32 command;
  593. u32 command2;
  594. bits_per_word = t->bits_per_word;
  595. speed = t->speed_hz;
  596. if (speed != tspi->cur_speed) {
  597. clk_set_rate(tspi->clk, speed * 4);
  598. tspi->cur_speed = speed;
  599. }
  600. tspi->cur_spi = spi;
  601. tspi->cur_pos = 0;
  602. tspi->cur_rx_pos = 0;
  603. tspi->cur_tx_pos = 0;
  604. tspi->curr_xfer = t;
  605. total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t);
  606. command = tspi->command_reg;
  607. command &= ~SLINK_BIT_LENGTH(~0);
  608. command |= SLINK_BIT_LENGTH(bits_per_word - 1);
  609. command2 = tspi->command2_reg;
  610. command2 &= ~(SLINK_RXEN | SLINK_TXEN);
  611. tspi->cur_direction = 0;
  612. if (t->rx_buf) {
  613. command2 |= SLINK_RXEN;
  614. tspi->cur_direction |= DATA_DIR_RX;
  615. }
  616. if (t->tx_buf) {
  617. command2 |= SLINK_TXEN;
  618. tspi->cur_direction |= DATA_DIR_TX;
  619. }
  620. /*
  621. * Writing to the command2 register bevore the command register prevents
  622. * a spike in chip_select line 0. This selects the chip_select line
  623. * before changing the chip_select value.
  624. */
  625. tegra_slink_writel(tspi, command2, SLINK_COMMAND2);
  626. tspi->command2_reg = command2;
  627. tegra_slink_writel(tspi, command, SLINK_COMMAND);
  628. tspi->command_reg = command;
  629. if (total_fifo_words > SLINK_FIFO_DEPTH)
  630. ret = tegra_slink_start_dma_based_transfer(tspi, t);
  631. else
  632. ret = tegra_slink_start_cpu_based_transfer(tspi, t);
  633. return ret;
  634. }
  635. static int tegra_slink_setup(struct spi_device *spi)
  636. {
  637. static const u32 cs_pol_bit[MAX_CHIP_SELECT] = {
  638. SLINK_CS_POLARITY,
  639. SLINK_CS_POLARITY1,
  640. SLINK_CS_POLARITY2,
  641. SLINK_CS_POLARITY3,
  642. };
  643. struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
  644. u32 val;
  645. unsigned long flags;
  646. int ret;
  647. dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
  648. spi->bits_per_word,
  649. spi->mode & SPI_CPOL ? "" : "~",
  650. spi->mode & SPI_CPHA ? "" : "~",
  651. spi->max_speed_hz);
  652. ret = pm_runtime_get_sync(tspi->dev);
  653. if (ret < 0) {
  654. pm_runtime_put_noidle(tspi->dev);
  655. dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
  656. return ret;
  657. }
  658. spin_lock_irqsave(&tspi->lock, flags);
  659. val = tspi->def_command_reg;
  660. if (spi->mode & SPI_CS_HIGH)
  661. val |= cs_pol_bit[spi->chip_select];
  662. else
  663. val &= ~cs_pol_bit[spi->chip_select];
  664. tspi->def_command_reg = val;
  665. tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
  666. spin_unlock_irqrestore(&tspi->lock, flags);
  667. pm_runtime_put(tspi->dev);
  668. return 0;
  669. }
  670. static int tegra_slink_prepare_message(struct spi_master *master,
  671. struct spi_message *msg)
  672. {
  673. struct tegra_slink_data *tspi = spi_master_get_devdata(master);
  674. struct spi_device *spi = msg->spi;
  675. tegra_slink_clear_status(tspi);
  676. tspi->command_reg = tspi->def_command_reg;
  677. tspi->command_reg |= SLINK_CS_SW | SLINK_CS_VALUE;
  678. tspi->command2_reg = tspi->def_command2_reg;
  679. tspi->command2_reg |= SLINK_SS_EN_CS(spi->chip_select);
  680. tspi->command_reg &= ~SLINK_MODES;
  681. if (spi->mode & SPI_CPHA)
  682. tspi->command_reg |= SLINK_CK_SDA;
  683. if (spi->mode & SPI_CPOL)
  684. tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_HIGH;
  685. else
  686. tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_LOW;
  687. return 0;
  688. }
  689. static int tegra_slink_transfer_one(struct spi_master *master,
  690. struct spi_device *spi,
  691. struct spi_transfer *xfer)
  692. {
  693. struct tegra_slink_data *tspi = spi_master_get_devdata(master);
  694. int ret;
  695. reinit_completion(&tspi->xfer_completion);
  696. ret = tegra_slink_start_transfer_one(spi, xfer);
  697. if (ret < 0) {
  698. dev_err(tspi->dev,
  699. "spi can not start transfer, err %d\n", ret);
  700. return ret;
  701. }
  702. ret = wait_for_completion_timeout(&tspi->xfer_completion,
  703. SLINK_DMA_TIMEOUT);
  704. if (WARN_ON(ret == 0)) {
  705. dev_err(tspi->dev,
  706. "spi transfer timeout, err %d\n", ret);
  707. return -EIO;
  708. }
  709. if (tspi->tx_status)
  710. return tspi->tx_status;
  711. if (tspi->rx_status)
  712. return tspi->rx_status;
  713. return 0;
  714. }
  715. static int tegra_slink_unprepare_message(struct spi_master *master,
  716. struct spi_message *msg)
  717. {
  718. struct tegra_slink_data *tspi = spi_master_get_devdata(master);
  719. tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
  720. tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
  721. return 0;
  722. }
  723. static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi)
  724. {
  725. struct spi_transfer *t = tspi->curr_xfer;
  726. unsigned long flags;
  727. spin_lock_irqsave(&tspi->lock, flags);
  728. if (tspi->tx_status || tspi->rx_status ||
  729. (tspi->status_reg & SLINK_BSY)) {
  730. dev_err(tspi->dev,
  731. "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg);
  732. dev_err(tspi->dev,
  733. "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
  734. tspi->command2_reg, tspi->dma_control_reg);
  735. reset_control_assert(tspi->rst);
  736. udelay(2);
  737. reset_control_deassert(tspi->rst);
  738. complete(&tspi->xfer_completion);
  739. goto exit;
  740. }
  741. if (tspi->cur_direction & DATA_DIR_RX)
  742. tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t);
  743. if (tspi->cur_direction & DATA_DIR_TX)
  744. tspi->cur_pos = tspi->cur_tx_pos;
  745. else
  746. tspi->cur_pos = tspi->cur_rx_pos;
  747. if (tspi->cur_pos == t->len) {
  748. complete(&tspi->xfer_completion);
  749. goto exit;
  750. }
  751. tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
  752. tegra_slink_start_cpu_based_transfer(tspi, t);
  753. exit:
  754. spin_unlock_irqrestore(&tspi->lock, flags);
  755. return IRQ_HANDLED;
  756. }
  757. static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi)
  758. {
  759. struct spi_transfer *t = tspi->curr_xfer;
  760. long wait_status;
  761. int err = 0;
  762. unsigned total_fifo_words;
  763. unsigned long flags;
  764. /* Abort dmas if any error */
  765. if (tspi->cur_direction & DATA_DIR_TX) {
  766. if (tspi->tx_status) {
  767. dmaengine_terminate_all(tspi->tx_dma_chan);
  768. err += 1;
  769. } else {
  770. wait_status = wait_for_completion_interruptible_timeout(
  771. &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT);
  772. if (wait_status <= 0) {
  773. dmaengine_terminate_all(tspi->tx_dma_chan);
  774. dev_err(tspi->dev, "TxDma Xfer failed\n");
  775. err += 1;
  776. }
  777. }
  778. }
  779. if (tspi->cur_direction & DATA_DIR_RX) {
  780. if (tspi->rx_status) {
  781. dmaengine_terminate_all(tspi->rx_dma_chan);
  782. err += 2;
  783. } else {
  784. wait_status = wait_for_completion_interruptible_timeout(
  785. &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT);
  786. if (wait_status <= 0) {
  787. dmaengine_terminate_all(tspi->rx_dma_chan);
  788. dev_err(tspi->dev, "RxDma Xfer failed\n");
  789. err += 2;
  790. }
  791. }
  792. }
  793. spin_lock_irqsave(&tspi->lock, flags);
  794. if (err) {
  795. dev_err(tspi->dev,
  796. "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg);
  797. dev_err(tspi->dev,
  798. "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
  799. tspi->command2_reg, tspi->dma_control_reg);
  800. reset_control_assert(tspi->rst);
  801. udelay(2);
  802. reset_control_assert(tspi->rst);
  803. complete(&tspi->xfer_completion);
  804. spin_unlock_irqrestore(&tspi->lock, flags);
  805. return IRQ_HANDLED;
  806. }
  807. if (tspi->cur_direction & DATA_DIR_RX)
  808. tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
  809. if (tspi->cur_direction & DATA_DIR_TX)
  810. tspi->cur_pos = tspi->cur_tx_pos;
  811. else
  812. tspi->cur_pos = tspi->cur_rx_pos;
  813. if (tspi->cur_pos == t->len) {
  814. complete(&tspi->xfer_completion);
  815. goto exit;
  816. }
  817. /* Continue transfer in current message */
  818. total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi,
  819. tspi, t);
  820. if (total_fifo_words > SLINK_FIFO_DEPTH)
  821. err = tegra_slink_start_dma_based_transfer(tspi, t);
  822. else
  823. err = tegra_slink_start_cpu_based_transfer(tspi, t);
  824. exit:
  825. spin_unlock_irqrestore(&tspi->lock, flags);
  826. return IRQ_HANDLED;
  827. }
  828. static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data)
  829. {
  830. struct tegra_slink_data *tspi = context_data;
  831. if (!tspi->is_curr_dma_xfer)
  832. return handle_cpu_based_xfer(tspi);
  833. return handle_dma_based_xfer(tspi);
  834. }
  835. static irqreturn_t tegra_slink_isr(int irq, void *context_data)
  836. {
  837. struct tegra_slink_data *tspi = context_data;
  838. tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS);
  839. if (tspi->cur_direction & DATA_DIR_TX)
  840. tspi->tx_status = tspi->status_reg &
  841. (SLINK_TX_OVF | SLINK_TX_UNF);
  842. if (tspi->cur_direction & DATA_DIR_RX)
  843. tspi->rx_status = tspi->status_reg &
  844. (SLINK_RX_OVF | SLINK_RX_UNF);
  845. tegra_slink_clear_status(tspi);
  846. return IRQ_WAKE_THREAD;
  847. }
  848. static const struct tegra_slink_chip_data tegra30_spi_cdata = {
  849. .cs_hold_time = true,
  850. };
  851. static const struct tegra_slink_chip_data tegra20_spi_cdata = {
  852. .cs_hold_time = false,
  853. };
  854. static const struct of_device_id tegra_slink_of_match[] = {
  855. { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, },
  856. { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, },
  857. {}
  858. };
  859. MODULE_DEVICE_TABLE(of, tegra_slink_of_match);
  860. static int tegra_slink_probe(struct platform_device *pdev)
  861. {
  862. struct spi_master *master;
  863. struct tegra_slink_data *tspi;
  864. struct resource *r;
  865. int ret, spi_irq;
  866. const struct tegra_slink_chip_data *cdata = NULL;
  867. cdata = of_device_get_match_data(&pdev->dev);
  868. master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
  869. if (!master) {
  870. dev_err(&pdev->dev, "master allocation failed\n");
  871. return -ENOMEM;
  872. }
  873. /* the spi->mode bits understood by this driver: */
  874. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
  875. master->setup = tegra_slink_setup;
  876. master->prepare_message = tegra_slink_prepare_message;
  877. master->transfer_one = tegra_slink_transfer_one;
  878. master->unprepare_message = tegra_slink_unprepare_message;
  879. master->auto_runtime_pm = true;
  880. master->num_chipselect = MAX_CHIP_SELECT;
  881. platform_set_drvdata(pdev, master);
  882. tspi = spi_master_get_devdata(master);
  883. tspi->master = master;
  884. tspi->dev = &pdev->dev;
  885. tspi->chip_data = cdata;
  886. spin_lock_init(&tspi->lock);
  887. if (of_property_read_u32(tspi->dev->of_node, "spi-max-frequency",
  888. &master->max_speed_hz))
  889. master->max_speed_hz = 25000000; /* 25MHz */
  890. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  891. if (!r) {
  892. dev_err(&pdev->dev, "No IO memory resource\n");
  893. ret = -ENODEV;
  894. goto exit_free_master;
  895. }
  896. tspi->phys = r->start;
  897. tspi->base = devm_ioremap_resource(&pdev->dev, r);
  898. if (IS_ERR(tspi->base)) {
  899. ret = PTR_ERR(tspi->base);
  900. goto exit_free_master;
  901. }
  902. /* disabled clock may cause interrupt storm upon request */
  903. tspi->clk = devm_clk_get(&pdev->dev, NULL);
  904. if (IS_ERR(tspi->clk)) {
  905. ret = PTR_ERR(tspi->clk);
  906. dev_err(&pdev->dev, "Can not get clock %d\n", ret);
  907. goto exit_free_master;
  908. }
  909. ret = clk_prepare(tspi->clk);
  910. if (ret < 0) {
  911. dev_err(&pdev->dev, "Clock prepare failed %d\n", ret);
  912. goto exit_free_master;
  913. }
  914. ret = clk_enable(tspi->clk);
  915. if (ret < 0) {
  916. dev_err(&pdev->dev, "Clock enable failed %d\n", ret);
  917. goto exit_clk_unprepare;
  918. }
  919. spi_irq = platform_get_irq(pdev, 0);
  920. tspi->irq = spi_irq;
  921. ret = request_threaded_irq(tspi->irq, tegra_slink_isr,
  922. tegra_slink_isr_thread, IRQF_ONESHOT,
  923. dev_name(&pdev->dev), tspi);
  924. if (ret < 0) {
  925. dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
  926. tspi->irq);
  927. goto exit_clk_disable;
  928. }
  929. tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
  930. if (IS_ERR(tspi->rst)) {
  931. dev_err(&pdev->dev, "can not get reset\n");
  932. ret = PTR_ERR(tspi->rst);
  933. goto exit_free_irq;
  934. }
  935. tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
  936. tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
  937. ret = tegra_slink_init_dma_param(tspi, true);
  938. if (ret < 0)
  939. goto exit_free_irq;
  940. ret = tegra_slink_init_dma_param(tspi, false);
  941. if (ret < 0)
  942. goto exit_rx_dma_free;
  943. tspi->max_buf_size = tspi->dma_buf_size;
  944. init_completion(&tspi->tx_dma_complete);
  945. init_completion(&tspi->rx_dma_complete);
  946. init_completion(&tspi->xfer_completion);
  947. pm_runtime_enable(&pdev->dev);
  948. if (!pm_runtime_enabled(&pdev->dev)) {
  949. ret = tegra_slink_runtime_resume(&pdev->dev);
  950. if (ret)
  951. goto exit_pm_disable;
  952. }
  953. ret = pm_runtime_get_sync(&pdev->dev);
  954. if (ret < 0) {
  955. dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
  956. pm_runtime_put_noidle(&pdev->dev);
  957. goto exit_pm_disable;
  958. }
  959. tspi->def_command_reg = SLINK_M_S;
  960. tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN;
  961. tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
  962. tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
  963. pm_runtime_put(&pdev->dev);
  964. master->dev.of_node = pdev->dev.of_node;
  965. ret = devm_spi_register_master(&pdev->dev, master);
  966. if (ret < 0) {
  967. dev_err(&pdev->dev, "can not register to master err %d\n", ret);
  968. goto exit_pm_disable;
  969. }
  970. return ret;
  971. exit_pm_disable:
  972. pm_runtime_disable(&pdev->dev);
  973. if (!pm_runtime_status_suspended(&pdev->dev))
  974. tegra_slink_runtime_suspend(&pdev->dev);
  975. tegra_slink_deinit_dma_param(tspi, false);
  976. exit_rx_dma_free:
  977. tegra_slink_deinit_dma_param(tspi, true);
  978. exit_free_irq:
  979. free_irq(spi_irq, tspi);
  980. exit_clk_disable:
  981. clk_disable(tspi->clk);
  982. exit_clk_unprepare:
  983. clk_unprepare(tspi->clk);
  984. exit_free_master:
  985. spi_master_put(master);
  986. return ret;
  987. }
  988. static int tegra_slink_remove(struct platform_device *pdev)
  989. {
  990. struct spi_master *master = platform_get_drvdata(pdev);
  991. struct tegra_slink_data *tspi = spi_master_get_devdata(master);
  992. free_irq(tspi->irq, tspi);
  993. clk_disable(tspi->clk);
  994. clk_unprepare(tspi->clk);
  995. if (tspi->tx_dma_chan)
  996. tegra_slink_deinit_dma_param(tspi, false);
  997. if (tspi->rx_dma_chan)
  998. tegra_slink_deinit_dma_param(tspi, true);
  999. pm_runtime_disable(&pdev->dev);
  1000. if (!pm_runtime_status_suspended(&pdev->dev))
  1001. tegra_slink_runtime_suspend(&pdev->dev);
  1002. return 0;
  1003. }
  1004. #ifdef CONFIG_PM_SLEEP
  1005. static int tegra_slink_suspend(struct device *dev)
  1006. {
  1007. struct spi_master *master = dev_get_drvdata(dev);
  1008. return spi_master_suspend(master);
  1009. }
  1010. static int tegra_slink_resume(struct device *dev)
  1011. {
  1012. struct spi_master *master = dev_get_drvdata(dev);
  1013. struct tegra_slink_data *tspi = spi_master_get_devdata(master);
  1014. int ret;
  1015. ret = pm_runtime_get_sync(dev);
  1016. if (ret < 0) {
  1017. pm_runtime_put_noidle(dev);
  1018. dev_err(dev, "pm runtime failed, e = %d\n", ret);
  1019. return ret;
  1020. }
  1021. tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND);
  1022. tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2);
  1023. pm_runtime_put(dev);
  1024. return spi_master_resume(master);
  1025. }
  1026. #endif
  1027. static int __maybe_unused tegra_slink_runtime_suspend(struct device *dev)
  1028. {
  1029. struct spi_master *master = dev_get_drvdata(dev);
  1030. struct tegra_slink_data *tspi = spi_master_get_devdata(master);
  1031. /* Flush all write which are in PPSB queue by reading back */
  1032. tegra_slink_readl(tspi, SLINK_MAS_DATA);
  1033. clk_disable_unprepare(tspi->clk);
  1034. return 0;
  1035. }
  1036. static int __maybe_unused tegra_slink_runtime_resume(struct device *dev)
  1037. {
  1038. struct spi_master *master = dev_get_drvdata(dev);
  1039. struct tegra_slink_data *tspi = spi_master_get_devdata(master);
  1040. int ret;
  1041. ret = clk_prepare_enable(tspi->clk);
  1042. if (ret < 0) {
  1043. dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
  1044. return ret;
  1045. }
  1046. return 0;
  1047. }
  1048. static const struct dev_pm_ops slink_pm_ops = {
  1049. SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend,
  1050. tegra_slink_runtime_resume, NULL)
  1051. SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume)
  1052. };
  1053. static struct platform_driver tegra_slink_driver = {
  1054. .driver = {
  1055. .name = "spi-tegra-slink",
  1056. .pm = &slink_pm_ops,
  1057. .of_match_table = tegra_slink_of_match,
  1058. },
  1059. .probe = tegra_slink_probe,
  1060. .remove = tegra_slink_remove,
  1061. };
  1062. module_platform_driver(tegra_slink_driver);
  1063. MODULE_ALIAS("platform:spi-tegra-slink");
  1064. MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver");
  1065. MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
  1066. MODULE_LICENSE("GPL v2");