spi-tegra20-sflash.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * SPI driver for Nvidia's Tegra20 Serial Flash Controller.
  4. *
  5. * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
  6. *
  7. * Author: Laxman Dewangan <ldewangan@nvidia.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/completion.h>
  11. #include <linux/delay.h>
  12. #include <linux/err.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/kernel.h>
  16. #include <linux/kthread.h>
  17. #include <linux/module.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/pm_runtime.h>
  20. #include <linux/of.h>
  21. #include <linux/of_device.h>
  22. #include <linux/reset.h>
  23. #include <linux/spi/spi.h>
  24. #define SPI_COMMAND 0x000
  25. #define SPI_GO BIT(30)
  26. #define SPI_M_S BIT(28)
  27. #define SPI_ACTIVE_SCLK_MASK (0x3 << 26)
  28. #define SPI_ACTIVE_SCLK_DRIVE_LOW (0 << 26)
  29. #define SPI_ACTIVE_SCLK_DRIVE_HIGH (1 << 26)
  30. #define SPI_ACTIVE_SCLK_PULL_LOW (2 << 26)
  31. #define SPI_ACTIVE_SCLK_PULL_HIGH (3 << 26)
  32. #define SPI_CK_SDA_FALLING (1 << 21)
  33. #define SPI_CK_SDA_RISING (0 << 21)
  34. #define SPI_CK_SDA_MASK (1 << 21)
  35. #define SPI_ACTIVE_SDA (0x3 << 18)
  36. #define SPI_ACTIVE_SDA_DRIVE_LOW (0 << 18)
  37. #define SPI_ACTIVE_SDA_DRIVE_HIGH (1 << 18)
  38. #define SPI_ACTIVE_SDA_PULL_LOW (2 << 18)
  39. #define SPI_ACTIVE_SDA_PULL_HIGH (3 << 18)
  40. #define SPI_CS_POL_INVERT BIT(16)
  41. #define SPI_TX_EN BIT(15)
  42. #define SPI_RX_EN BIT(14)
  43. #define SPI_CS_VAL_HIGH BIT(13)
  44. #define SPI_CS_VAL_LOW 0x0
  45. #define SPI_CS_SW BIT(12)
  46. #define SPI_CS_HW 0x0
  47. #define SPI_CS_DELAY_MASK (7 << 9)
  48. #define SPI_CS3_EN BIT(8)
  49. #define SPI_CS2_EN BIT(7)
  50. #define SPI_CS1_EN BIT(6)
  51. #define SPI_CS0_EN BIT(5)
  52. #define SPI_CS_MASK (SPI_CS3_EN | SPI_CS2_EN | \
  53. SPI_CS1_EN | SPI_CS0_EN)
  54. #define SPI_BIT_LENGTH(x) (((x) & 0x1f) << 0)
  55. #define SPI_MODES (SPI_ACTIVE_SCLK_MASK | SPI_CK_SDA_MASK)
  56. #define SPI_STATUS 0x004
  57. #define SPI_BSY BIT(31)
  58. #define SPI_RDY BIT(30)
  59. #define SPI_TXF_FLUSH BIT(29)
  60. #define SPI_RXF_FLUSH BIT(28)
  61. #define SPI_RX_UNF BIT(27)
  62. #define SPI_TX_OVF BIT(26)
  63. #define SPI_RXF_EMPTY BIT(25)
  64. #define SPI_RXF_FULL BIT(24)
  65. #define SPI_TXF_EMPTY BIT(23)
  66. #define SPI_TXF_FULL BIT(22)
  67. #define SPI_BLK_CNT(count) (((count) & 0xffff) + 1)
  68. #define SPI_FIFO_ERROR (SPI_RX_UNF | SPI_TX_OVF)
  69. #define SPI_FIFO_EMPTY (SPI_TX_EMPTY | SPI_RX_EMPTY)
  70. #define SPI_RX_CMP 0x8
  71. #define SPI_DMA_CTL 0x0C
  72. #define SPI_DMA_EN BIT(31)
  73. #define SPI_IE_RXC BIT(27)
  74. #define SPI_IE_TXC BIT(26)
  75. #define SPI_PACKED BIT(20)
  76. #define SPI_RX_TRIG_MASK (0x3 << 18)
  77. #define SPI_RX_TRIG_1W (0x0 << 18)
  78. #define SPI_RX_TRIG_4W (0x1 << 18)
  79. #define SPI_TX_TRIG_MASK (0x3 << 16)
  80. #define SPI_TX_TRIG_1W (0x0 << 16)
  81. #define SPI_TX_TRIG_4W (0x1 << 16)
  82. #define SPI_DMA_BLK_COUNT(count) (((count) - 1) & 0xFFFF)
  83. #define SPI_TX_FIFO 0x10
  84. #define SPI_RX_FIFO 0x20
  85. #define DATA_DIR_TX (1 << 0)
  86. #define DATA_DIR_RX (1 << 1)
  87. #define MAX_CHIP_SELECT 4
  88. #define SPI_FIFO_DEPTH 4
  89. #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
  90. struct tegra_sflash_data {
  91. struct device *dev;
  92. struct spi_master *master;
  93. spinlock_t lock;
  94. struct clk *clk;
  95. struct reset_control *rst;
  96. void __iomem *base;
  97. unsigned irq;
  98. u32 cur_speed;
  99. struct spi_device *cur_spi;
  100. unsigned cur_pos;
  101. unsigned cur_len;
  102. unsigned bytes_per_word;
  103. unsigned cur_direction;
  104. unsigned curr_xfer_words;
  105. unsigned cur_rx_pos;
  106. unsigned cur_tx_pos;
  107. u32 tx_status;
  108. u32 rx_status;
  109. u32 status_reg;
  110. u32 def_command_reg;
  111. u32 command_reg;
  112. u32 dma_control_reg;
  113. struct completion xfer_completion;
  114. struct spi_transfer *curr_xfer;
  115. };
  116. static int tegra_sflash_runtime_suspend(struct device *dev);
  117. static int tegra_sflash_runtime_resume(struct device *dev);
  118. static inline u32 tegra_sflash_readl(struct tegra_sflash_data *tsd,
  119. unsigned long reg)
  120. {
  121. return readl(tsd->base + reg);
  122. }
  123. static inline void tegra_sflash_writel(struct tegra_sflash_data *tsd,
  124. u32 val, unsigned long reg)
  125. {
  126. writel(val, tsd->base + reg);
  127. }
  128. static void tegra_sflash_clear_status(struct tegra_sflash_data *tsd)
  129. {
  130. /* Write 1 to clear status register */
  131. tegra_sflash_writel(tsd, SPI_RDY | SPI_FIFO_ERROR, SPI_STATUS);
  132. }
  133. static unsigned tegra_sflash_calculate_curr_xfer_param(
  134. struct spi_device *spi, struct tegra_sflash_data *tsd,
  135. struct spi_transfer *t)
  136. {
  137. unsigned remain_len = t->len - tsd->cur_pos;
  138. unsigned max_word;
  139. tsd->bytes_per_word = DIV_ROUND_UP(t->bits_per_word, 8);
  140. max_word = remain_len / tsd->bytes_per_word;
  141. if (max_word > SPI_FIFO_DEPTH)
  142. max_word = SPI_FIFO_DEPTH;
  143. tsd->curr_xfer_words = max_word;
  144. return max_word;
  145. }
  146. static unsigned tegra_sflash_fill_tx_fifo_from_client_txbuf(
  147. struct tegra_sflash_data *tsd, struct spi_transfer *t)
  148. {
  149. unsigned nbytes;
  150. u32 status;
  151. unsigned max_n_32bit = tsd->curr_xfer_words;
  152. u8 *tx_buf = (u8 *)t->tx_buf + tsd->cur_tx_pos;
  153. if (max_n_32bit > SPI_FIFO_DEPTH)
  154. max_n_32bit = SPI_FIFO_DEPTH;
  155. nbytes = max_n_32bit * tsd->bytes_per_word;
  156. status = tegra_sflash_readl(tsd, SPI_STATUS);
  157. while (!(status & SPI_TXF_FULL)) {
  158. int i;
  159. u32 x = 0;
  160. for (i = 0; nbytes && (i < tsd->bytes_per_word);
  161. i++, nbytes--)
  162. x |= (u32)(*tx_buf++) << (i * 8);
  163. tegra_sflash_writel(tsd, x, SPI_TX_FIFO);
  164. if (!nbytes)
  165. break;
  166. status = tegra_sflash_readl(tsd, SPI_STATUS);
  167. }
  168. tsd->cur_tx_pos += max_n_32bit * tsd->bytes_per_word;
  169. return max_n_32bit;
  170. }
  171. static int tegra_sflash_read_rx_fifo_to_client_rxbuf(
  172. struct tegra_sflash_data *tsd, struct spi_transfer *t)
  173. {
  174. u32 status;
  175. unsigned int read_words = 0;
  176. u8 *rx_buf = (u8 *)t->rx_buf + tsd->cur_rx_pos;
  177. status = tegra_sflash_readl(tsd, SPI_STATUS);
  178. while (!(status & SPI_RXF_EMPTY)) {
  179. int i;
  180. u32 x = tegra_sflash_readl(tsd, SPI_RX_FIFO);
  181. for (i = 0; (i < tsd->bytes_per_word); i++)
  182. *rx_buf++ = (x >> (i*8)) & 0xFF;
  183. read_words++;
  184. status = tegra_sflash_readl(tsd, SPI_STATUS);
  185. }
  186. tsd->cur_rx_pos += read_words * tsd->bytes_per_word;
  187. return 0;
  188. }
  189. static int tegra_sflash_start_cpu_based_transfer(
  190. struct tegra_sflash_data *tsd, struct spi_transfer *t)
  191. {
  192. u32 val = 0;
  193. unsigned cur_words;
  194. if (tsd->cur_direction & DATA_DIR_TX)
  195. val |= SPI_IE_TXC;
  196. if (tsd->cur_direction & DATA_DIR_RX)
  197. val |= SPI_IE_RXC;
  198. tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
  199. tsd->dma_control_reg = val;
  200. if (tsd->cur_direction & DATA_DIR_TX)
  201. cur_words = tegra_sflash_fill_tx_fifo_from_client_txbuf(tsd, t);
  202. else
  203. cur_words = tsd->curr_xfer_words;
  204. val |= SPI_DMA_BLK_COUNT(cur_words);
  205. tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
  206. tsd->dma_control_reg = val;
  207. val |= SPI_DMA_EN;
  208. tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
  209. return 0;
  210. }
  211. static int tegra_sflash_start_transfer_one(struct spi_device *spi,
  212. struct spi_transfer *t, bool is_first_of_msg,
  213. bool is_single_xfer)
  214. {
  215. struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master);
  216. u32 speed;
  217. u32 command;
  218. speed = t->speed_hz;
  219. if (speed != tsd->cur_speed) {
  220. clk_set_rate(tsd->clk, speed);
  221. tsd->cur_speed = speed;
  222. }
  223. tsd->cur_spi = spi;
  224. tsd->cur_pos = 0;
  225. tsd->cur_rx_pos = 0;
  226. tsd->cur_tx_pos = 0;
  227. tsd->curr_xfer = t;
  228. tegra_sflash_calculate_curr_xfer_param(spi, tsd, t);
  229. if (is_first_of_msg) {
  230. command = tsd->def_command_reg;
  231. command |= SPI_BIT_LENGTH(t->bits_per_word - 1);
  232. command |= SPI_CS_VAL_HIGH;
  233. command &= ~SPI_MODES;
  234. if (spi->mode & SPI_CPHA)
  235. command |= SPI_CK_SDA_FALLING;
  236. if (spi->mode & SPI_CPOL)
  237. command |= SPI_ACTIVE_SCLK_DRIVE_HIGH;
  238. else
  239. command |= SPI_ACTIVE_SCLK_DRIVE_LOW;
  240. command |= SPI_CS0_EN << spi->chip_select;
  241. } else {
  242. command = tsd->command_reg;
  243. command &= ~SPI_BIT_LENGTH(~0);
  244. command |= SPI_BIT_LENGTH(t->bits_per_word - 1);
  245. command &= ~(SPI_RX_EN | SPI_TX_EN);
  246. }
  247. tsd->cur_direction = 0;
  248. if (t->rx_buf) {
  249. command |= SPI_RX_EN;
  250. tsd->cur_direction |= DATA_DIR_RX;
  251. }
  252. if (t->tx_buf) {
  253. command |= SPI_TX_EN;
  254. tsd->cur_direction |= DATA_DIR_TX;
  255. }
  256. tegra_sflash_writel(tsd, command, SPI_COMMAND);
  257. tsd->command_reg = command;
  258. return tegra_sflash_start_cpu_based_transfer(tsd, t);
  259. }
  260. static int tegra_sflash_transfer_one_message(struct spi_master *master,
  261. struct spi_message *msg)
  262. {
  263. bool is_first_msg = true;
  264. int single_xfer;
  265. struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
  266. struct spi_transfer *xfer;
  267. struct spi_device *spi = msg->spi;
  268. int ret;
  269. msg->status = 0;
  270. msg->actual_length = 0;
  271. single_xfer = list_is_singular(&msg->transfers);
  272. list_for_each_entry(xfer, &msg->transfers, transfer_list) {
  273. reinit_completion(&tsd->xfer_completion);
  274. ret = tegra_sflash_start_transfer_one(spi, xfer,
  275. is_first_msg, single_xfer);
  276. if (ret < 0) {
  277. dev_err(tsd->dev,
  278. "spi can not start transfer, err %d\n", ret);
  279. goto exit;
  280. }
  281. is_first_msg = false;
  282. ret = wait_for_completion_timeout(&tsd->xfer_completion,
  283. SPI_DMA_TIMEOUT);
  284. if (WARN_ON(ret == 0)) {
  285. dev_err(tsd->dev,
  286. "spi transfer timeout, err %d\n", ret);
  287. ret = -EIO;
  288. goto exit;
  289. }
  290. if (tsd->tx_status || tsd->rx_status) {
  291. dev_err(tsd->dev, "Error in Transfer\n");
  292. ret = -EIO;
  293. goto exit;
  294. }
  295. msg->actual_length += xfer->len;
  296. if (xfer->cs_change &&
  297. (xfer->delay_usecs || xfer->delay.value)) {
  298. tegra_sflash_writel(tsd, tsd->def_command_reg,
  299. SPI_COMMAND);
  300. spi_transfer_delay_exec(xfer);
  301. }
  302. }
  303. ret = 0;
  304. exit:
  305. tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
  306. msg->status = ret;
  307. spi_finalize_current_message(master);
  308. return ret;
  309. }
  310. static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd)
  311. {
  312. struct spi_transfer *t = tsd->curr_xfer;
  313. spin_lock(&tsd->lock);
  314. if (tsd->tx_status || tsd->rx_status || (tsd->status_reg & SPI_BSY)) {
  315. dev_err(tsd->dev,
  316. "CpuXfer ERROR bit set 0x%x\n", tsd->status_reg);
  317. dev_err(tsd->dev,
  318. "CpuXfer 0x%08x:0x%08x\n", tsd->command_reg,
  319. tsd->dma_control_reg);
  320. reset_control_assert(tsd->rst);
  321. udelay(2);
  322. reset_control_deassert(tsd->rst);
  323. complete(&tsd->xfer_completion);
  324. goto exit;
  325. }
  326. if (tsd->cur_direction & DATA_DIR_RX)
  327. tegra_sflash_read_rx_fifo_to_client_rxbuf(tsd, t);
  328. if (tsd->cur_direction & DATA_DIR_TX)
  329. tsd->cur_pos = tsd->cur_tx_pos;
  330. else
  331. tsd->cur_pos = tsd->cur_rx_pos;
  332. if (tsd->cur_pos == t->len) {
  333. complete(&tsd->xfer_completion);
  334. goto exit;
  335. }
  336. tegra_sflash_calculate_curr_xfer_param(tsd->cur_spi, tsd, t);
  337. tegra_sflash_start_cpu_based_transfer(tsd, t);
  338. exit:
  339. spin_unlock(&tsd->lock);
  340. return IRQ_HANDLED;
  341. }
  342. static irqreturn_t tegra_sflash_isr(int irq, void *context_data)
  343. {
  344. struct tegra_sflash_data *tsd = context_data;
  345. tsd->status_reg = tegra_sflash_readl(tsd, SPI_STATUS);
  346. if (tsd->cur_direction & DATA_DIR_TX)
  347. tsd->tx_status = tsd->status_reg & SPI_TX_OVF;
  348. if (tsd->cur_direction & DATA_DIR_RX)
  349. tsd->rx_status = tsd->status_reg & SPI_RX_UNF;
  350. tegra_sflash_clear_status(tsd);
  351. return handle_cpu_based_xfer(tsd);
  352. }
  353. static const struct of_device_id tegra_sflash_of_match[] = {
  354. { .compatible = "nvidia,tegra20-sflash", },
  355. {}
  356. };
  357. MODULE_DEVICE_TABLE(of, tegra_sflash_of_match);
  358. static int tegra_sflash_probe(struct platform_device *pdev)
  359. {
  360. struct spi_master *master;
  361. struct tegra_sflash_data *tsd;
  362. int ret;
  363. const struct of_device_id *match;
  364. match = of_match_device(tegra_sflash_of_match, &pdev->dev);
  365. if (!match) {
  366. dev_err(&pdev->dev, "Error: No device match found\n");
  367. return -ENODEV;
  368. }
  369. master = spi_alloc_master(&pdev->dev, sizeof(*tsd));
  370. if (!master) {
  371. dev_err(&pdev->dev, "master allocation failed\n");
  372. return -ENOMEM;
  373. }
  374. /* the spi->mode bits understood by this driver: */
  375. master->mode_bits = SPI_CPOL | SPI_CPHA;
  376. master->transfer_one_message = tegra_sflash_transfer_one_message;
  377. master->auto_runtime_pm = true;
  378. master->num_chipselect = MAX_CHIP_SELECT;
  379. platform_set_drvdata(pdev, master);
  380. tsd = spi_master_get_devdata(master);
  381. tsd->master = master;
  382. tsd->dev = &pdev->dev;
  383. spin_lock_init(&tsd->lock);
  384. if (of_property_read_u32(tsd->dev->of_node, "spi-max-frequency",
  385. &master->max_speed_hz))
  386. master->max_speed_hz = 25000000; /* 25MHz */
  387. tsd->base = devm_platform_ioremap_resource(pdev, 0);
  388. if (IS_ERR(tsd->base)) {
  389. ret = PTR_ERR(tsd->base);
  390. goto exit_free_master;
  391. }
  392. tsd->irq = platform_get_irq(pdev, 0);
  393. ret = request_irq(tsd->irq, tegra_sflash_isr, 0,
  394. dev_name(&pdev->dev), tsd);
  395. if (ret < 0) {
  396. dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
  397. tsd->irq);
  398. goto exit_free_master;
  399. }
  400. tsd->clk = devm_clk_get(&pdev->dev, NULL);
  401. if (IS_ERR(tsd->clk)) {
  402. dev_err(&pdev->dev, "can not get clock\n");
  403. ret = PTR_ERR(tsd->clk);
  404. goto exit_free_irq;
  405. }
  406. tsd->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
  407. if (IS_ERR(tsd->rst)) {
  408. dev_err(&pdev->dev, "can not get reset\n");
  409. ret = PTR_ERR(tsd->rst);
  410. goto exit_free_irq;
  411. }
  412. init_completion(&tsd->xfer_completion);
  413. pm_runtime_enable(&pdev->dev);
  414. if (!pm_runtime_enabled(&pdev->dev)) {
  415. ret = tegra_sflash_runtime_resume(&pdev->dev);
  416. if (ret)
  417. goto exit_pm_disable;
  418. }
  419. ret = pm_runtime_get_sync(&pdev->dev);
  420. if (ret < 0) {
  421. dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
  422. pm_runtime_put_noidle(&pdev->dev);
  423. goto exit_pm_disable;
  424. }
  425. /* Reset controller */
  426. reset_control_assert(tsd->rst);
  427. udelay(2);
  428. reset_control_deassert(tsd->rst);
  429. tsd->def_command_reg = SPI_M_S | SPI_CS_SW;
  430. tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
  431. pm_runtime_put(&pdev->dev);
  432. master->dev.of_node = pdev->dev.of_node;
  433. ret = devm_spi_register_master(&pdev->dev, master);
  434. if (ret < 0) {
  435. dev_err(&pdev->dev, "can not register to master err %d\n", ret);
  436. goto exit_pm_disable;
  437. }
  438. return ret;
  439. exit_pm_disable:
  440. pm_runtime_disable(&pdev->dev);
  441. if (!pm_runtime_status_suspended(&pdev->dev))
  442. tegra_sflash_runtime_suspend(&pdev->dev);
  443. exit_free_irq:
  444. free_irq(tsd->irq, tsd);
  445. exit_free_master:
  446. spi_master_put(master);
  447. return ret;
  448. }
  449. static int tegra_sflash_remove(struct platform_device *pdev)
  450. {
  451. struct spi_master *master = platform_get_drvdata(pdev);
  452. struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
  453. free_irq(tsd->irq, tsd);
  454. pm_runtime_disable(&pdev->dev);
  455. if (!pm_runtime_status_suspended(&pdev->dev))
  456. tegra_sflash_runtime_suspend(&pdev->dev);
  457. return 0;
  458. }
  459. #ifdef CONFIG_PM_SLEEP
  460. static int tegra_sflash_suspend(struct device *dev)
  461. {
  462. struct spi_master *master = dev_get_drvdata(dev);
  463. return spi_master_suspend(master);
  464. }
  465. static int tegra_sflash_resume(struct device *dev)
  466. {
  467. struct spi_master *master = dev_get_drvdata(dev);
  468. struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
  469. int ret;
  470. ret = pm_runtime_get_sync(dev);
  471. if (ret < 0) {
  472. pm_runtime_put_noidle(dev);
  473. dev_err(dev, "pm runtime failed, e = %d\n", ret);
  474. return ret;
  475. }
  476. tegra_sflash_writel(tsd, tsd->command_reg, SPI_COMMAND);
  477. pm_runtime_put(dev);
  478. return spi_master_resume(master);
  479. }
  480. #endif
  481. static int tegra_sflash_runtime_suspend(struct device *dev)
  482. {
  483. struct spi_master *master = dev_get_drvdata(dev);
  484. struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
  485. /* Flush all write which are in PPSB queue by reading back */
  486. tegra_sflash_readl(tsd, SPI_COMMAND);
  487. clk_disable_unprepare(tsd->clk);
  488. return 0;
  489. }
  490. static int tegra_sflash_runtime_resume(struct device *dev)
  491. {
  492. struct spi_master *master = dev_get_drvdata(dev);
  493. struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
  494. int ret;
  495. ret = clk_prepare_enable(tsd->clk);
  496. if (ret < 0) {
  497. dev_err(tsd->dev, "clk_prepare failed: %d\n", ret);
  498. return ret;
  499. }
  500. return 0;
  501. }
  502. static const struct dev_pm_ops slink_pm_ops = {
  503. SET_RUNTIME_PM_OPS(tegra_sflash_runtime_suspend,
  504. tegra_sflash_runtime_resume, NULL)
  505. SET_SYSTEM_SLEEP_PM_OPS(tegra_sflash_suspend, tegra_sflash_resume)
  506. };
  507. static struct platform_driver tegra_sflash_driver = {
  508. .driver = {
  509. .name = "spi-tegra-sflash",
  510. .pm = &slink_pm_ops,
  511. .of_match_table = tegra_sflash_of_match,
  512. },
  513. .probe = tegra_sflash_probe,
  514. .remove = tegra_sflash_remove,
  515. };
  516. module_platform_driver(tegra_sflash_driver);
  517. MODULE_ALIAS("platform:spi-tegra-sflash");
  518. MODULE_DESCRIPTION("NVIDIA Tegra20 Serial Flash Controller Driver");
  519. MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
  520. MODULE_LICENSE("GPL v2");