spi-tegra114.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * SPI driver for NVIDIA's Tegra114 SPI Controller.
  4. *
  5. * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/completion.h>
  9. #include <linux/delay.h>
  10. #include <linux/dmaengine.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/dmapool.h>
  13. #include <linux/err.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/kernel.h>
  17. #include <linux/kthread.h>
  18. #include <linux/module.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/of.h>
  22. #include <linux/of_device.h>
  23. #include <linux/reset.h>
  24. #include <linux/spi/spi.h>
  25. #define SPI_COMMAND1 0x000
  26. #define SPI_BIT_LENGTH(x) (((x) & 0x1f) << 0)
  27. #define SPI_PACKED (1 << 5)
  28. #define SPI_TX_EN (1 << 11)
  29. #define SPI_RX_EN (1 << 12)
  30. #define SPI_BOTH_EN_BYTE (1 << 13)
  31. #define SPI_BOTH_EN_BIT (1 << 14)
  32. #define SPI_LSBYTE_FE (1 << 15)
  33. #define SPI_LSBIT_FE (1 << 16)
  34. #define SPI_BIDIROE (1 << 17)
  35. #define SPI_IDLE_SDA_DRIVE_LOW (0 << 18)
  36. #define SPI_IDLE_SDA_DRIVE_HIGH (1 << 18)
  37. #define SPI_IDLE_SDA_PULL_LOW (2 << 18)
  38. #define SPI_IDLE_SDA_PULL_HIGH (3 << 18)
  39. #define SPI_IDLE_SDA_MASK (3 << 18)
  40. #define SPI_CS_SW_VAL (1 << 20)
  41. #define SPI_CS_SW_HW (1 << 21)
  42. /* SPI_CS_POL_INACTIVE bits are default high */
  43. /* n from 0 to 3 */
  44. #define SPI_CS_POL_INACTIVE(n) (1 << (22 + (n)))
  45. #define SPI_CS_POL_INACTIVE_MASK (0xF << 22)
  46. #define SPI_CS_SEL_0 (0 << 26)
  47. #define SPI_CS_SEL_1 (1 << 26)
  48. #define SPI_CS_SEL_2 (2 << 26)
  49. #define SPI_CS_SEL_3 (3 << 26)
  50. #define SPI_CS_SEL_MASK (3 << 26)
  51. #define SPI_CS_SEL(x) (((x) & 0x3) << 26)
  52. #define SPI_CONTROL_MODE_0 (0 << 28)
  53. #define SPI_CONTROL_MODE_1 (1 << 28)
  54. #define SPI_CONTROL_MODE_2 (2 << 28)
  55. #define SPI_CONTROL_MODE_3 (3 << 28)
  56. #define SPI_CONTROL_MODE_MASK (3 << 28)
  57. #define SPI_MODE_SEL(x) (((x) & 0x3) << 28)
  58. #define SPI_M_S (1 << 30)
  59. #define SPI_PIO (1 << 31)
  60. #define SPI_COMMAND2 0x004
  61. #define SPI_TX_TAP_DELAY(x) (((x) & 0x3F) << 6)
  62. #define SPI_RX_TAP_DELAY(x) (((x) & 0x3F) << 0)
  63. #define SPI_CS_TIMING1 0x008
  64. #define SPI_SETUP_HOLD(setup, hold) (((setup) << 4) | (hold))
  65. #define SPI_CS_SETUP_HOLD(reg, cs, val) \
  66. ((((val) & 0xFFu) << ((cs) * 8)) | \
  67. ((reg) & ~(0xFFu << ((cs) * 8))))
  68. #define SPI_CS_TIMING2 0x00C
  69. #define CYCLES_BETWEEN_PACKETS_0(x) (((x) & 0x1F) << 0)
  70. #define CS_ACTIVE_BETWEEN_PACKETS_0 (1 << 5)
  71. #define CYCLES_BETWEEN_PACKETS_1(x) (((x) & 0x1F) << 8)
  72. #define CS_ACTIVE_BETWEEN_PACKETS_1 (1 << 13)
  73. #define CYCLES_BETWEEN_PACKETS_2(x) (((x) & 0x1F) << 16)
  74. #define CS_ACTIVE_BETWEEN_PACKETS_2 (1 << 21)
  75. #define CYCLES_BETWEEN_PACKETS_3(x) (((x) & 0x1F) << 24)
  76. #define CS_ACTIVE_BETWEEN_PACKETS_3 (1 << 29)
  77. #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val) \
  78. (reg = (((val) & 0x1) << ((cs) * 8 + 5)) | \
  79. ((reg) & ~(1 << ((cs) * 8 + 5))))
  80. #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val) \
  81. (reg = (((val) & 0x1F) << ((cs) * 8)) | \
  82. ((reg) & ~(0x1F << ((cs) * 8))))
  83. #define MAX_SETUP_HOLD_CYCLES 16
  84. #define MAX_INACTIVE_CYCLES 32
  85. #define SPI_TRANS_STATUS 0x010
  86. #define SPI_BLK_CNT(val) (((val) >> 0) & 0xFFFF)
  87. #define SPI_SLV_IDLE_COUNT(val) (((val) >> 16) & 0xFF)
  88. #define SPI_RDY (1 << 30)
  89. #define SPI_FIFO_STATUS 0x014
  90. #define SPI_RX_FIFO_EMPTY (1 << 0)
  91. #define SPI_RX_FIFO_FULL (1 << 1)
  92. #define SPI_TX_FIFO_EMPTY (1 << 2)
  93. #define SPI_TX_FIFO_FULL (1 << 3)
  94. #define SPI_RX_FIFO_UNF (1 << 4)
  95. #define SPI_RX_FIFO_OVF (1 << 5)
  96. #define SPI_TX_FIFO_UNF (1 << 6)
  97. #define SPI_TX_FIFO_OVF (1 << 7)
  98. #define SPI_ERR (1 << 8)
  99. #define SPI_TX_FIFO_FLUSH (1 << 14)
  100. #define SPI_RX_FIFO_FLUSH (1 << 15)
  101. #define SPI_TX_FIFO_EMPTY_COUNT(val) (((val) >> 16) & 0x7F)
  102. #define SPI_RX_FIFO_FULL_COUNT(val) (((val) >> 23) & 0x7F)
  103. #define SPI_FRAME_END (1 << 30)
  104. #define SPI_CS_INACTIVE (1 << 31)
  105. #define SPI_FIFO_ERROR (SPI_RX_FIFO_UNF | \
  106. SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF)
  107. #define SPI_FIFO_EMPTY (SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY)
  108. #define SPI_TX_DATA 0x018
  109. #define SPI_RX_DATA 0x01C
  110. #define SPI_DMA_CTL 0x020
  111. #define SPI_TX_TRIG_1 (0 << 15)
  112. #define SPI_TX_TRIG_4 (1 << 15)
  113. #define SPI_TX_TRIG_8 (2 << 15)
  114. #define SPI_TX_TRIG_16 (3 << 15)
  115. #define SPI_TX_TRIG_MASK (3 << 15)
  116. #define SPI_RX_TRIG_1 (0 << 19)
  117. #define SPI_RX_TRIG_4 (1 << 19)
  118. #define SPI_RX_TRIG_8 (2 << 19)
  119. #define SPI_RX_TRIG_16 (3 << 19)
  120. #define SPI_RX_TRIG_MASK (3 << 19)
  121. #define SPI_IE_TX (1 << 28)
  122. #define SPI_IE_RX (1 << 29)
  123. #define SPI_CONT (1 << 30)
  124. #define SPI_DMA (1 << 31)
  125. #define SPI_DMA_EN SPI_DMA
  126. #define SPI_DMA_BLK 0x024
  127. #define SPI_DMA_BLK_SET(x) (((x) & 0xFFFF) << 0)
  128. #define SPI_TX_FIFO 0x108
  129. #define SPI_RX_FIFO 0x188
  130. #define SPI_INTR_MASK 0x18c
  131. #define SPI_INTR_ALL_MASK (0x1fUL << 25)
  132. #define MAX_CHIP_SELECT 4
  133. #define SPI_FIFO_DEPTH 64
  134. #define DATA_DIR_TX (1 << 0)
  135. #define DATA_DIR_RX (1 << 1)
  136. #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
  137. #define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
  138. #define TX_FIFO_EMPTY_COUNT_MAX SPI_TX_FIFO_EMPTY_COUNT(0x40)
  139. #define RX_FIFO_FULL_COUNT_ZERO SPI_RX_FIFO_FULL_COUNT(0)
  140. #define MAX_HOLD_CYCLES 16
  141. #define SPI_DEFAULT_SPEED 25000000
  142. struct tegra_spi_soc_data {
  143. bool has_intr_mask_reg;
  144. };
  145. struct tegra_spi_client_data {
  146. int tx_clk_tap_delay;
  147. int rx_clk_tap_delay;
  148. };
  149. struct tegra_spi_data {
  150. struct device *dev;
  151. struct spi_master *master;
  152. spinlock_t lock;
  153. struct clk *clk;
  154. struct reset_control *rst;
  155. void __iomem *base;
  156. phys_addr_t phys;
  157. unsigned irq;
  158. u32 cur_speed;
  159. struct spi_device *cur_spi;
  160. struct spi_device *cs_control;
  161. unsigned cur_pos;
  162. unsigned words_per_32bit;
  163. unsigned bytes_per_word;
  164. unsigned curr_dma_words;
  165. unsigned cur_direction;
  166. unsigned cur_rx_pos;
  167. unsigned cur_tx_pos;
  168. unsigned dma_buf_size;
  169. unsigned max_buf_size;
  170. bool is_curr_dma_xfer;
  171. bool use_hw_based_cs;
  172. struct completion rx_dma_complete;
  173. struct completion tx_dma_complete;
  174. u32 tx_status;
  175. u32 rx_status;
  176. u32 status_reg;
  177. bool is_packed;
  178. u32 command1_reg;
  179. u32 dma_control_reg;
  180. u32 def_command1_reg;
  181. u32 def_command2_reg;
  182. u32 spi_cs_timing1;
  183. u32 spi_cs_timing2;
  184. u8 last_used_cs;
  185. struct completion xfer_completion;
  186. struct spi_transfer *curr_xfer;
  187. struct dma_chan *rx_dma_chan;
  188. u32 *rx_dma_buf;
  189. dma_addr_t rx_dma_phys;
  190. struct dma_async_tx_descriptor *rx_dma_desc;
  191. struct dma_chan *tx_dma_chan;
  192. u32 *tx_dma_buf;
  193. dma_addr_t tx_dma_phys;
  194. struct dma_async_tx_descriptor *tx_dma_desc;
  195. const struct tegra_spi_soc_data *soc_data;
  196. };
  197. static int tegra_spi_runtime_suspend(struct device *dev);
  198. static int tegra_spi_runtime_resume(struct device *dev);
  199. static inline u32 tegra_spi_readl(struct tegra_spi_data *tspi,
  200. unsigned long reg)
  201. {
  202. return readl(tspi->base + reg);
  203. }
  204. static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
  205. u32 val, unsigned long reg)
  206. {
  207. writel(val, tspi->base + reg);
  208. /* Read back register to make sure that register writes completed */
  209. if (reg != SPI_TX_FIFO)
  210. readl(tspi->base + SPI_COMMAND1);
  211. }
  212. static void tegra_spi_clear_status(struct tegra_spi_data *tspi)
  213. {
  214. u32 val;
  215. /* Write 1 to clear status register */
  216. val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
  217. tegra_spi_writel(tspi, val, SPI_TRANS_STATUS);
  218. /* Clear fifo status error if any */
  219. val = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
  220. if (val & SPI_ERR)
  221. tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR,
  222. SPI_FIFO_STATUS);
  223. }
  224. static unsigned tegra_spi_calculate_curr_xfer_param(
  225. struct spi_device *spi, struct tegra_spi_data *tspi,
  226. struct spi_transfer *t)
  227. {
  228. unsigned remain_len = t->len - tspi->cur_pos;
  229. unsigned max_word;
  230. unsigned bits_per_word = t->bits_per_word;
  231. unsigned max_len;
  232. unsigned total_fifo_words;
  233. tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
  234. if ((bits_per_word == 8 || bits_per_word == 16 ||
  235. bits_per_word == 32) && t->len > 3) {
  236. tspi->is_packed = true;
  237. tspi->words_per_32bit = 32/bits_per_word;
  238. } else {
  239. tspi->is_packed = false;
  240. tspi->words_per_32bit = 1;
  241. }
  242. if (tspi->is_packed) {
  243. max_len = min(remain_len, tspi->max_buf_size);
  244. tspi->curr_dma_words = max_len/tspi->bytes_per_word;
  245. total_fifo_words = (max_len + 3) / 4;
  246. } else {
  247. max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
  248. max_word = min(max_word, tspi->max_buf_size/4);
  249. tspi->curr_dma_words = max_word;
  250. total_fifo_words = max_word;
  251. }
  252. return total_fifo_words;
  253. }
  254. static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
  255. struct tegra_spi_data *tspi, struct spi_transfer *t)
  256. {
  257. unsigned nbytes;
  258. unsigned tx_empty_count;
  259. u32 fifo_status;
  260. unsigned max_n_32bit;
  261. unsigned i, count;
  262. unsigned int written_words;
  263. unsigned fifo_words_left;
  264. u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
  265. fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
  266. tx_empty_count = SPI_TX_FIFO_EMPTY_COUNT(fifo_status);
  267. if (tspi->is_packed) {
  268. fifo_words_left = tx_empty_count * tspi->words_per_32bit;
  269. written_words = min(fifo_words_left, tspi->curr_dma_words);
  270. nbytes = written_words * tspi->bytes_per_word;
  271. max_n_32bit = DIV_ROUND_UP(nbytes, 4);
  272. for (count = 0; count < max_n_32bit; count++) {
  273. u32 x = 0;
  274. for (i = 0; (i < 4) && nbytes; i++, nbytes--)
  275. x |= (u32)(*tx_buf++) << (i * 8);
  276. tegra_spi_writel(tspi, x, SPI_TX_FIFO);
  277. }
  278. tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
  279. } else {
  280. unsigned int write_bytes;
  281. max_n_32bit = min(tspi->curr_dma_words, tx_empty_count);
  282. written_words = max_n_32bit;
  283. nbytes = written_words * tspi->bytes_per_word;
  284. if (nbytes > t->len - tspi->cur_pos)
  285. nbytes = t->len - tspi->cur_pos;
  286. write_bytes = nbytes;
  287. for (count = 0; count < max_n_32bit; count++) {
  288. u32 x = 0;
  289. for (i = 0; nbytes && (i < tspi->bytes_per_word);
  290. i++, nbytes--)
  291. x |= (u32)(*tx_buf++) << (i * 8);
  292. tegra_spi_writel(tspi, x, SPI_TX_FIFO);
  293. }
  294. tspi->cur_tx_pos += write_bytes;
  295. }
  296. return written_words;
  297. }
  298. static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
  299. struct tegra_spi_data *tspi, struct spi_transfer *t)
  300. {
  301. unsigned rx_full_count;
  302. u32 fifo_status;
  303. unsigned i, count;
  304. unsigned int read_words = 0;
  305. unsigned len;
  306. u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
  307. fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
  308. rx_full_count = SPI_RX_FIFO_FULL_COUNT(fifo_status);
  309. if (tspi->is_packed) {
  310. len = tspi->curr_dma_words * tspi->bytes_per_word;
  311. for (count = 0; count < rx_full_count; count++) {
  312. u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO);
  313. for (i = 0; len && (i < 4); i++, len--)
  314. *rx_buf++ = (x >> i*8) & 0xFF;
  315. }
  316. read_words += tspi->curr_dma_words;
  317. tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
  318. } else {
  319. u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
  320. u8 bytes_per_word = tspi->bytes_per_word;
  321. unsigned int read_bytes;
  322. len = rx_full_count * bytes_per_word;
  323. if (len > t->len - tspi->cur_pos)
  324. len = t->len - tspi->cur_pos;
  325. read_bytes = len;
  326. for (count = 0; count < rx_full_count; count++) {
  327. u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask;
  328. for (i = 0; len && (i < bytes_per_word); i++, len--)
  329. *rx_buf++ = (x >> (i*8)) & 0xFF;
  330. }
  331. read_words += rx_full_count;
  332. tspi->cur_rx_pos += read_bytes;
  333. }
  334. return read_words;
  335. }
  336. static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
  337. struct tegra_spi_data *tspi, struct spi_transfer *t)
  338. {
  339. /* Make the dma buffer to read by cpu */
  340. dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
  341. tspi->dma_buf_size, DMA_TO_DEVICE);
  342. if (tspi->is_packed) {
  343. unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
  344. memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
  345. tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
  346. } else {
  347. unsigned int i;
  348. unsigned int count;
  349. u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
  350. unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
  351. unsigned int write_bytes;
  352. if (consume > t->len - tspi->cur_pos)
  353. consume = t->len - tspi->cur_pos;
  354. write_bytes = consume;
  355. for (count = 0; count < tspi->curr_dma_words; count++) {
  356. u32 x = 0;
  357. for (i = 0; consume && (i < tspi->bytes_per_word);
  358. i++, consume--)
  359. x |= (u32)(*tx_buf++) << (i * 8);
  360. tspi->tx_dma_buf[count] = x;
  361. }
  362. tspi->cur_tx_pos += write_bytes;
  363. }
  364. /* Make the dma buffer to read by dma */
  365. dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
  366. tspi->dma_buf_size, DMA_TO_DEVICE);
  367. }
  368. static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
  369. struct tegra_spi_data *tspi, struct spi_transfer *t)
  370. {
  371. /* Make the dma buffer to read by cpu */
  372. dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
  373. tspi->dma_buf_size, DMA_FROM_DEVICE);
  374. if (tspi->is_packed) {
  375. unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
  376. memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
  377. tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
  378. } else {
  379. unsigned int i;
  380. unsigned int count;
  381. unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
  382. u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
  383. unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
  384. unsigned int read_bytes;
  385. if (consume > t->len - tspi->cur_pos)
  386. consume = t->len - tspi->cur_pos;
  387. read_bytes = consume;
  388. for (count = 0; count < tspi->curr_dma_words; count++) {
  389. u32 x = tspi->rx_dma_buf[count] & rx_mask;
  390. for (i = 0; consume && (i < tspi->bytes_per_word);
  391. i++, consume--)
  392. *rx_buf++ = (x >> (i*8)) & 0xFF;
  393. }
  394. tspi->cur_rx_pos += read_bytes;
  395. }
  396. /* Make the dma buffer to read by dma */
  397. dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
  398. tspi->dma_buf_size, DMA_FROM_DEVICE);
  399. }
  400. static void tegra_spi_dma_complete(void *args)
  401. {
  402. struct completion *dma_complete = args;
  403. complete(dma_complete);
  404. }
  405. static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len)
  406. {
  407. reinit_completion(&tspi->tx_dma_complete);
  408. tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
  409. tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
  410. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  411. if (!tspi->tx_dma_desc) {
  412. dev_err(tspi->dev, "Not able to get desc for Tx\n");
  413. return -EIO;
  414. }
  415. tspi->tx_dma_desc->callback = tegra_spi_dma_complete;
  416. tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
  417. dmaengine_submit(tspi->tx_dma_desc);
  418. dma_async_issue_pending(tspi->tx_dma_chan);
  419. return 0;
  420. }
  421. static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len)
  422. {
  423. reinit_completion(&tspi->rx_dma_complete);
  424. tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
  425. tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
  426. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  427. if (!tspi->rx_dma_desc) {
  428. dev_err(tspi->dev, "Not able to get desc for Rx\n");
  429. return -EIO;
  430. }
  431. tspi->rx_dma_desc->callback = tegra_spi_dma_complete;
  432. tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
  433. dmaengine_submit(tspi->rx_dma_desc);
  434. dma_async_issue_pending(tspi->rx_dma_chan);
  435. return 0;
  436. }
  437. static int tegra_spi_flush_fifos(struct tegra_spi_data *tspi)
  438. {
  439. unsigned long timeout = jiffies + HZ;
  440. u32 status;
  441. status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
  442. if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
  443. status |= SPI_RX_FIFO_FLUSH | SPI_TX_FIFO_FLUSH;
  444. tegra_spi_writel(tspi, status, SPI_FIFO_STATUS);
  445. while ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
  446. status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
  447. if (time_after(jiffies, timeout)) {
  448. dev_err(tspi->dev,
  449. "timeout waiting for fifo flush\n");
  450. return -EIO;
  451. }
  452. udelay(1);
  453. }
  454. }
  455. return 0;
  456. }
  457. static int tegra_spi_start_dma_based_transfer(
  458. struct tegra_spi_data *tspi, struct spi_transfer *t)
  459. {
  460. u32 val;
  461. unsigned int len;
  462. int ret = 0;
  463. u8 dma_burst;
  464. struct dma_slave_config dma_sconfig = {0};
  465. val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1);
  466. tegra_spi_writel(tspi, val, SPI_DMA_BLK);
  467. if (tspi->is_packed)
  468. len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
  469. 4) * 4;
  470. else
  471. len = tspi->curr_dma_words * 4;
  472. /* Set attention level based on length of transfer */
  473. if (len & 0xF) {
  474. val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1;
  475. dma_burst = 1;
  476. } else if (((len) >> 4) & 0x1) {
  477. val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4;
  478. dma_burst = 4;
  479. } else {
  480. val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8;
  481. dma_burst = 8;
  482. }
  483. if (!tspi->soc_data->has_intr_mask_reg) {
  484. if (tspi->cur_direction & DATA_DIR_TX)
  485. val |= SPI_IE_TX;
  486. if (tspi->cur_direction & DATA_DIR_RX)
  487. val |= SPI_IE_RX;
  488. }
  489. tegra_spi_writel(tspi, val, SPI_DMA_CTL);
  490. tspi->dma_control_reg = val;
  491. dma_sconfig.device_fc = true;
  492. if (tspi->cur_direction & DATA_DIR_TX) {
  493. dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO;
  494. dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  495. dma_sconfig.dst_maxburst = dma_burst;
  496. ret = dmaengine_slave_config(tspi->tx_dma_chan, &dma_sconfig);
  497. if (ret < 0) {
  498. dev_err(tspi->dev,
  499. "DMA slave config failed: %d\n", ret);
  500. return ret;
  501. }
  502. tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t);
  503. ret = tegra_spi_start_tx_dma(tspi, len);
  504. if (ret < 0) {
  505. dev_err(tspi->dev,
  506. "Starting tx dma failed, err %d\n", ret);
  507. return ret;
  508. }
  509. }
  510. if (tspi->cur_direction & DATA_DIR_RX) {
  511. dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
  512. dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  513. dma_sconfig.src_maxburst = dma_burst;
  514. ret = dmaengine_slave_config(tspi->rx_dma_chan, &dma_sconfig);
  515. if (ret < 0) {
  516. dev_err(tspi->dev,
  517. "DMA slave config failed: %d\n", ret);
  518. return ret;
  519. }
  520. /* Make the dma buffer to read by dma */
  521. dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
  522. tspi->dma_buf_size, DMA_FROM_DEVICE);
  523. ret = tegra_spi_start_rx_dma(tspi, len);
  524. if (ret < 0) {
  525. dev_err(tspi->dev,
  526. "Starting rx dma failed, err %d\n", ret);
  527. if (tspi->cur_direction & DATA_DIR_TX)
  528. dmaengine_terminate_all(tspi->tx_dma_chan);
  529. return ret;
  530. }
  531. }
  532. tspi->is_curr_dma_xfer = true;
  533. tspi->dma_control_reg = val;
  534. val |= SPI_DMA_EN;
  535. tegra_spi_writel(tspi, val, SPI_DMA_CTL);
  536. return ret;
  537. }
  538. static int tegra_spi_start_cpu_based_transfer(
  539. struct tegra_spi_data *tspi, struct spi_transfer *t)
  540. {
  541. u32 val;
  542. unsigned cur_words;
  543. if (tspi->cur_direction & DATA_DIR_TX)
  544. cur_words = tegra_spi_fill_tx_fifo_from_client_txbuf(tspi, t);
  545. else
  546. cur_words = tspi->curr_dma_words;
  547. val = SPI_DMA_BLK_SET(cur_words - 1);
  548. tegra_spi_writel(tspi, val, SPI_DMA_BLK);
  549. val = 0;
  550. if (tspi->cur_direction & DATA_DIR_TX)
  551. val |= SPI_IE_TX;
  552. if (tspi->cur_direction & DATA_DIR_RX)
  553. val |= SPI_IE_RX;
  554. tegra_spi_writel(tspi, val, SPI_DMA_CTL);
  555. tspi->dma_control_reg = val;
  556. tspi->is_curr_dma_xfer = false;
  557. val = tspi->command1_reg;
  558. val |= SPI_PIO;
  559. tegra_spi_writel(tspi, val, SPI_COMMAND1);
  560. return 0;
  561. }
  562. static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
  563. bool dma_to_memory)
  564. {
  565. struct dma_chan *dma_chan;
  566. u32 *dma_buf;
  567. dma_addr_t dma_phys;
  568. dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx");
  569. if (IS_ERR(dma_chan))
  570. return dev_err_probe(tspi->dev, PTR_ERR(dma_chan),
  571. "Dma channel is not available\n");
  572. dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
  573. &dma_phys, GFP_KERNEL);
  574. if (!dma_buf) {
  575. dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
  576. dma_release_channel(dma_chan);
  577. return -ENOMEM;
  578. }
  579. if (dma_to_memory) {
  580. tspi->rx_dma_chan = dma_chan;
  581. tspi->rx_dma_buf = dma_buf;
  582. tspi->rx_dma_phys = dma_phys;
  583. } else {
  584. tspi->tx_dma_chan = dma_chan;
  585. tspi->tx_dma_buf = dma_buf;
  586. tspi->tx_dma_phys = dma_phys;
  587. }
  588. return 0;
  589. }
  590. static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
  591. bool dma_to_memory)
  592. {
  593. u32 *dma_buf;
  594. dma_addr_t dma_phys;
  595. struct dma_chan *dma_chan;
  596. if (dma_to_memory) {
  597. dma_buf = tspi->rx_dma_buf;
  598. dma_chan = tspi->rx_dma_chan;
  599. dma_phys = tspi->rx_dma_phys;
  600. tspi->rx_dma_chan = NULL;
  601. tspi->rx_dma_buf = NULL;
  602. } else {
  603. dma_buf = tspi->tx_dma_buf;
  604. dma_chan = tspi->tx_dma_chan;
  605. dma_phys = tspi->tx_dma_phys;
  606. tspi->tx_dma_buf = NULL;
  607. tspi->tx_dma_chan = NULL;
  608. }
  609. if (!dma_chan)
  610. return;
  611. dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
  612. dma_release_channel(dma_chan);
  613. }
  614. static int tegra_spi_set_hw_cs_timing(struct spi_device *spi,
  615. struct spi_delay *setup,
  616. struct spi_delay *hold,
  617. struct spi_delay *inactive)
  618. {
  619. struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
  620. u8 setup_dly, hold_dly, inactive_dly;
  621. u32 setup_hold;
  622. u32 spi_cs_timing;
  623. u32 inactive_cycles;
  624. u8 cs_state;
  625. if ((setup && setup->unit != SPI_DELAY_UNIT_SCK) ||
  626. (hold && hold->unit != SPI_DELAY_UNIT_SCK) ||
  627. (inactive && inactive->unit != SPI_DELAY_UNIT_SCK)) {
  628. dev_err(&spi->dev,
  629. "Invalid delay unit %d, should be SPI_DELAY_UNIT_SCK\n",
  630. SPI_DELAY_UNIT_SCK);
  631. return -EINVAL;
  632. }
  633. setup_dly = setup ? setup->value : 0;
  634. hold_dly = hold ? hold->value : 0;
  635. inactive_dly = inactive ? inactive->value : 0;
  636. setup_dly = min_t(u8, setup_dly, MAX_SETUP_HOLD_CYCLES);
  637. hold_dly = min_t(u8, hold_dly, MAX_SETUP_HOLD_CYCLES);
  638. if (setup_dly && hold_dly) {
  639. setup_hold = SPI_SETUP_HOLD(setup_dly - 1, hold_dly - 1);
  640. spi_cs_timing = SPI_CS_SETUP_HOLD(tspi->spi_cs_timing1,
  641. spi->chip_select,
  642. setup_hold);
  643. if (tspi->spi_cs_timing1 != spi_cs_timing) {
  644. tspi->spi_cs_timing1 = spi_cs_timing;
  645. tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING1);
  646. }
  647. }
  648. inactive_cycles = min_t(u8, inactive_dly, MAX_INACTIVE_CYCLES);
  649. if (inactive_cycles)
  650. inactive_cycles--;
  651. cs_state = inactive_cycles ? 0 : 1;
  652. spi_cs_timing = tspi->spi_cs_timing2;
  653. SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(spi_cs_timing, spi->chip_select,
  654. cs_state);
  655. SPI_SET_CYCLES_BETWEEN_PACKETS(spi_cs_timing, spi->chip_select,
  656. inactive_cycles);
  657. if (tspi->spi_cs_timing2 != spi_cs_timing) {
  658. tspi->spi_cs_timing2 = spi_cs_timing;
  659. tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING2);
  660. }
  661. return 0;
  662. }
  663. static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
  664. struct spi_transfer *t,
  665. bool is_first_of_msg,
  666. bool is_single_xfer)
  667. {
  668. struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
  669. struct tegra_spi_client_data *cdata = spi->controller_data;
  670. u32 speed = t->speed_hz;
  671. u8 bits_per_word = t->bits_per_word;
  672. u32 command1, command2;
  673. int req_mode;
  674. u32 tx_tap = 0, rx_tap = 0;
  675. if (speed != tspi->cur_speed) {
  676. clk_set_rate(tspi->clk, speed);
  677. tspi->cur_speed = speed;
  678. }
  679. tspi->cur_spi = spi;
  680. tspi->cur_pos = 0;
  681. tspi->cur_rx_pos = 0;
  682. tspi->cur_tx_pos = 0;
  683. tspi->curr_xfer = t;
  684. if (is_first_of_msg) {
  685. tegra_spi_clear_status(tspi);
  686. command1 = tspi->def_command1_reg;
  687. command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
  688. command1 &= ~SPI_CONTROL_MODE_MASK;
  689. req_mode = spi->mode & 0x3;
  690. if (req_mode == SPI_MODE_0)
  691. command1 |= SPI_CONTROL_MODE_0;
  692. else if (req_mode == SPI_MODE_1)
  693. command1 |= SPI_CONTROL_MODE_1;
  694. else if (req_mode == SPI_MODE_2)
  695. command1 |= SPI_CONTROL_MODE_2;
  696. else if (req_mode == SPI_MODE_3)
  697. command1 |= SPI_CONTROL_MODE_3;
  698. if (spi->mode & SPI_LSB_FIRST)
  699. command1 |= SPI_LSBIT_FE;
  700. else
  701. command1 &= ~SPI_LSBIT_FE;
  702. if (spi->mode & SPI_3WIRE)
  703. command1 |= SPI_BIDIROE;
  704. else
  705. command1 &= ~SPI_BIDIROE;
  706. if (tspi->cs_control) {
  707. if (tspi->cs_control != spi)
  708. tegra_spi_writel(tspi, command1, SPI_COMMAND1);
  709. tspi->cs_control = NULL;
  710. } else
  711. tegra_spi_writel(tspi, command1, SPI_COMMAND1);
  712. /* GPIO based chip select control */
  713. if (spi->cs_gpiod)
  714. gpiod_set_value(spi->cs_gpiod, 1);
  715. if (is_single_xfer && !(t->cs_change)) {
  716. tspi->use_hw_based_cs = true;
  717. command1 &= ~(SPI_CS_SW_HW | SPI_CS_SW_VAL);
  718. } else {
  719. tspi->use_hw_based_cs = false;
  720. command1 |= SPI_CS_SW_HW;
  721. if (spi->mode & SPI_CS_HIGH)
  722. command1 |= SPI_CS_SW_VAL;
  723. else
  724. command1 &= ~SPI_CS_SW_VAL;
  725. }
  726. if (tspi->last_used_cs != spi->chip_select) {
  727. if (cdata && cdata->tx_clk_tap_delay)
  728. tx_tap = cdata->tx_clk_tap_delay;
  729. if (cdata && cdata->rx_clk_tap_delay)
  730. rx_tap = cdata->rx_clk_tap_delay;
  731. command2 = SPI_TX_TAP_DELAY(tx_tap) |
  732. SPI_RX_TAP_DELAY(rx_tap);
  733. if (command2 != tspi->def_command2_reg)
  734. tegra_spi_writel(tspi, command2, SPI_COMMAND2);
  735. tspi->last_used_cs = spi->chip_select;
  736. }
  737. } else {
  738. command1 = tspi->command1_reg;
  739. command1 &= ~SPI_BIT_LENGTH(~0);
  740. command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
  741. }
  742. return command1;
  743. }
  744. static int tegra_spi_start_transfer_one(struct spi_device *spi,
  745. struct spi_transfer *t, u32 command1)
  746. {
  747. struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
  748. unsigned total_fifo_words;
  749. int ret;
  750. total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t);
  751. if (t->rx_nbits == SPI_NBITS_DUAL || t->tx_nbits == SPI_NBITS_DUAL)
  752. command1 |= SPI_BOTH_EN_BIT;
  753. else
  754. command1 &= ~SPI_BOTH_EN_BIT;
  755. if (tspi->is_packed)
  756. command1 |= SPI_PACKED;
  757. else
  758. command1 &= ~SPI_PACKED;
  759. command1 &= ~(SPI_CS_SEL_MASK | SPI_TX_EN | SPI_RX_EN);
  760. tspi->cur_direction = 0;
  761. if (t->rx_buf) {
  762. command1 |= SPI_RX_EN;
  763. tspi->cur_direction |= DATA_DIR_RX;
  764. }
  765. if (t->tx_buf) {
  766. command1 |= SPI_TX_EN;
  767. tspi->cur_direction |= DATA_DIR_TX;
  768. }
  769. command1 |= SPI_CS_SEL(spi->chip_select);
  770. tegra_spi_writel(tspi, command1, SPI_COMMAND1);
  771. tspi->command1_reg = command1;
  772. dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n",
  773. tspi->def_command1_reg, (unsigned)command1);
  774. ret = tegra_spi_flush_fifos(tspi);
  775. if (ret < 0)
  776. return ret;
  777. if (total_fifo_words > SPI_FIFO_DEPTH)
  778. ret = tegra_spi_start_dma_based_transfer(tspi, t);
  779. else
  780. ret = tegra_spi_start_cpu_based_transfer(tspi, t);
  781. return ret;
  782. }
  783. static struct tegra_spi_client_data
  784. *tegra_spi_parse_cdata_dt(struct spi_device *spi)
  785. {
  786. struct tegra_spi_client_data *cdata;
  787. struct device_node *slave_np;
  788. slave_np = spi->dev.of_node;
  789. if (!slave_np) {
  790. dev_dbg(&spi->dev, "device node not found\n");
  791. return NULL;
  792. }
  793. cdata = kzalloc(sizeof(*cdata), GFP_KERNEL);
  794. if (!cdata)
  795. return NULL;
  796. of_property_read_u32(slave_np, "nvidia,tx-clk-tap-delay",
  797. &cdata->tx_clk_tap_delay);
  798. of_property_read_u32(slave_np, "nvidia,rx-clk-tap-delay",
  799. &cdata->rx_clk_tap_delay);
  800. return cdata;
  801. }
  802. static void tegra_spi_cleanup(struct spi_device *spi)
  803. {
  804. struct tegra_spi_client_data *cdata = spi->controller_data;
  805. spi->controller_data = NULL;
  806. if (spi->dev.of_node)
  807. kfree(cdata);
  808. }
  809. static int tegra_spi_setup(struct spi_device *spi)
  810. {
  811. struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
  812. struct tegra_spi_client_data *cdata = spi->controller_data;
  813. u32 val;
  814. unsigned long flags;
  815. int ret;
  816. dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
  817. spi->bits_per_word,
  818. spi->mode & SPI_CPOL ? "" : "~",
  819. spi->mode & SPI_CPHA ? "" : "~",
  820. spi->max_speed_hz);
  821. if (!cdata) {
  822. cdata = tegra_spi_parse_cdata_dt(spi);
  823. spi->controller_data = cdata;
  824. }
  825. ret = pm_runtime_get_sync(tspi->dev);
  826. if (ret < 0) {
  827. pm_runtime_put_noidle(tspi->dev);
  828. dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
  829. if (cdata)
  830. tegra_spi_cleanup(spi);
  831. return ret;
  832. }
  833. if (tspi->soc_data->has_intr_mask_reg) {
  834. val = tegra_spi_readl(tspi, SPI_INTR_MASK);
  835. val &= ~SPI_INTR_ALL_MASK;
  836. tegra_spi_writel(tspi, val, SPI_INTR_MASK);
  837. }
  838. spin_lock_irqsave(&tspi->lock, flags);
  839. /* GPIO based chip select control */
  840. if (spi->cs_gpiod)
  841. gpiod_set_value(spi->cs_gpiod, 0);
  842. val = tspi->def_command1_reg;
  843. if (spi->mode & SPI_CS_HIGH)
  844. val &= ~SPI_CS_POL_INACTIVE(spi->chip_select);
  845. else
  846. val |= SPI_CS_POL_INACTIVE(spi->chip_select);
  847. tspi->def_command1_reg = val;
  848. tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
  849. spin_unlock_irqrestore(&tspi->lock, flags);
  850. pm_runtime_put(tspi->dev);
  851. return 0;
  852. }
  853. static void tegra_spi_transfer_end(struct spi_device *spi)
  854. {
  855. struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
  856. int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;
  857. /* GPIO based chip select control */
  858. if (spi->cs_gpiod)
  859. gpiod_set_value(spi->cs_gpiod, 0);
  860. if (!tspi->use_hw_based_cs) {
  861. if (cs_val)
  862. tspi->command1_reg |= SPI_CS_SW_VAL;
  863. else
  864. tspi->command1_reg &= ~SPI_CS_SW_VAL;
  865. tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
  866. }
  867. tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
  868. }
  869. static void tegra_spi_dump_regs(struct tegra_spi_data *tspi)
  870. {
  871. dev_dbg(tspi->dev, "============ SPI REGISTER DUMP ============\n");
  872. dev_dbg(tspi->dev, "Command1: 0x%08x | Command2: 0x%08x\n",
  873. tegra_spi_readl(tspi, SPI_COMMAND1),
  874. tegra_spi_readl(tspi, SPI_COMMAND2));
  875. dev_dbg(tspi->dev, "DMA_CTL: 0x%08x | DMA_BLK: 0x%08x\n",
  876. tegra_spi_readl(tspi, SPI_DMA_CTL),
  877. tegra_spi_readl(tspi, SPI_DMA_BLK));
  878. dev_dbg(tspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n",
  879. tegra_spi_readl(tspi, SPI_TRANS_STATUS),
  880. tegra_spi_readl(tspi, SPI_FIFO_STATUS));
  881. }
  882. static int tegra_spi_transfer_one_message(struct spi_master *master,
  883. struct spi_message *msg)
  884. {
  885. bool is_first_msg = true;
  886. struct tegra_spi_data *tspi = spi_master_get_devdata(master);
  887. struct spi_transfer *xfer;
  888. struct spi_device *spi = msg->spi;
  889. int ret;
  890. bool skip = false;
  891. int single_xfer;
  892. msg->status = 0;
  893. msg->actual_length = 0;
  894. single_xfer = list_is_singular(&msg->transfers);
  895. list_for_each_entry(xfer, &msg->transfers, transfer_list) {
  896. u32 cmd1;
  897. reinit_completion(&tspi->xfer_completion);
  898. cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg,
  899. single_xfer);
  900. if (!xfer->len) {
  901. ret = 0;
  902. skip = true;
  903. goto complete_xfer;
  904. }
  905. ret = tegra_spi_start_transfer_one(spi, xfer, cmd1);
  906. if (ret < 0) {
  907. dev_err(tspi->dev,
  908. "spi can not start transfer, err %d\n", ret);
  909. goto complete_xfer;
  910. }
  911. is_first_msg = false;
  912. ret = wait_for_completion_timeout(&tspi->xfer_completion,
  913. SPI_DMA_TIMEOUT);
  914. if (WARN_ON(ret == 0)) {
  915. dev_err(tspi->dev,
  916. "spi transfer timeout, err %d\n", ret);
  917. if (tspi->is_curr_dma_xfer &&
  918. (tspi->cur_direction & DATA_DIR_TX))
  919. dmaengine_terminate_all(tspi->tx_dma_chan);
  920. if (tspi->is_curr_dma_xfer &&
  921. (tspi->cur_direction & DATA_DIR_RX))
  922. dmaengine_terminate_all(tspi->rx_dma_chan);
  923. ret = -EIO;
  924. tegra_spi_dump_regs(tspi);
  925. tegra_spi_flush_fifos(tspi);
  926. reset_control_assert(tspi->rst);
  927. udelay(2);
  928. reset_control_deassert(tspi->rst);
  929. tspi->last_used_cs = master->num_chipselect + 1;
  930. goto complete_xfer;
  931. }
  932. if (tspi->tx_status || tspi->rx_status) {
  933. dev_err(tspi->dev, "Error in Transfer\n");
  934. ret = -EIO;
  935. tegra_spi_dump_regs(tspi);
  936. goto complete_xfer;
  937. }
  938. msg->actual_length += xfer->len;
  939. complete_xfer:
  940. if (ret < 0 || skip) {
  941. tegra_spi_transfer_end(spi);
  942. spi_transfer_delay_exec(xfer);
  943. goto exit;
  944. } else if (list_is_last(&xfer->transfer_list,
  945. &msg->transfers)) {
  946. if (xfer->cs_change)
  947. tspi->cs_control = spi;
  948. else {
  949. tegra_spi_transfer_end(spi);
  950. spi_transfer_delay_exec(xfer);
  951. }
  952. } else if (xfer->cs_change) {
  953. tegra_spi_transfer_end(spi);
  954. spi_transfer_delay_exec(xfer);
  955. }
  956. }
  957. ret = 0;
  958. exit:
  959. msg->status = ret;
  960. spi_finalize_current_message(master);
  961. return ret;
  962. }
  963. static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
  964. {
  965. struct spi_transfer *t = tspi->curr_xfer;
  966. unsigned long flags;
  967. spin_lock_irqsave(&tspi->lock, flags);
  968. if (tspi->tx_status || tspi->rx_status) {
  969. dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n",
  970. tspi->status_reg);
  971. dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
  972. tspi->command1_reg, tspi->dma_control_reg);
  973. tegra_spi_dump_regs(tspi);
  974. tegra_spi_flush_fifos(tspi);
  975. complete(&tspi->xfer_completion);
  976. spin_unlock_irqrestore(&tspi->lock, flags);
  977. reset_control_assert(tspi->rst);
  978. udelay(2);
  979. reset_control_deassert(tspi->rst);
  980. return IRQ_HANDLED;
  981. }
  982. if (tspi->cur_direction & DATA_DIR_RX)
  983. tegra_spi_read_rx_fifo_to_client_rxbuf(tspi, t);
  984. if (tspi->cur_direction & DATA_DIR_TX)
  985. tspi->cur_pos = tspi->cur_tx_pos;
  986. else
  987. tspi->cur_pos = tspi->cur_rx_pos;
  988. if (tspi->cur_pos == t->len) {
  989. complete(&tspi->xfer_completion);
  990. goto exit;
  991. }
  992. tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
  993. tegra_spi_start_cpu_based_transfer(tspi, t);
  994. exit:
  995. spin_unlock_irqrestore(&tspi->lock, flags);
  996. return IRQ_HANDLED;
  997. }
  998. static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
  999. {
  1000. struct spi_transfer *t = tspi->curr_xfer;
  1001. long wait_status;
  1002. int err = 0;
  1003. unsigned total_fifo_words;
  1004. unsigned long flags;
  1005. /* Abort dmas if any error */
  1006. if (tspi->cur_direction & DATA_DIR_TX) {
  1007. if (tspi->tx_status) {
  1008. dmaengine_terminate_all(tspi->tx_dma_chan);
  1009. err += 1;
  1010. } else {
  1011. wait_status = wait_for_completion_interruptible_timeout(
  1012. &tspi->tx_dma_complete, SPI_DMA_TIMEOUT);
  1013. if (wait_status <= 0) {
  1014. dmaengine_terminate_all(tspi->tx_dma_chan);
  1015. dev_err(tspi->dev, "TxDma Xfer failed\n");
  1016. err += 1;
  1017. }
  1018. }
  1019. }
  1020. if (tspi->cur_direction & DATA_DIR_RX) {
  1021. if (tspi->rx_status) {
  1022. dmaengine_terminate_all(tspi->rx_dma_chan);
  1023. err += 2;
  1024. } else {
  1025. wait_status = wait_for_completion_interruptible_timeout(
  1026. &tspi->rx_dma_complete, SPI_DMA_TIMEOUT);
  1027. if (wait_status <= 0) {
  1028. dmaengine_terminate_all(tspi->rx_dma_chan);
  1029. dev_err(tspi->dev, "RxDma Xfer failed\n");
  1030. err += 2;
  1031. }
  1032. }
  1033. }
  1034. spin_lock_irqsave(&tspi->lock, flags);
  1035. if (err) {
  1036. dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n",
  1037. tspi->status_reg);
  1038. dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
  1039. tspi->command1_reg, tspi->dma_control_reg);
  1040. tegra_spi_dump_regs(tspi);
  1041. tegra_spi_flush_fifos(tspi);
  1042. complete(&tspi->xfer_completion);
  1043. spin_unlock_irqrestore(&tspi->lock, flags);
  1044. reset_control_assert(tspi->rst);
  1045. udelay(2);
  1046. reset_control_deassert(tspi->rst);
  1047. return IRQ_HANDLED;
  1048. }
  1049. if (tspi->cur_direction & DATA_DIR_RX)
  1050. tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
  1051. if (tspi->cur_direction & DATA_DIR_TX)
  1052. tspi->cur_pos = tspi->cur_tx_pos;
  1053. else
  1054. tspi->cur_pos = tspi->cur_rx_pos;
  1055. if (tspi->cur_pos == t->len) {
  1056. complete(&tspi->xfer_completion);
  1057. goto exit;
  1058. }
  1059. /* Continue transfer in current message */
  1060. total_fifo_words = tegra_spi_calculate_curr_xfer_param(tspi->cur_spi,
  1061. tspi, t);
  1062. if (total_fifo_words > SPI_FIFO_DEPTH)
  1063. err = tegra_spi_start_dma_based_transfer(tspi, t);
  1064. else
  1065. err = tegra_spi_start_cpu_based_transfer(tspi, t);
  1066. exit:
  1067. spin_unlock_irqrestore(&tspi->lock, flags);
  1068. return IRQ_HANDLED;
  1069. }
  1070. static irqreturn_t tegra_spi_isr_thread(int irq, void *context_data)
  1071. {
  1072. struct tegra_spi_data *tspi = context_data;
  1073. if (!tspi->is_curr_dma_xfer)
  1074. return handle_cpu_based_xfer(tspi);
  1075. return handle_dma_based_xfer(tspi);
  1076. }
  1077. static irqreturn_t tegra_spi_isr(int irq, void *context_data)
  1078. {
  1079. struct tegra_spi_data *tspi = context_data;
  1080. tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
  1081. if (tspi->cur_direction & DATA_DIR_TX)
  1082. tspi->tx_status = tspi->status_reg &
  1083. (SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF);
  1084. if (tspi->cur_direction & DATA_DIR_RX)
  1085. tspi->rx_status = tspi->status_reg &
  1086. (SPI_RX_FIFO_OVF | SPI_RX_FIFO_UNF);
  1087. tegra_spi_clear_status(tspi);
  1088. return IRQ_WAKE_THREAD;
  1089. }
  1090. static struct tegra_spi_soc_data tegra114_spi_soc_data = {
  1091. .has_intr_mask_reg = false,
  1092. };
  1093. static struct tegra_spi_soc_data tegra124_spi_soc_data = {
  1094. .has_intr_mask_reg = false,
  1095. };
  1096. static struct tegra_spi_soc_data tegra210_spi_soc_data = {
  1097. .has_intr_mask_reg = true,
  1098. };
  1099. static const struct of_device_id tegra_spi_of_match[] = {
  1100. {
  1101. .compatible = "nvidia,tegra114-spi",
  1102. .data = &tegra114_spi_soc_data,
  1103. }, {
  1104. .compatible = "nvidia,tegra124-spi",
  1105. .data = &tegra124_spi_soc_data,
  1106. }, {
  1107. .compatible = "nvidia,tegra210-spi",
  1108. .data = &tegra210_spi_soc_data,
  1109. },
  1110. {}
  1111. };
  1112. MODULE_DEVICE_TABLE(of, tegra_spi_of_match);
  1113. static int tegra_spi_probe(struct platform_device *pdev)
  1114. {
  1115. struct spi_master *master;
  1116. struct tegra_spi_data *tspi;
  1117. struct resource *r;
  1118. int ret, spi_irq;
  1119. int bus_num;
  1120. master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
  1121. if (!master) {
  1122. dev_err(&pdev->dev, "master allocation failed\n");
  1123. return -ENOMEM;
  1124. }
  1125. platform_set_drvdata(pdev, master);
  1126. tspi = spi_master_get_devdata(master);
  1127. if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
  1128. &master->max_speed_hz))
  1129. master->max_speed_hz = 25000000; /* 25MHz */
  1130. /* the spi->mode bits understood by this driver: */
  1131. master->use_gpio_descriptors = true;
  1132. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
  1133. SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE;
  1134. master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
  1135. master->setup = tegra_spi_setup;
  1136. master->cleanup = tegra_spi_cleanup;
  1137. master->transfer_one_message = tegra_spi_transfer_one_message;
  1138. master->set_cs_timing = tegra_spi_set_hw_cs_timing;
  1139. master->num_chipselect = MAX_CHIP_SELECT;
  1140. master->auto_runtime_pm = true;
  1141. bus_num = of_alias_get_id(pdev->dev.of_node, "spi");
  1142. if (bus_num >= 0)
  1143. master->bus_num = bus_num;
  1144. tspi->master = master;
  1145. tspi->dev = &pdev->dev;
  1146. spin_lock_init(&tspi->lock);
  1147. tspi->soc_data = of_device_get_match_data(&pdev->dev);
  1148. if (!tspi->soc_data) {
  1149. dev_err(&pdev->dev, "unsupported tegra\n");
  1150. ret = -ENODEV;
  1151. goto exit_free_master;
  1152. }
  1153. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1154. tspi->base = devm_ioremap_resource(&pdev->dev, r);
  1155. if (IS_ERR(tspi->base)) {
  1156. ret = PTR_ERR(tspi->base);
  1157. goto exit_free_master;
  1158. }
  1159. tspi->phys = r->start;
  1160. spi_irq = platform_get_irq(pdev, 0);
  1161. if (spi_irq < 0) {
  1162. ret = spi_irq;
  1163. goto exit_free_master;
  1164. }
  1165. tspi->irq = spi_irq;
  1166. tspi->clk = devm_clk_get(&pdev->dev, "spi");
  1167. if (IS_ERR(tspi->clk)) {
  1168. dev_err(&pdev->dev, "can not get clock\n");
  1169. ret = PTR_ERR(tspi->clk);
  1170. goto exit_free_master;
  1171. }
  1172. tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
  1173. if (IS_ERR(tspi->rst)) {
  1174. dev_err(&pdev->dev, "can not get reset\n");
  1175. ret = PTR_ERR(tspi->rst);
  1176. goto exit_free_master;
  1177. }
  1178. tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
  1179. tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
  1180. ret = tegra_spi_init_dma_param(tspi, true);
  1181. if (ret < 0)
  1182. goto exit_free_master;
  1183. ret = tegra_spi_init_dma_param(tspi, false);
  1184. if (ret < 0)
  1185. goto exit_rx_dma_free;
  1186. tspi->max_buf_size = tspi->dma_buf_size;
  1187. init_completion(&tspi->tx_dma_complete);
  1188. init_completion(&tspi->rx_dma_complete);
  1189. init_completion(&tspi->xfer_completion);
  1190. pm_runtime_enable(&pdev->dev);
  1191. if (!pm_runtime_enabled(&pdev->dev)) {
  1192. ret = tegra_spi_runtime_resume(&pdev->dev);
  1193. if (ret)
  1194. goto exit_pm_disable;
  1195. }
  1196. ret = pm_runtime_get_sync(&pdev->dev);
  1197. if (ret < 0) {
  1198. dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
  1199. pm_runtime_put_noidle(&pdev->dev);
  1200. goto exit_pm_disable;
  1201. }
  1202. reset_control_assert(tspi->rst);
  1203. udelay(2);
  1204. reset_control_deassert(tspi->rst);
  1205. tspi->def_command1_reg = SPI_M_S;
  1206. tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
  1207. tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1);
  1208. tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2);
  1209. tspi->def_command2_reg = tegra_spi_readl(tspi, SPI_COMMAND2);
  1210. tspi->last_used_cs = master->num_chipselect + 1;
  1211. pm_runtime_put(&pdev->dev);
  1212. ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
  1213. tegra_spi_isr_thread, IRQF_ONESHOT,
  1214. dev_name(&pdev->dev), tspi);
  1215. if (ret < 0) {
  1216. dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
  1217. tspi->irq);
  1218. goto exit_pm_disable;
  1219. }
  1220. master->dev.of_node = pdev->dev.of_node;
  1221. ret = devm_spi_register_master(&pdev->dev, master);
  1222. if (ret < 0) {
  1223. dev_err(&pdev->dev, "can not register to master err %d\n", ret);
  1224. goto exit_free_irq;
  1225. }
  1226. return ret;
  1227. exit_free_irq:
  1228. free_irq(spi_irq, tspi);
  1229. exit_pm_disable:
  1230. pm_runtime_disable(&pdev->dev);
  1231. if (!pm_runtime_status_suspended(&pdev->dev))
  1232. tegra_spi_runtime_suspend(&pdev->dev);
  1233. tegra_spi_deinit_dma_param(tspi, false);
  1234. exit_rx_dma_free:
  1235. tegra_spi_deinit_dma_param(tspi, true);
  1236. exit_free_master:
  1237. spi_master_put(master);
  1238. return ret;
  1239. }
  1240. static int tegra_spi_remove(struct platform_device *pdev)
  1241. {
  1242. struct spi_master *master = platform_get_drvdata(pdev);
  1243. struct tegra_spi_data *tspi = spi_master_get_devdata(master);
  1244. free_irq(tspi->irq, tspi);
  1245. if (tspi->tx_dma_chan)
  1246. tegra_spi_deinit_dma_param(tspi, false);
  1247. if (tspi->rx_dma_chan)
  1248. tegra_spi_deinit_dma_param(tspi, true);
  1249. pm_runtime_disable(&pdev->dev);
  1250. if (!pm_runtime_status_suspended(&pdev->dev))
  1251. tegra_spi_runtime_suspend(&pdev->dev);
  1252. return 0;
  1253. }
  1254. #ifdef CONFIG_PM_SLEEP
  1255. static int tegra_spi_suspend(struct device *dev)
  1256. {
  1257. struct spi_master *master = dev_get_drvdata(dev);
  1258. return spi_master_suspend(master);
  1259. }
  1260. static int tegra_spi_resume(struct device *dev)
  1261. {
  1262. struct spi_master *master = dev_get_drvdata(dev);
  1263. struct tegra_spi_data *tspi = spi_master_get_devdata(master);
  1264. int ret;
  1265. ret = pm_runtime_get_sync(dev);
  1266. if (ret < 0) {
  1267. pm_runtime_put_noidle(dev);
  1268. dev_err(dev, "pm runtime failed, e = %d\n", ret);
  1269. return ret;
  1270. }
  1271. tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
  1272. tegra_spi_writel(tspi, tspi->def_command2_reg, SPI_COMMAND2);
  1273. tspi->last_used_cs = master->num_chipselect + 1;
  1274. pm_runtime_put(dev);
  1275. return spi_master_resume(master);
  1276. }
  1277. #endif
  1278. static int tegra_spi_runtime_suspend(struct device *dev)
  1279. {
  1280. struct spi_master *master = dev_get_drvdata(dev);
  1281. struct tegra_spi_data *tspi = spi_master_get_devdata(master);
  1282. /* Flush all write which are in PPSB queue by reading back */
  1283. tegra_spi_readl(tspi, SPI_COMMAND1);
  1284. clk_disable_unprepare(tspi->clk);
  1285. return 0;
  1286. }
  1287. static int tegra_spi_runtime_resume(struct device *dev)
  1288. {
  1289. struct spi_master *master = dev_get_drvdata(dev);
  1290. struct tegra_spi_data *tspi = spi_master_get_devdata(master);
  1291. int ret;
  1292. ret = clk_prepare_enable(tspi->clk);
  1293. if (ret < 0) {
  1294. dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
  1295. return ret;
  1296. }
  1297. return 0;
  1298. }
  1299. static const struct dev_pm_ops tegra_spi_pm_ops = {
  1300. SET_RUNTIME_PM_OPS(tegra_spi_runtime_suspend,
  1301. tegra_spi_runtime_resume, NULL)
  1302. SET_SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend, tegra_spi_resume)
  1303. };
  1304. static struct platform_driver tegra_spi_driver = {
  1305. .driver = {
  1306. .name = "spi-tegra114",
  1307. .pm = &tegra_spi_pm_ops,
  1308. .of_match_table = tegra_spi_of_match,
  1309. },
  1310. .probe = tegra_spi_probe,
  1311. .remove = tegra_spi_remove,
  1312. };
  1313. module_platform_driver(tegra_spi_driver);
  1314. MODULE_ALIAS("platform:spi-tegra114");
  1315. MODULE_DESCRIPTION("NVIDIA Tegra114 SPI Controller Driver");
  1316. MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
  1317. MODULE_LICENSE("GPL v2");