spi-sun4i.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2012 - 2014 Allwinner Tech
  4. * Pan Nan <pannan@allwinnertech.com>
  5. *
  6. * Copyright (C) 2014 Maxime Ripard
  7. * Maxime Ripard <maxime.ripard@free-electrons.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/device.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/spi/spi.h>
  18. #define SUN4I_FIFO_DEPTH 64
  19. #define SUN4I_RXDATA_REG 0x00
  20. #define SUN4I_TXDATA_REG 0x04
  21. #define SUN4I_CTL_REG 0x08
  22. #define SUN4I_CTL_ENABLE BIT(0)
  23. #define SUN4I_CTL_MASTER BIT(1)
  24. #define SUN4I_CTL_CPHA BIT(2)
  25. #define SUN4I_CTL_CPOL BIT(3)
  26. #define SUN4I_CTL_CS_ACTIVE_LOW BIT(4)
  27. #define SUN4I_CTL_LMTF BIT(6)
  28. #define SUN4I_CTL_TF_RST BIT(8)
  29. #define SUN4I_CTL_RF_RST BIT(9)
  30. #define SUN4I_CTL_XCH BIT(10)
  31. #define SUN4I_CTL_CS_MASK 0x3000
  32. #define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK)
  33. #define SUN4I_CTL_DHB BIT(15)
  34. #define SUN4I_CTL_CS_MANUAL BIT(16)
  35. #define SUN4I_CTL_CS_LEVEL BIT(17)
  36. #define SUN4I_CTL_TP BIT(18)
  37. #define SUN4I_INT_CTL_REG 0x0c
  38. #define SUN4I_INT_CTL_RF_F34 BIT(4)
  39. #define SUN4I_INT_CTL_TF_E34 BIT(12)
  40. #define SUN4I_INT_CTL_TC BIT(16)
  41. #define SUN4I_INT_STA_REG 0x10
  42. #define SUN4I_DMA_CTL_REG 0x14
  43. #define SUN4I_WAIT_REG 0x18
  44. #define SUN4I_CLK_CTL_REG 0x1c
  45. #define SUN4I_CLK_CTL_CDR2_MASK 0xff
  46. #define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK)
  47. #define SUN4I_CLK_CTL_CDR1_MASK 0xf
  48. #define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
  49. #define SUN4I_CLK_CTL_DRS BIT(12)
  50. #define SUN4I_MAX_XFER_SIZE 0xffffff
  51. #define SUN4I_BURST_CNT_REG 0x20
  52. #define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
  53. #define SUN4I_XMIT_CNT_REG 0x24
  54. #define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
  55. #define SUN4I_FIFO_STA_REG 0x28
  56. #define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f
  57. #define SUN4I_FIFO_STA_RF_CNT_BITS 0
  58. #define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f
  59. #define SUN4I_FIFO_STA_TF_CNT_BITS 16
  60. struct sun4i_spi {
  61. struct spi_master *master;
  62. void __iomem *base_addr;
  63. struct clk *hclk;
  64. struct clk *mclk;
  65. struct completion done;
  66. const u8 *tx_buf;
  67. u8 *rx_buf;
  68. int len;
  69. };
  70. static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg)
  71. {
  72. return readl(sspi->base_addr + reg);
  73. }
  74. static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value)
  75. {
  76. writel(value, sspi->base_addr + reg);
  77. }
  78. static inline u32 sun4i_spi_get_tx_fifo_count(struct sun4i_spi *sspi)
  79. {
  80. u32 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
  81. reg >>= SUN4I_FIFO_STA_TF_CNT_BITS;
  82. return reg & SUN4I_FIFO_STA_TF_CNT_MASK;
  83. }
  84. static inline void sun4i_spi_enable_interrupt(struct sun4i_spi *sspi, u32 mask)
  85. {
  86. u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
  87. reg |= mask;
  88. sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
  89. }
  90. static inline void sun4i_spi_disable_interrupt(struct sun4i_spi *sspi, u32 mask)
  91. {
  92. u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
  93. reg &= ~mask;
  94. sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
  95. }
  96. static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
  97. {
  98. u32 reg, cnt;
  99. u8 byte;
  100. /* See how much data is available */
  101. reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
  102. reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
  103. cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;
  104. if (len > cnt)
  105. len = cnt;
  106. while (len--) {
  107. byte = readb(sspi->base_addr + SUN4I_RXDATA_REG);
  108. if (sspi->rx_buf)
  109. *sspi->rx_buf++ = byte;
  110. }
  111. }
  112. static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
  113. {
  114. u32 cnt;
  115. u8 byte;
  116. /* See how much data we can fit */
  117. cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi);
  118. len = min3(len, (int)cnt, sspi->len);
  119. while (len--) {
  120. byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
  121. writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG);
  122. sspi->len--;
  123. }
  124. }
  125. static void sun4i_spi_set_cs(struct spi_device *spi, bool enable)
  126. {
  127. struct sun4i_spi *sspi = spi_master_get_devdata(spi->master);
  128. u32 reg;
  129. reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
  130. reg &= ~SUN4I_CTL_CS_MASK;
  131. reg |= SUN4I_CTL_CS(spi->chip_select);
  132. /* We want to control the chip select manually */
  133. reg |= SUN4I_CTL_CS_MANUAL;
  134. if (enable)
  135. reg |= SUN4I_CTL_CS_LEVEL;
  136. else
  137. reg &= ~SUN4I_CTL_CS_LEVEL;
  138. /*
  139. * Even though this looks irrelevant since we are supposed to
  140. * be controlling the chip select manually, this bit also
  141. * controls the levels of the chip select for inactive
  142. * devices.
  143. *
  144. * If we don't set it, the chip select level will go low by
  145. * default when the device is idle, which is not really
  146. * expected in the common case where the chip select is active
  147. * low.
  148. */
  149. if (spi->mode & SPI_CS_HIGH)
  150. reg &= ~SUN4I_CTL_CS_ACTIVE_LOW;
  151. else
  152. reg |= SUN4I_CTL_CS_ACTIVE_LOW;
  153. sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
  154. }
  155. static size_t sun4i_spi_max_transfer_size(struct spi_device *spi)
  156. {
  157. return SUN4I_MAX_XFER_SIZE - 1;
  158. }
  159. static int sun4i_spi_transfer_one(struct spi_master *master,
  160. struct spi_device *spi,
  161. struct spi_transfer *tfr)
  162. {
  163. struct sun4i_spi *sspi = spi_master_get_devdata(master);
  164. unsigned int mclk_rate, div, timeout;
  165. unsigned int start, end, tx_time;
  166. unsigned int tx_len = 0;
  167. int ret = 0;
  168. u32 reg;
  169. /* We don't support transfer larger than the FIFO */
  170. if (tfr->len > SUN4I_MAX_XFER_SIZE)
  171. return -EMSGSIZE;
  172. if (tfr->tx_buf && tfr->len >= SUN4I_MAX_XFER_SIZE)
  173. return -EMSGSIZE;
  174. reinit_completion(&sspi->done);
  175. sspi->tx_buf = tfr->tx_buf;
  176. sspi->rx_buf = tfr->rx_buf;
  177. sspi->len = tfr->len;
  178. /* Clear pending interrupts */
  179. sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0);
  180. reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
  181. /* Reset FIFOs */
  182. sun4i_spi_write(sspi, SUN4I_CTL_REG,
  183. reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST);
  184. /*
  185. * Setup the transfer control register: Chip Select,
  186. * polarities, etc.
  187. */
  188. if (spi->mode & SPI_CPOL)
  189. reg |= SUN4I_CTL_CPOL;
  190. else
  191. reg &= ~SUN4I_CTL_CPOL;
  192. if (spi->mode & SPI_CPHA)
  193. reg |= SUN4I_CTL_CPHA;
  194. else
  195. reg &= ~SUN4I_CTL_CPHA;
  196. if (spi->mode & SPI_LSB_FIRST)
  197. reg |= SUN4I_CTL_LMTF;
  198. else
  199. reg &= ~SUN4I_CTL_LMTF;
  200. /*
  201. * If it's a TX only transfer, we don't want to fill the RX
  202. * FIFO with bogus data
  203. */
  204. if (sspi->rx_buf)
  205. reg &= ~SUN4I_CTL_DHB;
  206. else
  207. reg |= SUN4I_CTL_DHB;
  208. sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
  209. /* Ensure that we have a parent clock fast enough */
  210. mclk_rate = clk_get_rate(sspi->mclk);
  211. if (mclk_rate < (2 * tfr->speed_hz)) {
  212. clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
  213. mclk_rate = clk_get_rate(sspi->mclk);
  214. }
  215. /*
  216. * Setup clock divider.
  217. *
  218. * We have two choices there. Either we can use the clock
  219. * divide rate 1, which is calculated thanks to this formula:
  220. * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
  221. * Or we can use CDR2, which is calculated with the formula:
  222. * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
  223. * Wether we use the former or the latter is set through the
  224. * DRS bit.
  225. *
  226. * First try CDR2, and if we can't reach the expected
  227. * frequency, fall back to CDR1.
  228. */
  229. div = mclk_rate / (2 * tfr->speed_hz);
  230. if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
  231. if (div > 0)
  232. div--;
  233. reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
  234. } else {
  235. div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);
  236. reg = SUN4I_CLK_CTL_CDR1(div);
  237. }
  238. sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg);
  239. /* Setup the transfer now... */
  240. if (sspi->tx_buf)
  241. tx_len = tfr->len;
  242. /* Setup the counters */
  243. sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
  244. sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
  245. /*
  246. * Fill the TX FIFO
  247. * Filling the FIFO fully causes timeout for some reason
  248. * at least on spi2 on A10s
  249. */
  250. sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);
  251. /* Enable the interrupts */
  252. sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TC |
  253. SUN4I_INT_CTL_RF_F34);
  254. /* Only enable Tx FIFO interrupt if we really need it */
  255. if (tx_len > SUN4I_FIFO_DEPTH)
  256. sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
  257. /* Start the transfer */
  258. reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
  259. sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
  260. tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
  261. start = jiffies;
  262. timeout = wait_for_completion_timeout(&sspi->done,
  263. msecs_to_jiffies(tx_time));
  264. end = jiffies;
  265. if (!timeout) {
  266. dev_warn(&master->dev,
  267. "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
  268. dev_name(&spi->dev), tfr->len, tfr->speed_hz,
  269. jiffies_to_msecs(end - start), tx_time);
  270. ret = -ETIMEDOUT;
  271. goto out;
  272. }
  273. out:
  274. sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
  275. return ret;
  276. }
  277. static irqreturn_t sun4i_spi_handler(int irq, void *dev_id)
  278. {
  279. struct sun4i_spi *sspi = dev_id;
  280. u32 status = sun4i_spi_read(sspi, SUN4I_INT_STA_REG);
  281. /* Transfer complete */
  282. if (status & SUN4I_INT_CTL_TC) {
  283. sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC);
  284. sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
  285. complete(&sspi->done);
  286. return IRQ_HANDLED;
  287. }
  288. /* Receive FIFO 3/4 full */
  289. if (status & SUN4I_INT_CTL_RF_F34) {
  290. sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
  291. /* Only clear the interrupt _after_ draining the FIFO */
  292. sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_RF_F34);
  293. return IRQ_HANDLED;
  294. }
  295. /* Transmit FIFO 3/4 empty */
  296. if (status & SUN4I_INT_CTL_TF_E34) {
  297. sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
  298. if (!sspi->len)
  299. /* nothing left to transmit */
  300. sun4i_spi_disable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
  301. /* Only clear the interrupt _after_ re-seeding the FIFO */
  302. sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TF_E34);
  303. return IRQ_HANDLED;
  304. }
  305. return IRQ_NONE;
  306. }
  307. static int sun4i_spi_runtime_resume(struct device *dev)
  308. {
  309. struct spi_master *master = dev_get_drvdata(dev);
  310. struct sun4i_spi *sspi = spi_master_get_devdata(master);
  311. int ret;
  312. ret = clk_prepare_enable(sspi->hclk);
  313. if (ret) {
  314. dev_err(dev, "Couldn't enable AHB clock\n");
  315. goto out;
  316. }
  317. ret = clk_prepare_enable(sspi->mclk);
  318. if (ret) {
  319. dev_err(dev, "Couldn't enable module clock\n");
  320. goto err;
  321. }
  322. sun4i_spi_write(sspi, SUN4I_CTL_REG,
  323. SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP);
  324. return 0;
  325. err:
  326. clk_disable_unprepare(sspi->hclk);
  327. out:
  328. return ret;
  329. }
  330. static int sun4i_spi_runtime_suspend(struct device *dev)
  331. {
  332. struct spi_master *master = dev_get_drvdata(dev);
  333. struct sun4i_spi *sspi = spi_master_get_devdata(master);
  334. clk_disable_unprepare(sspi->mclk);
  335. clk_disable_unprepare(sspi->hclk);
  336. return 0;
  337. }
  338. static int sun4i_spi_probe(struct platform_device *pdev)
  339. {
  340. struct spi_master *master;
  341. struct sun4i_spi *sspi;
  342. int ret = 0, irq;
  343. master = spi_alloc_master(&pdev->dev, sizeof(struct sun4i_spi));
  344. if (!master) {
  345. dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
  346. return -ENOMEM;
  347. }
  348. platform_set_drvdata(pdev, master);
  349. sspi = spi_master_get_devdata(master);
  350. sspi->base_addr = devm_platform_ioremap_resource(pdev, 0);
  351. if (IS_ERR(sspi->base_addr)) {
  352. ret = PTR_ERR(sspi->base_addr);
  353. goto err_free_master;
  354. }
  355. irq = platform_get_irq(pdev, 0);
  356. if (irq < 0) {
  357. ret = -ENXIO;
  358. goto err_free_master;
  359. }
  360. ret = devm_request_irq(&pdev->dev, irq, sun4i_spi_handler,
  361. 0, "sun4i-spi", sspi);
  362. if (ret) {
  363. dev_err(&pdev->dev, "Cannot request IRQ\n");
  364. goto err_free_master;
  365. }
  366. sspi->master = master;
  367. master->max_speed_hz = 100 * 1000 * 1000;
  368. master->min_speed_hz = 3 * 1000;
  369. master->set_cs = sun4i_spi_set_cs;
  370. master->transfer_one = sun4i_spi_transfer_one;
  371. master->num_chipselect = 4;
  372. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
  373. master->bits_per_word_mask = SPI_BPW_MASK(8);
  374. master->dev.of_node = pdev->dev.of_node;
  375. master->auto_runtime_pm = true;
  376. master->max_transfer_size = sun4i_spi_max_transfer_size;
  377. sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
  378. if (IS_ERR(sspi->hclk)) {
  379. dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
  380. ret = PTR_ERR(sspi->hclk);
  381. goto err_free_master;
  382. }
  383. sspi->mclk = devm_clk_get(&pdev->dev, "mod");
  384. if (IS_ERR(sspi->mclk)) {
  385. dev_err(&pdev->dev, "Unable to acquire module clock\n");
  386. ret = PTR_ERR(sspi->mclk);
  387. goto err_free_master;
  388. }
  389. init_completion(&sspi->done);
  390. /*
  391. * This wake-up/shutdown pattern is to be able to have the
  392. * device woken up, even if runtime_pm is disabled
  393. */
  394. ret = sun4i_spi_runtime_resume(&pdev->dev);
  395. if (ret) {
  396. dev_err(&pdev->dev, "Couldn't resume the device\n");
  397. goto err_free_master;
  398. }
  399. pm_runtime_set_active(&pdev->dev);
  400. pm_runtime_enable(&pdev->dev);
  401. pm_runtime_idle(&pdev->dev);
  402. ret = devm_spi_register_master(&pdev->dev, master);
  403. if (ret) {
  404. dev_err(&pdev->dev, "cannot register SPI master\n");
  405. goto err_pm_disable;
  406. }
  407. return 0;
  408. err_pm_disable:
  409. pm_runtime_disable(&pdev->dev);
  410. sun4i_spi_runtime_suspend(&pdev->dev);
  411. err_free_master:
  412. spi_master_put(master);
  413. return ret;
  414. }
  415. static int sun4i_spi_remove(struct platform_device *pdev)
  416. {
  417. pm_runtime_force_suspend(&pdev->dev);
  418. return 0;
  419. }
  420. static const struct of_device_id sun4i_spi_match[] = {
  421. { .compatible = "allwinner,sun4i-a10-spi", },
  422. {}
  423. };
  424. MODULE_DEVICE_TABLE(of, sun4i_spi_match);
  425. static const struct dev_pm_ops sun4i_spi_pm_ops = {
  426. .runtime_resume = sun4i_spi_runtime_resume,
  427. .runtime_suspend = sun4i_spi_runtime_suspend,
  428. };
  429. static struct platform_driver sun4i_spi_driver = {
  430. .probe = sun4i_spi_probe,
  431. .remove = sun4i_spi_remove,
  432. .driver = {
  433. .name = "sun4i-spi",
  434. .of_match_table = sun4i_spi_match,
  435. .pm = &sun4i_spi_pm_ops,
  436. },
  437. };
  438. module_platform_driver(sun4i_spi_driver);
  439. MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
  440. MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
  441. MODULE_DESCRIPTION("Allwinner A1X/A20 SPI controller driver");
  442. MODULE_LICENSE("GPL");