spi-stm32.c 59 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // STMicroelectronics STM32 SPI Controller driver (master mode only)
  4. //
  5. // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  6. // Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
  7. #include <linux/debugfs.h>
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/dmaengine.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/iopoll.h>
  13. #include <linux/module.h>
  14. #include <linux/of_platform.h>
  15. #include <linux/pinctrl/consumer.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/reset.h>
  18. #include <linux/spi/spi.h>
  19. #define DRIVER_NAME "spi_stm32"
  20. /* STM32F4 SPI registers */
  21. #define STM32F4_SPI_CR1 0x00
  22. #define STM32F4_SPI_CR2 0x04
  23. #define STM32F4_SPI_SR 0x08
  24. #define STM32F4_SPI_DR 0x0C
  25. #define STM32F4_SPI_I2SCFGR 0x1C
  26. /* STM32F4_SPI_CR1 bit fields */
  27. #define STM32F4_SPI_CR1_CPHA BIT(0)
  28. #define STM32F4_SPI_CR1_CPOL BIT(1)
  29. #define STM32F4_SPI_CR1_MSTR BIT(2)
  30. #define STM32F4_SPI_CR1_BR_SHIFT 3
  31. #define STM32F4_SPI_CR1_BR GENMASK(5, 3)
  32. #define STM32F4_SPI_CR1_SPE BIT(6)
  33. #define STM32F4_SPI_CR1_LSBFRST BIT(7)
  34. #define STM32F4_SPI_CR1_SSI BIT(8)
  35. #define STM32F4_SPI_CR1_SSM BIT(9)
  36. #define STM32F4_SPI_CR1_RXONLY BIT(10)
  37. #define STM32F4_SPI_CR1_DFF BIT(11)
  38. #define STM32F4_SPI_CR1_CRCNEXT BIT(12)
  39. #define STM32F4_SPI_CR1_CRCEN BIT(13)
  40. #define STM32F4_SPI_CR1_BIDIOE BIT(14)
  41. #define STM32F4_SPI_CR1_BIDIMODE BIT(15)
  42. #define STM32F4_SPI_CR1_BR_MIN 0
  43. #define STM32F4_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3)
  44. /* STM32F4_SPI_CR2 bit fields */
  45. #define STM32F4_SPI_CR2_RXDMAEN BIT(0)
  46. #define STM32F4_SPI_CR2_TXDMAEN BIT(1)
  47. #define STM32F4_SPI_CR2_SSOE BIT(2)
  48. #define STM32F4_SPI_CR2_FRF BIT(4)
  49. #define STM32F4_SPI_CR2_ERRIE BIT(5)
  50. #define STM32F4_SPI_CR2_RXNEIE BIT(6)
  51. #define STM32F4_SPI_CR2_TXEIE BIT(7)
  52. /* STM32F4_SPI_SR bit fields */
  53. #define STM32F4_SPI_SR_RXNE BIT(0)
  54. #define STM32F4_SPI_SR_TXE BIT(1)
  55. #define STM32F4_SPI_SR_CHSIDE BIT(2)
  56. #define STM32F4_SPI_SR_UDR BIT(3)
  57. #define STM32F4_SPI_SR_CRCERR BIT(4)
  58. #define STM32F4_SPI_SR_MODF BIT(5)
  59. #define STM32F4_SPI_SR_OVR BIT(6)
  60. #define STM32F4_SPI_SR_BSY BIT(7)
  61. #define STM32F4_SPI_SR_FRE BIT(8)
  62. /* STM32F4_SPI_I2SCFGR bit fields */
  63. #define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11)
  64. /* STM32F4 SPI Baud Rate min/max divisor */
  65. #define STM32F4_SPI_BR_DIV_MIN (2 << STM32F4_SPI_CR1_BR_MIN)
  66. #define STM32F4_SPI_BR_DIV_MAX (2 << STM32F4_SPI_CR1_BR_MAX)
  67. /* STM32H7 SPI registers */
  68. #define STM32H7_SPI_CR1 0x00
  69. #define STM32H7_SPI_CR2 0x04
  70. #define STM32H7_SPI_CFG1 0x08
  71. #define STM32H7_SPI_CFG2 0x0C
  72. #define STM32H7_SPI_IER 0x10
  73. #define STM32H7_SPI_SR 0x14
  74. #define STM32H7_SPI_IFCR 0x18
  75. #define STM32H7_SPI_TXDR 0x20
  76. #define STM32H7_SPI_RXDR 0x30
  77. #define STM32H7_SPI_I2SCFGR 0x50
  78. /* STM32H7_SPI_CR1 bit fields */
  79. #define STM32H7_SPI_CR1_SPE BIT(0)
  80. #define STM32H7_SPI_CR1_MASRX BIT(8)
  81. #define STM32H7_SPI_CR1_CSTART BIT(9)
  82. #define STM32H7_SPI_CR1_CSUSP BIT(10)
  83. #define STM32H7_SPI_CR1_HDDIR BIT(11)
  84. #define STM32H7_SPI_CR1_SSI BIT(12)
  85. /* STM32H7_SPI_CR2 bit fields */
  86. #define STM32H7_SPI_CR2_TSIZE_SHIFT 0
  87. #define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
  88. /* STM32H7_SPI_CFG1 bit fields */
  89. #define STM32H7_SPI_CFG1_DSIZE_SHIFT 0
  90. #define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
  91. #define STM32H7_SPI_CFG1_FTHLV_SHIFT 5
  92. #define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
  93. #define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
  94. #define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
  95. #define STM32H7_SPI_CFG1_MBR_SHIFT 28
  96. #define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
  97. #define STM32H7_SPI_CFG1_MBR_MIN 0
  98. #define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
  99. /* STM32H7_SPI_CFG2 bit fields */
  100. #define STM32H7_SPI_CFG2_MIDI_SHIFT 4
  101. #define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
  102. #define STM32H7_SPI_CFG2_COMM_SHIFT 17
  103. #define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
  104. #define STM32H7_SPI_CFG2_SP_SHIFT 19
  105. #define STM32H7_SPI_CFG2_SP GENMASK(21, 19)
  106. #define STM32H7_SPI_CFG2_MASTER BIT(22)
  107. #define STM32H7_SPI_CFG2_LSBFRST BIT(23)
  108. #define STM32H7_SPI_CFG2_CPHA BIT(24)
  109. #define STM32H7_SPI_CFG2_CPOL BIT(25)
  110. #define STM32H7_SPI_CFG2_SSM BIT(26)
  111. #define STM32H7_SPI_CFG2_AFCNTR BIT(31)
  112. /* STM32H7_SPI_IER bit fields */
  113. #define STM32H7_SPI_IER_RXPIE BIT(0)
  114. #define STM32H7_SPI_IER_TXPIE BIT(1)
  115. #define STM32H7_SPI_IER_DXPIE BIT(2)
  116. #define STM32H7_SPI_IER_EOTIE BIT(3)
  117. #define STM32H7_SPI_IER_TXTFIE BIT(4)
  118. #define STM32H7_SPI_IER_OVRIE BIT(6)
  119. #define STM32H7_SPI_IER_MODFIE BIT(9)
  120. #define STM32H7_SPI_IER_ALL GENMASK(10, 0)
  121. /* STM32H7_SPI_SR bit fields */
  122. #define STM32H7_SPI_SR_RXP BIT(0)
  123. #define STM32H7_SPI_SR_TXP BIT(1)
  124. #define STM32H7_SPI_SR_EOT BIT(3)
  125. #define STM32H7_SPI_SR_OVR BIT(6)
  126. #define STM32H7_SPI_SR_MODF BIT(9)
  127. #define STM32H7_SPI_SR_SUSP BIT(11)
  128. #define STM32H7_SPI_SR_RXPLVL_SHIFT 13
  129. #define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
  130. #define STM32H7_SPI_SR_RXWNE BIT(15)
  131. /* STM32H7_SPI_IFCR bit fields */
  132. #define STM32H7_SPI_IFCR_ALL GENMASK(11, 3)
  133. /* STM32H7_SPI_I2SCFGR bit fields */
  134. #define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0)
  135. /* STM32H7 SPI Master Baud Rate min/max divisor */
  136. #define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN)
  137. #define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX)
  138. /* STM32H7 SPI Communication mode */
  139. #define STM32H7_SPI_FULL_DUPLEX 0
  140. #define STM32H7_SPI_SIMPLEX_TX 1
  141. #define STM32H7_SPI_SIMPLEX_RX 2
  142. #define STM32H7_SPI_HALF_DUPLEX 3
  143. /* SPI Communication type */
  144. #define SPI_FULL_DUPLEX 0
  145. #define SPI_SIMPLEX_TX 1
  146. #define SPI_SIMPLEX_RX 2
  147. #define SPI_3WIRE_TX 3
  148. #define SPI_3WIRE_RX 4
  149. #define SPI_1HZ_NS 1000000000
  150. /*
  151. * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
  152. * without fifo buffers.
  153. */
  154. #define SPI_DMA_MIN_BYTES 16
  155. /**
  156. * struct stm32_spi_reg - stm32 SPI register & bitfield desc
  157. * @reg: register offset
  158. * @mask: bitfield mask
  159. * @shift: left shift
  160. */
  161. struct stm32_spi_reg {
  162. int reg;
  163. int mask;
  164. int shift;
  165. };
  166. /**
  167. * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
  168. * @en: enable register and SPI enable bit
  169. * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
  170. * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
  171. * @cpol: clock polarity register and polarity bit
  172. * @cpha: clock phase register and phase bit
  173. * @lsb_first: LSB transmitted first register and bit
  174. * @br: baud rate register and bitfields
  175. * @rx: SPI RX data register
  176. * @tx: SPI TX data register
  177. */
  178. struct stm32_spi_regspec {
  179. const struct stm32_spi_reg en;
  180. const struct stm32_spi_reg dma_rx_en;
  181. const struct stm32_spi_reg dma_tx_en;
  182. const struct stm32_spi_reg cpol;
  183. const struct stm32_spi_reg cpha;
  184. const struct stm32_spi_reg lsb_first;
  185. const struct stm32_spi_reg br;
  186. const struct stm32_spi_reg rx;
  187. const struct stm32_spi_reg tx;
  188. };
  189. struct stm32_spi;
  190. /**
  191. * struct stm32_spi_cfg - stm32 compatible configuration data
  192. * @regs: registers descriptions
  193. * @get_fifo_size: routine to get fifo size
  194. * @get_bpw_mask: routine to get bits per word mask
  195. * @disable: routine to disable controller
  196. * @config: routine to configure controller as SPI Master
  197. * @set_bpw: routine to configure registers to for bits per word
  198. * @set_mode: routine to configure registers to desired mode
  199. * @set_data_idleness: optional routine to configure registers to desired idle
  200. * time between frames (if driver has this functionality)
  201. * @set_number_of_data: optional routine to configure registers to desired
  202. * number of data (if driver has this functionality)
  203. * @can_dma: routine to determine if the transfer is eligible for DMA use
  204. * @transfer_one_dma_start: routine to start transfer a single spi_transfer
  205. * using DMA
  206. * @dma_rx_cb: routine to call after DMA RX channel operation is complete
  207. * @dma_tx_cb: routine to call after DMA TX channel operation is complete
  208. * @transfer_one_irq: routine to configure interrupts for driver
  209. * @irq_handler_event: Interrupt handler for SPI controller events
  210. * @irq_handler_thread: thread of interrupt handler for SPI controller
  211. * @baud_rate_div_min: minimum baud rate divisor
  212. * @baud_rate_div_max: maximum baud rate divisor
  213. * @has_fifo: boolean to know if fifo is used for driver
  214. * @has_startbit: boolean to know if start bit is used to start transfer
  215. */
  216. struct stm32_spi_cfg {
  217. const struct stm32_spi_regspec *regs;
  218. int (*get_fifo_size)(struct stm32_spi *spi);
  219. int (*get_bpw_mask)(struct stm32_spi *spi);
  220. void (*disable)(struct stm32_spi *spi);
  221. int (*config)(struct stm32_spi *spi);
  222. void (*set_bpw)(struct stm32_spi *spi);
  223. int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
  224. void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
  225. int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
  226. void (*transfer_one_dma_start)(struct stm32_spi *spi);
  227. void (*dma_rx_cb)(void *data);
  228. void (*dma_tx_cb)(void *data);
  229. int (*transfer_one_irq)(struct stm32_spi *spi);
  230. irqreturn_t (*irq_handler_event)(int irq, void *dev_id);
  231. irqreturn_t (*irq_handler_thread)(int irq, void *dev_id);
  232. unsigned int baud_rate_div_min;
  233. unsigned int baud_rate_div_max;
  234. bool has_fifo;
  235. };
  236. /**
  237. * struct stm32_spi - private data of the SPI controller
  238. * @dev: driver model representation of the controller
  239. * @master: controller master interface
  240. * @cfg: compatible configuration data
  241. * @base: virtual memory area
  242. * @clk: hw kernel clock feeding the SPI clock generator
  243. * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
  244. * @rst: SPI controller reset line
  245. * @lock: prevent I/O concurrent access
  246. * @irq: SPI controller interrupt line
  247. * @fifo_size: size of the embedded fifo in bytes
  248. * @cur_midi: master inter-data idleness in ns
  249. * @cur_speed: speed configured in Hz
  250. * @cur_bpw: number of bits in a single SPI data frame
  251. * @cur_fthlv: fifo threshold level (data frames in a single data packet)
  252. * @cur_comm: SPI communication mode
  253. * @cur_xferlen: current transfer length in bytes
  254. * @cur_usedma: boolean to know if dma is used in current transfer
  255. * @tx_buf: data to be written, or NULL
  256. * @rx_buf: data to be read, or NULL
  257. * @tx_len: number of data to be written in bytes
  258. * @rx_len: number of data to be read in bytes
  259. * @dma_tx: dma channel for TX transfer
  260. * @dma_rx: dma channel for RX transfer
  261. * @phys_addr: SPI registers physical base address
  262. */
  263. struct stm32_spi {
  264. struct device *dev;
  265. struct spi_master *master;
  266. const struct stm32_spi_cfg *cfg;
  267. void __iomem *base;
  268. struct clk *clk;
  269. u32 clk_rate;
  270. struct reset_control *rst;
  271. spinlock_t lock; /* prevent I/O concurrent access */
  272. int irq;
  273. unsigned int fifo_size;
  274. unsigned int cur_midi;
  275. unsigned int cur_speed;
  276. unsigned int cur_bpw;
  277. unsigned int cur_fthlv;
  278. unsigned int cur_comm;
  279. unsigned int cur_xferlen;
  280. bool cur_usedma;
  281. const void *tx_buf;
  282. void *rx_buf;
  283. int tx_len;
  284. int rx_len;
  285. struct dma_chan *dma_tx;
  286. struct dma_chan *dma_rx;
  287. dma_addr_t phys_addr;
  288. };
  289. static const struct stm32_spi_regspec stm32f4_spi_regspec = {
  290. .en = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE },
  291. .dma_rx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN },
  292. .dma_tx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN },
  293. .cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL },
  294. .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA },
  295. .lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST },
  296. .br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT },
  297. .rx = { STM32F4_SPI_DR },
  298. .tx = { STM32F4_SPI_DR },
  299. };
  300. static const struct stm32_spi_regspec stm32h7_spi_regspec = {
  301. /* SPI data transfer is enabled but spi_ker_ck is idle.
  302. * CFG1 and CFG2 registers are write protected when SPE is enabled.
  303. */
  304. .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
  305. .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN },
  306. .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN },
  307. .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
  308. .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
  309. .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
  310. .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
  311. STM32H7_SPI_CFG1_MBR_SHIFT },
  312. .rx = { STM32H7_SPI_RXDR },
  313. .tx = { STM32H7_SPI_TXDR },
  314. };
  315. static inline void stm32_spi_set_bits(struct stm32_spi *spi,
  316. u32 offset, u32 bits)
  317. {
  318. writel_relaxed(readl_relaxed(spi->base + offset) | bits,
  319. spi->base + offset);
  320. }
  321. static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
  322. u32 offset, u32 bits)
  323. {
  324. writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
  325. spi->base + offset);
  326. }
  327. /**
  328. * stm32h7_spi_get_fifo_size - Return fifo size
  329. * @spi: pointer to the spi controller data structure
  330. */
  331. static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
  332. {
  333. unsigned long flags;
  334. u32 count = 0;
  335. spin_lock_irqsave(&spi->lock, flags);
  336. stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
  337. while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
  338. writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
  339. stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
  340. spin_unlock_irqrestore(&spi->lock, flags);
  341. dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
  342. return count;
  343. }
  344. /**
  345. * stm32f4_spi_get_bpw_mask - Return bits per word mask
  346. * @spi: pointer to the spi controller data structure
  347. */
  348. static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
  349. {
  350. dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
  351. return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
  352. }
  353. /**
  354. * stm32h7_spi_get_bpw_mask - Return bits per word mask
  355. * @spi: pointer to the spi controller data structure
  356. */
  357. static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
  358. {
  359. unsigned long flags;
  360. u32 cfg1, max_bpw;
  361. spin_lock_irqsave(&spi->lock, flags);
  362. /*
  363. * The most significant bit at DSIZE bit field is reserved when the
  364. * maximum data size of periperal instances is limited to 16-bit
  365. */
  366. stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
  367. cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
  368. max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >>
  369. STM32H7_SPI_CFG1_DSIZE_SHIFT;
  370. max_bpw += 1;
  371. spin_unlock_irqrestore(&spi->lock, flags);
  372. dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
  373. return SPI_BPW_RANGE_MASK(4, max_bpw);
  374. }
  375. /**
  376. * stm32_spi_prepare_mbr - Determine baud rate divisor value
  377. * @spi: pointer to the spi controller data structure
  378. * @speed_hz: requested speed
  379. * @min_div: minimum baud rate divisor
  380. * @max_div: maximum baud rate divisor
  381. *
  382. * Return baud rate divisor value in case of success or -EINVAL
  383. */
  384. static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
  385. u32 min_div, u32 max_div)
  386. {
  387. u32 div, mbrdiv;
  388. /* Ensure spi->clk_rate is even */
  389. div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz);
  390. /*
  391. * SPI framework set xfer->speed_hz to master->max_speed_hz if
  392. * xfer->speed_hz is greater than master->max_speed_hz, and it returns
  393. * an error when xfer->speed_hz is lower than master->min_speed_hz, so
  394. * no need to check it there.
  395. * However, we need to ensure the following calculations.
  396. */
  397. if ((div < min_div) || (div > max_div))
  398. return -EINVAL;
  399. /* Determine the first power of 2 greater than or equal to div */
  400. if (div & (div - 1))
  401. mbrdiv = fls(div);
  402. else
  403. mbrdiv = fls(div) - 1;
  404. spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
  405. return mbrdiv - 1;
  406. }
  407. /**
  408. * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
  409. * @spi: pointer to the spi controller data structure
  410. * @xfer_len: length of the message to be transferred
  411. */
  412. static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
  413. {
  414. u32 fthlv, half_fifo, packet;
  415. /* data packet should not exceed 1/2 of fifo space */
  416. half_fifo = (spi->fifo_size / 2);
  417. /* data_packet should not exceed transfer length */
  418. if (half_fifo > xfer_len)
  419. packet = xfer_len;
  420. else
  421. packet = half_fifo;
  422. if (spi->cur_bpw <= 8)
  423. fthlv = packet;
  424. else if (spi->cur_bpw <= 16)
  425. fthlv = packet / 2;
  426. else
  427. fthlv = packet / 4;
  428. /* align packet size with data registers access */
  429. if (spi->cur_bpw > 8)
  430. fthlv += (fthlv % 2) ? 1 : 0;
  431. else
  432. fthlv += (fthlv % 4) ? (4 - (fthlv % 4)) : 0;
  433. if (!fthlv)
  434. fthlv = 1;
  435. return fthlv;
  436. }
  437. /**
  438. * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
  439. * @spi: pointer to the spi controller data structure
  440. *
  441. * Read from tx_buf depends on remaining bytes to avoid to read beyond
  442. * tx_buf end.
  443. */
  444. static void stm32f4_spi_write_tx(struct stm32_spi *spi)
  445. {
  446. if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
  447. STM32F4_SPI_SR_TXE)) {
  448. u32 offs = spi->cur_xferlen - spi->tx_len;
  449. if (spi->cur_bpw == 16) {
  450. const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
  451. writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR);
  452. spi->tx_len -= sizeof(u16);
  453. } else {
  454. const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
  455. writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR);
  456. spi->tx_len -= sizeof(u8);
  457. }
  458. }
  459. dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
  460. }
  461. /**
  462. * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
  463. * @spi: pointer to the spi controller data structure
  464. *
  465. * Read from tx_buf depends on remaining bytes to avoid to read beyond
  466. * tx_buf end.
  467. */
  468. static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
  469. {
  470. while ((spi->tx_len > 0) &&
  471. (readl_relaxed(spi->base + STM32H7_SPI_SR) &
  472. STM32H7_SPI_SR_TXP)) {
  473. u32 offs = spi->cur_xferlen - spi->tx_len;
  474. if (spi->tx_len >= sizeof(u32)) {
  475. const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
  476. writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
  477. spi->tx_len -= sizeof(u32);
  478. } else if (spi->tx_len >= sizeof(u16)) {
  479. const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
  480. writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
  481. spi->tx_len -= sizeof(u16);
  482. } else {
  483. const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
  484. writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
  485. spi->tx_len -= sizeof(u8);
  486. }
  487. }
  488. dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
  489. }
  490. /**
  491. * stm32f4_spi_read_rx - Read bytes from Receive Data Register
  492. * @spi: pointer to the spi controller data structure
  493. *
  494. * Write in rx_buf depends on remaining bytes to avoid to write beyond
  495. * rx_buf end.
  496. */
  497. static void stm32f4_spi_read_rx(struct stm32_spi *spi)
  498. {
  499. if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
  500. STM32F4_SPI_SR_RXNE)) {
  501. u32 offs = spi->cur_xferlen - spi->rx_len;
  502. if (spi->cur_bpw == 16) {
  503. u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
  504. *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR);
  505. spi->rx_len -= sizeof(u16);
  506. } else {
  507. u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
  508. *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR);
  509. spi->rx_len -= sizeof(u8);
  510. }
  511. }
  512. dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
  513. }
  514. /**
  515. * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
  516. * @spi: pointer to the spi controller data structure
  517. * @flush: boolean indicating that FIFO should be flushed
  518. *
  519. * Write in rx_buf depends on remaining bytes to avoid to write beyond
  520. * rx_buf end.
  521. */
  522. static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
  523. {
  524. u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
  525. u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
  526. STM32H7_SPI_SR_RXPLVL_SHIFT;
  527. while ((spi->rx_len > 0) &&
  528. ((sr & STM32H7_SPI_SR_RXP) ||
  529. (flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
  530. u32 offs = spi->cur_xferlen - spi->rx_len;
  531. if ((spi->rx_len >= sizeof(u32)) ||
  532. (flush && (sr & STM32H7_SPI_SR_RXWNE))) {
  533. u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
  534. *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
  535. spi->rx_len -= sizeof(u32);
  536. } else if ((spi->rx_len >= sizeof(u16)) ||
  537. (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) {
  538. u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
  539. *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
  540. spi->rx_len -= sizeof(u16);
  541. } else {
  542. u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
  543. *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
  544. spi->rx_len -= sizeof(u8);
  545. }
  546. sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
  547. rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
  548. STM32H7_SPI_SR_RXPLVL_SHIFT;
  549. }
  550. dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
  551. flush ? "(flush)" : "", spi->rx_len);
  552. }
  553. /**
  554. * stm32_spi_enable - Enable SPI controller
  555. * @spi: pointer to the spi controller data structure
  556. */
  557. static void stm32_spi_enable(struct stm32_spi *spi)
  558. {
  559. dev_dbg(spi->dev, "enable controller\n");
  560. stm32_spi_set_bits(spi, spi->cfg->regs->en.reg,
  561. spi->cfg->regs->en.mask);
  562. }
  563. /**
  564. * stm32f4_spi_disable - Disable SPI controller
  565. * @spi: pointer to the spi controller data structure
  566. */
  567. static void stm32f4_spi_disable(struct stm32_spi *spi)
  568. {
  569. unsigned long flags;
  570. u32 sr;
  571. dev_dbg(spi->dev, "disable controller\n");
  572. spin_lock_irqsave(&spi->lock, flags);
  573. if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) &
  574. STM32F4_SPI_CR1_SPE)) {
  575. spin_unlock_irqrestore(&spi->lock, flags);
  576. return;
  577. }
  578. /* Disable interrupts */
  579. stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE |
  580. STM32F4_SPI_CR2_RXNEIE |
  581. STM32F4_SPI_CR2_ERRIE);
  582. /* Wait until BSY = 0 */
  583. if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR,
  584. sr, !(sr & STM32F4_SPI_SR_BSY),
  585. 10, 100000) < 0) {
  586. dev_warn(spi->dev, "disabling condition timeout\n");
  587. }
  588. if (spi->cur_usedma && spi->dma_tx)
  589. dmaengine_terminate_all(spi->dma_tx);
  590. if (spi->cur_usedma && spi->dma_rx)
  591. dmaengine_terminate_all(spi->dma_rx);
  592. stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
  593. stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN |
  594. STM32F4_SPI_CR2_RXDMAEN);
  595. /* Sequence to clear OVR flag */
  596. readl_relaxed(spi->base + STM32F4_SPI_DR);
  597. readl_relaxed(spi->base + STM32F4_SPI_SR);
  598. spin_unlock_irqrestore(&spi->lock, flags);
  599. }
  600. /**
  601. * stm32h7_spi_disable - Disable SPI controller
  602. * @spi: pointer to the spi controller data structure
  603. *
  604. * RX-Fifo is flushed when SPI controller is disabled. To prevent any data
  605. * loss, use stm32h7_spi_read_rxfifo(flush) to read the remaining bytes in
  606. * RX-Fifo.
  607. * Normally, if TSIZE has been configured, we should relax the hardware at the
  608. * reception of the EOT interrupt. But in case of error, EOT will not be
  609. * raised. So the subsystem unprepare_message call allows us to properly
  610. * complete the transfer from an hardware point of view.
  611. */
  612. static void stm32h7_spi_disable(struct stm32_spi *spi)
  613. {
  614. unsigned long flags;
  615. u32 cr1, sr;
  616. dev_dbg(spi->dev, "disable controller\n");
  617. spin_lock_irqsave(&spi->lock, flags);
  618. cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
  619. if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
  620. spin_unlock_irqrestore(&spi->lock, flags);
  621. return;
  622. }
  623. /* Wait on EOT or suspend the flow */
  624. if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR,
  625. sr, !(sr & STM32H7_SPI_SR_EOT),
  626. 10, 100000) < 0) {
  627. if (cr1 & STM32H7_SPI_CR1_CSTART) {
  628. writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP,
  629. spi->base + STM32H7_SPI_CR1);
  630. if (readl_relaxed_poll_timeout_atomic(
  631. spi->base + STM32H7_SPI_SR,
  632. sr, !(sr & STM32H7_SPI_SR_SUSP),
  633. 10, 100000) < 0)
  634. dev_warn(spi->dev,
  635. "Suspend request timeout\n");
  636. }
  637. }
  638. if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0))
  639. stm32h7_spi_read_rxfifo(spi, true);
  640. if (spi->cur_usedma && spi->dma_tx)
  641. dmaengine_terminate_all(spi->dma_tx);
  642. if (spi->cur_usedma && spi->dma_rx)
  643. dmaengine_terminate_all(spi->dma_rx);
  644. stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
  645. stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
  646. STM32H7_SPI_CFG1_RXDMAEN);
  647. /* Disable interrupts and clear status flags */
  648. writel_relaxed(0, spi->base + STM32H7_SPI_IER);
  649. writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
  650. spin_unlock_irqrestore(&spi->lock, flags);
  651. }
  652. /**
  653. * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
  654. * @master: controller master interface
  655. * @spi_dev: pointer to the spi device
  656. * @transfer: pointer to spi transfer
  657. *
  658. * If driver has fifo and the current transfer size is greater than fifo size,
  659. * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes.
  660. */
  661. static bool stm32_spi_can_dma(struct spi_master *master,
  662. struct spi_device *spi_dev,
  663. struct spi_transfer *transfer)
  664. {
  665. unsigned int dma_size;
  666. struct stm32_spi *spi = spi_master_get_devdata(master);
  667. if (spi->cfg->has_fifo)
  668. dma_size = spi->fifo_size;
  669. else
  670. dma_size = SPI_DMA_MIN_BYTES;
  671. dev_dbg(spi->dev, "%s: %s\n", __func__,
  672. (transfer->len > dma_size) ? "true" : "false");
  673. return (transfer->len > dma_size);
  674. }
  675. /**
  676. * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
  677. * @irq: interrupt line
  678. * @dev_id: SPI controller master interface
  679. */
  680. static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
  681. {
  682. struct spi_master *master = dev_id;
  683. struct stm32_spi *spi = spi_master_get_devdata(master);
  684. u32 sr, mask = 0;
  685. bool end = false;
  686. spin_lock(&spi->lock);
  687. sr = readl_relaxed(spi->base + STM32F4_SPI_SR);
  688. /*
  689. * BSY flag is not handled in interrupt but it is normal behavior when
  690. * this flag is set.
  691. */
  692. sr &= ~STM32F4_SPI_SR_BSY;
  693. if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX ||
  694. spi->cur_comm == SPI_3WIRE_TX)) {
  695. /* OVR flag shouldn't be handled for TX only mode */
  696. sr &= ~STM32F4_SPI_SR_OVR | STM32F4_SPI_SR_RXNE;
  697. mask |= STM32F4_SPI_SR_TXE;
  698. }
  699. if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX ||
  700. spi->cur_comm == SPI_SIMPLEX_RX ||
  701. spi->cur_comm == SPI_3WIRE_RX)) {
  702. /* TXE flag is set and is handled when RXNE flag occurs */
  703. sr &= ~STM32F4_SPI_SR_TXE;
  704. mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR;
  705. }
  706. if (!(sr & mask)) {
  707. dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
  708. spin_unlock(&spi->lock);
  709. return IRQ_NONE;
  710. }
  711. if (sr & STM32F4_SPI_SR_OVR) {
  712. dev_warn(spi->dev, "Overrun: received value discarded\n");
  713. /* Sequence to clear OVR flag */
  714. readl_relaxed(spi->base + STM32F4_SPI_DR);
  715. readl_relaxed(spi->base + STM32F4_SPI_SR);
  716. /*
  717. * If overrun is detected, it means that something went wrong,
  718. * so stop the current transfer. Transfer can wait for next
  719. * RXNE but DR is already read and end never happens.
  720. */
  721. end = true;
  722. goto end_irq;
  723. }
  724. if (sr & STM32F4_SPI_SR_TXE) {
  725. if (spi->tx_buf)
  726. stm32f4_spi_write_tx(spi);
  727. if (spi->tx_len == 0)
  728. end = true;
  729. }
  730. if (sr & STM32F4_SPI_SR_RXNE) {
  731. stm32f4_spi_read_rx(spi);
  732. if (spi->rx_len == 0)
  733. end = true;
  734. else if (spi->tx_buf)/* Load data for discontinuous mode */
  735. stm32f4_spi_write_tx(spi);
  736. }
  737. end_irq:
  738. if (end) {
  739. /* Immediately disable interrupts to do not generate new one */
  740. stm32_spi_clr_bits(spi, STM32F4_SPI_CR2,
  741. STM32F4_SPI_CR2_TXEIE |
  742. STM32F4_SPI_CR2_RXNEIE |
  743. STM32F4_SPI_CR2_ERRIE);
  744. spin_unlock(&spi->lock);
  745. return IRQ_WAKE_THREAD;
  746. }
  747. spin_unlock(&spi->lock);
  748. return IRQ_HANDLED;
  749. }
  750. /**
  751. * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
  752. * @irq: interrupt line
  753. * @dev_id: SPI controller master interface
  754. */
  755. static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id)
  756. {
  757. struct spi_master *master = dev_id;
  758. struct stm32_spi *spi = spi_master_get_devdata(master);
  759. spi_finalize_current_transfer(master);
  760. stm32f4_spi_disable(spi);
  761. return IRQ_HANDLED;
  762. }
  763. /**
  764. * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
  765. * @irq: interrupt line
  766. * @dev_id: SPI controller master interface
  767. */
  768. static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
  769. {
  770. struct spi_master *master = dev_id;
  771. struct stm32_spi *spi = spi_master_get_devdata(master);
  772. u32 sr, ier, mask;
  773. unsigned long flags;
  774. bool end = false;
  775. spin_lock_irqsave(&spi->lock, flags);
  776. sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
  777. ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
  778. mask = ier;
  779. /*
  780. * EOTIE enables irq from EOT, SUSP and TXC events. We need to set
  781. * SUSP to acknowledge it later. TXC is automatically cleared
  782. */
  783. mask |= STM32H7_SPI_SR_SUSP;
  784. /*
  785. * DXPIE is set in Full-Duplex, one IT will be raised if TXP and RXP
  786. * are set. So in case of Full-Duplex, need to poll TXP and RXP event.
  787. */
  788. if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma)
  789. mask |= STM32H7_SPI_SR_TXP | STM32H7_SPI_SR_RXP;
  790. if (!(sr & mask)) {
  791. dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
  792. sr, ier);
  793. spin_unlock_irqrestore(&spi->lock, flags);
  794. return IRQ_NONE;
  795. }
  796. if (sr & STM32H7_SPI_SR_SUSP) {
  797. static DEFINE_RATELIMIT_STATE(rs,
  798. DEFAULT_RATELIMIT_INTERVAL * 10,
  799. 1);
  800. if (__ratelimit(&rs))
  801. dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
  802. if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
  803. stm32h7_spi_read_rxfifo(spi, false);
  804. /*
  805. * If communication is suspended while using DMA, it means
  806. * that something went wrong, so stop the current transfer
  807. */
  808. if (spi->cur_usedma)
  809. end = true;
  810. }
  811. if (sr & STM32H7_SPI_SR_MODF) {
  812. dev_warn(spi->dev, "Mode fault: transfer aborted\n");
  813. end = true;
  814. }
  815. if (sr & STM32H7_SPI_SR_OVR) {
  816. dev_err(spi->dev, "Overrun: RX data lost\n");
  817. end = true;
  818. }
  819. if (sr & STM32H7_SPI_SR_EOT) {
  820. if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
  821. stm32h7_spi_read_rxfifo(spi, true);
  822. end = true;
  823. }
  824. if (sr & STM32H7_SPI_SR_TXP)
  825. if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
  826. stm32h7_spi_write_txfifo(spi);
  827. if (sr & STM32H7_SPI_SR_RXP)
  828. if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
  829. stm32h7_spi_read_rxfifo(spi, false);
  830. writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR);
  831. spin_unlock_irqrestore(&spi->lock, flags);
  832. if (end) {
  833. stm32h7_spi_disable(spi);
  834. spi_finalize_current_transfer(master);
  835. }
  836. return IRQ_HANDLED;
  837. }
  838. /**
  839. * stm32_spi_prepare_msg - set up the controller to transfer a single message
  840. * @master: controller master interface
  841. * @msg: pointer to spi message
  842. */
  843. static int stm32_spi_prepare_msg(struct spi_master *master,
  844. struct spi_message *msg)
  845. {
  846. struct stm32_spi *spi = spi_master_get_devdata(master);
  847. struct spi_device *spi_dev = msg->spi;
  848. struct device_node *np = spi_dev->dev.of_node;
  849. unsigned long flags;
  850. u32 clrb = 0, setb = 0;
  851. /* SPI slave device may need time between data frames */
  852. spi->cur_midi = 0;
  853. if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
  854. dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
  855. if (spi_dev->mode & SPI_CPOL)
  856. setb |= spi->cfg->regs->cpol.mask;
  857. else
  858. clrb |= spi->cfg->regs->cpol.mask;
  859. if (spi_dev->mode & SPI_CPHA)
  860. setb |= spi->cfg->regs->cpha.mask;
  861. else
  862. clrb |= spi->cfg->regs->cpha.mask;
  863. if (spi_dev->mode & SPI_LSB_FIRST)
  864. setb |= spi->cfg->regs->lsb_first.mask;
  865. else
  866. clrb |= spi->cfg->regs->lsb_first.mask;
  867. dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
  868. spi_dev->mode & SPI_CPOL,
  869. spi_dev->mode & SPI_CPHA,
  870. spi_dev->mode & SPI_LSB_FIRST,
  871. spi_dev->mode & SPI_CS_HIGH);
  872. spin_lock_irqsave(&spi->lock, flags);
  873. /* CPOL, CPHA and LSB FIRST bits have common register */
  874. if (clrb || setb)
  875. writel_relaxed(
  876. (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) &
  877. ~clrb) | setb,
  878. spi->base + spi->cfg->regs->cpol.reg);
  879. spin_unlock_irqrestore(&spi->lock, flags);
  880. return 0;
  881. }
  882. /**
  883. * stm32f4_spi_dma_tx_cb - dma callback
  884. * @data: pointer to the spi controller data structure
  885. *
  886. * DMA callback is called when the transfer is complete for DMA TX channel.
  887. */
  888. static void stm32f4_spi_dma_tx_cb(void *data)
  889. {
  890. struct stm32_spi *spi = data;
  891. if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
  892. spi_finalize_current_transfer(spi->master);
  893. stm32f4_spi_disable(spi);
  894. }
  895. }
  896. /**
  897. * stm32f4_spi_dma_rx_cb - dma callback
  898. * @data: pointer to the spi controller data structure
  899. *
  900. * DMA callback is called when the transfer is complete for DMA RX channel.
  901. */
  902. static void stm32f4_spi_dma_rx_cb(void *data)
  903. {
  904. struct stm32_spi *spi = data;
  905. spi_finalize_current_transfer(spi->master);
  906. stm32f4_spi_disable(spi);
  907. }
  908. /**
  909. * stm32h7_spi_dma_cb - dma callback
  910. * @data: pointer to the spi controller data structure
  911. *
  912. * DMA callback is called when the transfer is complete or when an error
  913. * occurs. If the transfer is complete, EOT flag is raised.
  914. */
  915. static void stm32h7_spi_dma_cb(void *data)
  916. {
  917. struct stm32_spi *spi = data;
  918. unsigned long flags;
  919. u32 sr;
  920. spin_lock_irqsave(&spi->lock, flags);
  921. sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
  922. spin_unlock_irqrestore(&spi->lock, flags);
  923. if (!(sr & STM32H7_SPI_SR_EOT))
  924. dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr);
  925. /* Now wait for EOT, or SUSP or OVR in case of error */
  926. }
  927. /**
  928. * stm32_spi_dma_config - configure dma slave channel depending on current
  929. * transfer bits_per_word.
  930. * @spi: pointer to the spi controller data structure
  931. * @dma_conf: pointer to the dma_slave_config structure
  932. * @dir: direction of the dma transfer
  933. */
  934. static void stm32_spi_dma_config(struct stm32_spi *spi,
  935. struct dma_slave_config *dma_conf,
  936. enum dma_transfer_direction dir)
  937. {
  938. enum dma_slave_buswidth buswidth;
  939. u32 maxburst;
  940. if (spi->cur_bpw <= 8)
  941. buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
  942. else if (spi->cur_bpw <= 16)
  943. buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
  944. else
  945. buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
  946. if (spi->cfg->has_fifo) {
  947. /* Valid for DMA Half or Full Fifo threshold */
  948. if (spi->cur_fthlv == 2)
  949. maxburst = 1;
  950. else
  951. maxburst = spi->cur_fthlv;
  952. } else {
  953. maxburst = 1;
  954. }
  955. memset(dma_conf, 0, sizeof(struct dma_slave_config));
  956. dma_conf->direction = dir;
  957. if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
  958. dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg;
  959. dma_conf->src_addr_width = buswidth;
  960. dma_conf->src_maxburst = maxburst;
  961. dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
  962. buswidth, maxburst);
  963. } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
  964. dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg;
  965. dma_conf->dst_addr_width = buswidth;
  966. dma_conf->dst_maxburst = maxburst;
  967. dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
  968. buswidth, maxburst);
  969. }
  970. }
  971. /**
  972. * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using
  973. * interrupts
  974. * @spi: pointer to the spi controller data structure
  975. *
  976. * It must returns 0 if the transfer is finished or 1 if the transfer is still
  977. * in progress.
  978. */
  979. static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi)
  980. {
  981. unsigned long flags;
  982. u32 cr2 = 0;
  983. /* Enable the interrupts relative to the current communication mode */
  984. if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
  985. cr2 |= STM32F4_SPI_CR2_TXEIE;
  986. } else if (spi->cur_comm == SPI_FULL_DUPLEX ||
  987. spi->cur_comm == SPI_SIMPLEX_RX ||
  988. spi->cur_comm == SPI_3WIRE_RX) {
  989. /* In transmit-only mode, the OVR flag is set in the SR register
  990. * since the received data are never read. Therefore set OVR
  991. * interrupt only when rx buffer is available.
  992. */
  993. cr2 |= STM32F4_SPI_CR2_RXNEIE | STM32F4_SPI_CR2_ERRIE;
  994. } else {
  995. return -EINVAL;
  996. }
  997. spin_lock_irqsave(&spi->lock, flags);
  998. stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2);
  999. stm32_spi_enable(spi);
  1000. /* starting data transfer when buffer is loaded */
  1001. if (spi->tx_buf)
  1002. stm32f4_spi_write_tx(spi);
  1003. spin_unlock_irqrestore(&spi->lock, flags);
  1004. return 1;
  1005. }
  1006. /**
  1007. * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
  1008. * interrupts
  1009. * @spi: pointer to the spi controller data structure
  1010. *
  1011. * It must returns 0 if the transfer is finished or 1 if the transfer is still
  1012. * in progress.
  1013. */
  1014. static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
  1015. {
  1016. unsigned long flags;
  1017. u32 ier = 0;
  1018. /* Enable the interrupts relative to the current communication mode */
  1019. if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
  1020. ier |= STM32H7_SPI_IER_DXPIE;
  1021. else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
  1022. ier |= STM32H7_SPI_IER_TXPIE;
  1023. else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
  1024. ier |= STM32H7_SPI_IER_RXPIE;
  1025. /* Enable the interrupts relative to the end of transfer */
  1026. ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
  1027. STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
  1028. spin_lock_irqsave(&spi->lock, flags);
  1029. stm32_spi_enable(spi);
  1030. /* Be sure to have data in fifo before starting data transfer */
  1031. if (spi->tx_buf)
  1032. stm32h7_spi_write_txfifo(spi);
  1033. stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
  1034. writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
  1035. spin_unlock_irqrestore(&spi->lock, flags);
  1036. return 1;
  1037. }
  1038. /**
  1039. * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
  1040. * transfer using DMA
  1041. * @spi: pointer to the spi controller data structure
  1042. */
  1043. static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi)
  1044. {
  1045. /* In DMA mode end of transfer is handled by DMA TX or RX callback. */
  1046. if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX ||
  1047. spi->cur_comm == SPI_FULL_DUPLEX) {
  1048. /*
  1049. * In transmit-only mode, the OVR flag is set in the SR register
  1050. * since the received data are never read. Therefore set OVR
  1051. * interrupt only when rx buffer is available.
  1052. */
  1053. stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE);
  1054. }
  1055. stm32_spi_enable(spi);
  1056. }
  1057. /**
  1058. * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
  1059. * transfer using DMA
  1060. * @spi: pointer to the spi controller data structure
  1061. */
  1062. static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
  1063. {
  1064. /* Enable the interrupts relative to the end of transfer */
  1065. stm32_spi_set_bits(spi, STM32H7_SPI_IER, STM32H7_SPI_IER_EOTIE |
  1066. STM32H7_SPI_IER_TXTFIE |
  1067. STM32H7_SPI_IER_OVRIE |
  1068. STM32H7_SPI_IER_MODFIE);
  1069. stm32_spi_enable(spi);
  1070. stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
  1071. }
  1072. /**
  1073. * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
  1074. * @spi: pointer to the spi controller data structure
  1075. * @xfer: pointer to the spi_transfer structure
  1076. *
  1077. * It must returns 0 if the transfer is finished or 1 if the transfer is still
  1078. * in progress.
  1079. */
  1080. static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
  1081. struct spi_transfer *xfer)
  1082. {
  1083. struct dma_slave_config tx_dma_conf, rx_dma_conf;
  1084. struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
  1085. unsigned long flags;
  1086. spin_lock_irqsave(&spi->lock, flags);
  1087. rx_dma_desc = NULL;
  1088. if (spi->rx_buf && spi->dma_rx) {
  1089. stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
  1090. dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
  1091. /* Enable Rx DMA request */
  1092. stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
  1093. spi->cfg->regs->dma_rx_en.mask);
  1094. rx_dma_desc = dmaengine_prep_slave_sg(
  1095. spi->dma_rx, xfer->rx_sg.sgl,
  1096. xfer->rx_sg.nents,
  1097. rx_dma_conf.direction,
  1098. DMA_PREP_INTERRUPT);
  1099. }
  1100. tx_dma_desc = NULL;
  1101. if (spi->tx_buf && spi->dma_tx) {
  1102. stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
  1103. dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
  1104. tx_dma_desc = dmaengine_prep_slave_sg(
  1105. spi->dma_tx, xfer->tx_sg.sgl,
  1106. xfer->tx_sg.nents,
  1107. tx_dma_conf.direction,
  1108. DMA_PREP_INTERRUPT);
  1109. }
  1110. if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) ||
  1111. (spi->rx_buf && spi->dma_rx && !rx_dma_desc))
  1112. goto dma_desc_error;
  1113. if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc))
  1114. goto dma_desc_error;
  1115. if (rx_dma_desc) {
  1116. rx_dma_desc->callback = spi->cfg->dma_rx_cb;
  1117. rx_dma_desc->callback_param = spi;
  1118. if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
  1119. dev_err(spi->dev, "Rx DMA submit failed\n");
  1120. goto dma_desc_error;
  1121. }
  1122. /* Enable Rx DMA channel */
  1123. dma_async_issue_pending(spi->dma_rx);
  1124. }
  1125. if (tx_dma_desc) {
  1126. if (spi->cur_comm == SPI_SIMPLEX_TX ||
  1127. spi->cur_comm == SPI_3WIRE_TX) {
  1128. tx_dma_desc->callback = spi->cfg->dma_tx_cb;
  1129. tx_dma_desc->callback_param = spi;
  1130. }
  1131. if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
  1132. dev_err(spi->dev, "Tx DMA submit failed\n");
  1133. goto dma_submit_error;
  1134. }
  1135. /* Enable Tx DMA channel */
  1136. dma_async_issue_pending(spi->dma_tx);
  1137. /* Enable Tx DMA request */
  1138. stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg,
  1139. spi->cfg->regs->dma_tx_en.mask);
  1140. }
  1141. spi->cfg->transfer_one_dma_start(spi);
  1142. spin_unlock_irqrestore(&spi->lock, flags);
  1143. return 1;
  1144. dma_submit_error:
  1145. if (spi->dma_rx)
  1146. dmaengine_terminate_all(spi->dma_rx);
  1147. dma_desc_error:
  1148. stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,
  1149. spi->cfg->regs->dma_rx_en.mask);
  1150. spin_unlock_irqrestore(&spi->lock, flags);
  1151. dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
  1152. spi->cur_usedma = false;
  1153. return spi->cfg->transfer_one_irq(spi);
  1154. }
  1155. /**
  1156. * stm32f4_spi_set_bpw - Configure bits per word
  1157. * @spi: pointer to the spi controller data structure
  1158. */
  1159. static void stm32f4_spi_set_bpw(struct stm32_spi *spi)
  1160. {
  1161. if (spi->cur_bpw == 16)
  1162. stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
  1163. else
  1164. stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
  1165. }
  1166. /**
  1167. * stm32h7_spi_set_bpw - configure bits per word
  1168. * @spi: pointer to the spi controller data structure
  1169. */
  1170. static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
  1171. {
  1172. u32 bpw, fthlv;
  1173. u32 cfg1_clrb = 0, cfg1_setb = 0;
  1174. bpw = spi->cur_bpw - 1;
  1175. cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
  1176. cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
  1177. STM32H7_SPI_CFG1_DSIZE;
  1178. spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
  1179. fthlv = spi->cur_fthlv - 1;
  1180. cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
  1181. cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
  1182. STM32H7_SPI_CFG1_FTHLV;
  1183. writel_relaxed(
  1184. (readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
  1185. ~cfg1_clrb) | cfg1_setb,
  1186. spi->base + STM32H7_SPI_CFG1);
  1187. }
  1188. /**
  1189. * stm32_spi_set_mbr - Configure baud rate divisor in master mode
  1190. * @spi: pointer to the spi controller data structure
  1191. * @mbrdiv: baud rate divisor value
  1192. */
  1193. static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
  1194. {
  1195. u32 clrb = 0, setb = 0;
  1196. clrb |= spi->cfg->regs->br.mask;
  1197. setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) &
  1198. spi->cfg->regs->br.mask;
  1199. writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
  1200. ~clrb) | setb,
  1201. spi->base + spi->cfg->regs->br.reg);
  1202. }
  1203. /**
  1204. * stm32_spi_communication_type - return transfer communication type
  1205. * @spi_dev: pointer to the spi device
  1206. * @transfer: pointer to spi transfer
  1207. */
  1208. static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev,
  1209. struct spi_transfer *transfer)
  1210. {
  1211. unsigned int type = SPI_FULL_DUPLEX;
  1212. if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
  1213. /*
  1214. * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
  1215. * is forbidden and unvalidated by SPI subsystem so depending
  1216. * on the valid buffer, we can determine the direction of the
  1217. * transfer.
  1218. */
  1219. if (!transfer->tx_buf)
  1220. type = SPI_3WIRE_RX;
  1221. else
  1222. type = SPI_3WIRE_TX;
  1223. } else {
  1224. if (!transfer->tx_buf)
  1225. type = SPI_SIMPLEX_RX;
  1226. else if (!transfer->rx_buf)
  1227. type = SPI_SIMPLEX_TX;
  1228. }
  1229. return type;
  1230. }
  1231. /**
  1232. * stm32f4_spi_set_mode - configure communication mode
  1233. * @spi: pointer to the spi controller data structure
  1234. * @comm_type: type of communication to configure
  1235. */
  1236. static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
  1237. {
  1238. if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) {
  1239. stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
  1240. STM32F4_SPI_CR1_BIDIMODE |
  1241. STM32F4_SPI_CR1_BIDIOE);
  1242. } else if (comm_type == SPI_FULL_DUPLEX ||
  1243. comm_type == SPI_SIMPLEX_RX) {
  1244. stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
  1245. STM32F4_SPI_CR1_BIDIMODE |
  1246. STM32F4_SPI_CR1_BIDIOE);
  1247. } else if (comm_type == SPI_3WIRE_RX) {
  1248. stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
  1249. STM32F4_SPI_CR1_BIDIMODE);
  1250. stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
  1251. STM32F4_SPI_CR1_BIDIOE);
  1252. } else {
  1253. return -EINVAL;
  1254. }
  1255. return 0;
  1256. }
  1257. /**
  1258. * stm32h7_spi_set_mode - configure communication mode
  1259. * @spi: pointer to the spi controller data structure
  1260. * @comm_type: type of communication to configure
  1261. */
  1262. static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
  1263. {
  1264. u32 mode;
  1265. u32 cfg2_clrb = 0, cfg2_setb = 0;
  1266. if (comm_type == SPI_3WIRE_RX) {
  1267. mode = STM32H7_SPI_HALF_DUPLEX;
  1268. stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
  1269. } else if (comm_type == SPI_3WIRE_TX) {
  1270. mode = STM32H7_SPI_HALF_DUPLEX;
  1271. stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
  1272. } else if (comm_type == SPI_SIMPLEX_RX) {
  1273. mode = STM32H7_SPI_SIMPLEX_RX;
  1274. } else if (comm_type == SPI_SIMPLEX_TX) {
  1275. mode = STM32H7_SPI_SIMPLEX_TX;
  1276. } else {
  1277. mode = STM32H7_SPI_FULL_DUPLEX;
  1278. }
  1279. cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
  1280. cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) &
  1281. STM32H7_SPI_CFG2_COMM;
  1282. writel_relaxed(
  1283. (readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
  1284. ~cfg2_clrb) | cfg2_setb,
  1285. spi->base + STM32H7_SPI_CFG2);
  1286. return 0;
  1287. }
  1288. /**
  1289. * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
  1290. * consecutive data frames in master mode
  1291. * @spi: pointer to the spi controller data structure
  1292. * @len: transfer len
  1293. */
  1294. static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
  1295. {
  1296. u32 cfg2_clrb = 0, cfg2_setb = 0;
  1297. cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
  1298. if ((len > 1) && (spi->cur_midi > 0)) {
  1299. u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
  1300. u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
  1301. (u32)STM32H7_SPI_CFG2_MIDI >>
  1302. STM32H7_SPI_CFG2_MIDI_SHIFT);
  1303. dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
  1304. sck_period_ns, midi, midi * sck_period_ns);
  1305. cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) &
  1306. STM32H7_SPI_CFG2_MIDI;
  1307. }
  1308. writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
  1309. ~cfg2_clrb) | cfg2_setb,
  1310. spi->base + STM32H7_SPI_CFG2);
  1311. }
  1312. /**
  1313. * stm32h7_spi_number_of_data - configure number of data at current transfer
  1314. * @spi: pointer to the spi controller data structure
  1315. * @nb_words: transfer length (in words)
  1316. */
  1317. static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
  1318. {
  1319. u32 cr2_clrb = 0, cr2_setb = 0;
  1320. if (nb_words <= (STM32H7_SPI_CR2_TSIZE >>
  1321. STM32H7_SPI_CR2_TSIZE_SHIFT)) {
  1322. cr2_clrb |= STM32H7_SPI_CR2_TSIZE;
  1323. cr2_setb = nb_words << STM32H7_SPI_CR2_TSIZE_SHIFT;
  1324. writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) &
  1325. ~cr2_clrb) | cr2_setb,
  1326. spi->base + STM32H7_SPI_CR2);
  1327. } else {
  1328. return -EMSGSIZE;
  1329. }
  1330. return 0;
  1331. }
  1332. /**
  1333. * stm32_spi_transfer_one_setup - common setup to transfer a single
  1334. * spi_transfer either using DMA or
  1335. * interrupts.
  1336. * @spi: pointer to the spi controller data structure
  1337. * @spi_dev: pointer to the spi device
  1338. * @transfer: pointer to spi transfer
  1339. */
  1340. static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
  1341. struct spi_device *spi_dev,
  1342. struct spi_transfer *transfer)
  1343. {
  1344. unsigned long flags;
  1345. unsigned int comm_type;
  1346. int nb_words, ret = 0;
  1347. int mbr;
  1348. spin_lock_irqsave(&spi->lock, flags);
  1349. spi->cur_xferlen = transfer->len;
  1350. spi->cur_bpw = transfer->bits_per_word;
  1351. spi->cfg->set_bpw(spi);
  1352. /* Update spi->cur_speed with real clock speed */
  1353. mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
  1354. spi->cfg->baud_rate_div_min,
  1355. spi->cfg->baud_rate_div_max);
  1356. if (mbr < 0) {
  1357. ret = mbr;
  1358. goto out;
  1359. }
  1360. transfer->speed_hz = spi->cur_speed;
  1361. stm32_spi_set_mbr(spi, mbr);
  1362. comm_type = stm32_spi_communication_type(spi_dev, transfer);
  1363. ret = spi->cfg->set_mode(spi, comm_type);
  1364. if (ret < 0)
  1365. goto out;
  1366. spi->cur_comm = comm_type;
  1367. if (spi->cfg->set_data_idleness)
  1368. spi->cfg->set_data_idleness(spi, transfer->len);
  1369. if (spi->cur_bpw <= 8)
  1370. nb_words = transfer->len;
  1371. else if (spi->cur_bpw <= 16)
  1372. nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
  1373. else
  1374. nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
  1375. if (spi->cfg->set_number_of_data) {
  1376. ret = spi->cfg->set_number_of_data(spi, nb_words);
  1377. if (ret < 0)
  1378. goto out;
  1379. }
  1380. dev_dbg(spi->dev, "transfer communication mode set to %d\n",
  1381. spi->cur_comm);
  1382. dev_dbg(spi->dev,
  1383. "data frame of %d-bit, data packet of %d data frames\n",
  1384. spi->cur_bpw, spi->cur_fthlv);
  1385. dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
  1386. dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
  1387. spi->cur_xferlen, nb_words);
  1388. dev_dbg(spi->dev, "dma %s\n",
  1389. (spi->cur_usedma) ? "enabled" : "disabled");
  1390. out:
  1391. spin_unlock_irqrestore(&spi->lock, flags);
  1392. return ret;
  1393. }
  1394. /**
  1395. * stm32_spi_transfer_one - transfer a single spi_transfer
  1396. * @master: controller master interface
  1397. * @spi_dev: pointer to the spi device
  1398. * @transfer: pointer to spi transfer
  1399. *
  1400. * It must return 0 if the transfer is finished or 1 if the transfer is still
  1401. * in progress.
  1402. */
  1403. static int stm32_spi_transfer_one(struct spi_master *master,
  1404. struct spi_device *spi_dev,
  1405. struct spi_transfer *transfer)
  1406. {
  1407. struct stm32_spi *spi = spi_master_get_devdata(master);
  1408. int ret;
  1409. /* Don't do anything on 0 bytes transfers */
  1410. if (transfer->len == 0)
  1411. return 0;
  1412. spi->tx_buf = transfer->tx_buf;
  1413. spi->rx_buf = transfer->rx_buf;
  1414. spi->tx_len = spi->tx_buf ? transfer->len : 0;
  1415. spi->rx_len = spi->rx_buf ? transfer->len : 0;
  1416. spi->cur_usedma = (master->can_dma &&
  1417. master->can_dma(master, spi_dev, transfer));
  1418. ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
  1419. if (ret) {
  1420. dev_err(spi->dev, "SPI transfer setup failed\n");
  1421. return ret;
  1422. }
  1423. if (spi->cur_usedma)
  1424. return stm32_spi_transfer_one_dma(spi, transfer);
  1425. else
  1426. return spi->cfg->transfer_one_irq(spi);
  1427. }
  1428. /**
  1429. * stm32_spi_unprepare_msg - relax the hardware
  1430. * @master: controller master interface
  1431. * @msg: pointer to the spi message
  1432. */
  1433. static int stm32_spi_unprepare_msg(struct spi_master *master,
  1434. struct spi_message *msg)
  1435. {
  1436. struct stm32_spi *spi = spi_master_get_devdata(master);
  1437. spi->cfg->disable(spi);
  1438. return 0;
  1439. }
  1440. /**
  1441. * stm32f4_spi_config - Configure SPI controller as SPI master
  1442. * @spi: pointer to the spi controller data structure
  1443. */
  1444. static int stm32f4_spi_config(struct stm32_spi *spi)
  1445. {
  1446. unsigned long flags;
  1447. spin_lock_irqsave(&spi->lock, flags);
  1448. /* Ensure I2SMOD bit is kept cleared */
  1449. stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR,
  1450. STM32F4_SPI_I2SCFGR_I2SMOD);
  1451. /*
  1452. * - SS input value high
  1453. * - transmitter half duplex direction
  1454. * - Set the master mode (default Motorola mode)
  1455. * - Consider 1 master/n slaves configuration and
  1456. * SS input value is determined by the SSI bit
  1457. */
  1458. stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI |
  1459. STM32F4_SPI_CR1_BIDIOE |
  1460. STM32F4_SPI_CR1_MSTR |
  1461. STM32F4_SPI_CR1_SSM);
  1462. spin_unlock_irqrestore(&spi->lock, flags);
  1463. return 0;
  1464. }
  1465. /**
  1466. * stm32h7_spi_config - Configure SPI controller as SPI master
  1467. * @spi: pointer to the spi controller data structure
  1468. */
  1469. static int stm32h7_spi_config(struct stm32_spi *spi)
  1470. {
  1471. unsigned long flags;
  1472. spin_lock_irqsave(&spi->lock, flags);
  1473. /* Ensure I2SMOD bit is kept cleared */
  1474. stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
  1475. STM32H7_SPI_I2SCFGR_I2SMOD);
  1476. /*
  1477. * - SS input value high
  1478. * - transmitter half duplex direction
  1479. * - automatic communication suspend when RX-Fifo is full
  1480. */
  1481. stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI |
  1482. STM32H7_SPI_CR1_HDDIR |
  1483. STM32H7_SPI_CR1_MASRX);
  1484. /*
  1485. * - Set the master mode (default Motorola mode)
  1486. * - Consider 1 master/n slaves configuration and
  1487. * SS input value is determined by the SSI bit
  1488. * - keep control of all associated GPIOs
  1489. */
  1490. stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER |
  1491. STM32H7_SPI_CFG2_SSM |
  1492. STM32H7_SPI_CFG2_AFCNTR);
  1493. spin_unlock_irqrestore(&spi->lock, flags);
  1494. return 0;
  1495. }
  1496. static const struct stm32_spi_cfg stm32f4_spi_cfg = {
  1497. .regs = &stm32f4_spi_regspec,
  1498. .get_bpw_mask = stm32f4_spi_get_bpw_mask,
  1499. .disable = stm32f4_spi_disable,
  1500. .config = stm32f4_spi_config,
  1501. .set_bpw = stm32f4_spi_set_bpw,
  1502. .set_mode = stm32f4_spi_set_mode,
  1503. .transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start,
  1504. .dma_tx_cb = stm32f4_spi_dma_tx_cb,
  1505. .dma_rx_cb = stm32f4_spi_dma_rx_cb,
  1506. .transfer_one_irq = stm32f4_spi_transfer_one_irq,
  1507. .irq_handler_event = stm32f4_spi_irq_event,
  1508. .irq_handler_thread = stm32f4_spi_irq_thread,
  1509. .baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN,
  1510. .baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX,
  1511. .has_fifo = false,
  1512. };
  1513. static const struct stm32_spi_cfg stm32h7_spi_cfg = {
  1514. .regs = &stm32h7_spi_regspec,
  1515. .get_fifo_size = stm32h7_spi_get_fifo_size,
  1516. .get_bpw_mask = stm32h7_spi_get_bpw_mask,
  1517. .disable = stm32h7_spi_disable,
  1518. .config = stm32h7_spi_config,
  1519. .set_bpw = stm32h7_spi_set_bpw,
  1520. .set_mode = stm32h7_spi_set_mode,
  1521. .set_data_idleness = stm32h7_spi_data_idleness,
  1522. .set_number_of_data = stm32h7_spi_number_of_data,
  1523. .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
  1524. .dma_rx_cb = stm32h7_spi_dma_cb,
  1525. .dma_tx_cb = stm32h7_spi_dma_cb,
  1526. .transfer_one_irq = stm32h7_spi_transfer_one_irq,
  1527. .irq_handler_thread = stm32h7_spi_irq_thread,
  1528. .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
  1529. .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
  1530. .has_fifo = true,
  1531. };
  1532. static const struct of_device_id stm32_spi_of_match[] = {
  1533. { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
  1534. { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
  1535. {},
  1536. };
  1537. MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
  1538. static int stm32_spi_probe(struct platform_device *pdev)
  1539. {
  1540. struct spi_master *master;
  1541. struct stm32_spi *spi;
  1542. struct resource *res;
  1543. int ret;
  1544. master = devm_spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
  1545. if (!master) {
  1546. dev_err(&pdev->dev, "spi master allocation failed\n");
  1547. return -ENOMEM;
  1548. }
  1549. platform_set_drvdata(pdev, master);
  1550. spi = spi_master_get_devdata(master);
  1551. spi->dev = &pdev->dev;
  1552. spi->master = master;
  1553. spin_lock_init(&spi->lock);
  1554. spi->cfg = (const struct stm32_spi_cfg *)
  1555. of_match_device(pdev->dev.driver->of_match_table,
  1556. &pdev->dev)->data;
  1557. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1558. spi->base = devm_ioremap_resource(&pdev->dev, res);
  1559. if (IS_ERR(spi->base))
  1560. return PTR_ERR(spi->base);
  1561. spi->phys_addr = (dma_addr_t)res->start;
  1562. spi->irq = platform_get_irq(pdev, 0);
  1563. if (spi->irq <= 0)
  1564. return dev_err_probe(&pdev->dev, spi->irq,
  1565. "failed to get irq\n");
  1566. ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
  1567. spi->cfg->irq_handler_event,
  1568. spi->cfg->irq_handler_thread,
  1569. IRQF_ONESHOT, pdev->name, master);
  1570. if (ret) {
  1571. dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
  1572. ret);
  1573. return ret;
  1574. }
  1575. spi->clk = devm_clk_get(&pdev->dev, NULL);
  1576. if (IS_ERR(spi->clk)) {
  1577. ret = PTR_ERR(spi->clk);
  1578. dev_err(&pdev->dev, "clk get failed: %d\n", ret);
  1579. return ret;
  1580. }
  1581. ret = clk_prepare_enable(spi->clk);
  1582. if (ret) {
  1583. dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
  1584. return ret;
  1585. }
  1586. spi->clk_rate = clk_get_rate(spi->clk);
  1587. if (!spi->clk_rate) {
  1588. dev_err(&pdev->dev, "clk rate = 0\n");
  1589. ret = -EINVAL;
  1590. goto err_clk_disable;
  1591. }
  1592. spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
  1593. if (!IS_ERR(spi->rst)) {
  1594. reset_control_assert(spi->rst);
  1595. udelay(2);
  1596. reset_control_deassert(spi->rst);
  1597. }
  1598. if (spi->cfg->has_fifo)
  1599. spi->fifo_size = spi->cfg->get_fifo_size(spi);
  1600. ret = spi->cfg->config(spi);
  1601. if (ret) {
  1602. dev_err(&pdev->dev, "controller configuration failed: %d\n",
  1603. ret);
  1604. goto err_clk_disable;
  1605. }
  1606. master->dev.of_node = pdev->dev.of_node;
  1607. master->auto_runtime_pm = true;
  1608. master->bus_num = pdev->id;
  1609. master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
  1610. SPI_3WIRE;
  1611. master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi);
  1612. master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
  1613. master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
  1614. master->use_gpio_descriptors = true;
  1615. master->prepare_message = stm32_spi_prepare_msg;
  1616. master->transfer_one = stm32_spi_transfer_one;
  1617. master->unprepare_message = stm32_spi_unprepare_msg;
  1618. master->flags = SPI_MASTER_MUST_TX;
  1619. spi->dma_tx = dma_request_chan(spi->dev, "tx");
  1620. if (IS_ERR(spi->dma_tx)) {
  1621. ret = PTR_ERR(spi->dma_tx);
  1622. spi->dma_tx = NULL;
  1623. if (ret == -EPROBE_DEFER)
  1624. goto err_clk_disable;
  1625. dev_warn(&pdev->dev, "failed to request tx dma channel\n");
  1626. } else {
  1627. master->dma_tx = spi->dma_tx;
  1628. }
  1629. spi->dma_rx = dma_request_chan(spi->dev, "rx");
  1630. if (IS_ERR(spi->dma_rx)) {
  1631. ret = PTR_ERR(spi->dma_rx);
  1632. spi->dma_rx = NULL;
  1633. if (ret == -EPROBE_DEFER)
  1634. goto err_dma_release;
  1635. dev_warn(&pdev->dev, "failed to request rx dma channel\n");
  1636. } else {
  1637. master->dma_rx = spi->dma_rx;
  1638. }
  1639. if (spi->dma_tx || spi->dma_rx)
  1640. master->can_dma = stm32_spi_can_dma;
  1641. pm_runtime_set_active(&pdev->dev);
  1642. pm_runtime_get_noresume(&pdev->dev);
  1643. pm_runtime_enable(&pdev->dev);
  1644. ret = spi_register_master(master);
  1645. if (ret) {
  1646. dev_err(&pdev->dev, "spi master registration failed: %d\n",
  1647. ret);
  1648. goto err_pm_disable;
  1649. }
  1650. if (!master->cs_gpiods) {
  1651. dev_err(&pdev->dev, "no CS gpios available\n");
  1652. ret = -EINVAL;
  1653. goto err_pm_disable;
  1654. }
  1655. dev_info(&pdev->dev, "driver initialized\n");
  1656. return 0;
  1657. err_pm_disable:
  1658. pm_runtime_disable(&pdev->dev);
  1659. pm_runtime_put_noidle(&pdev->dev);
  1660. pm_runtime_set_suspended(&pdev->dev);
  1661. err_dma_release:
  1662. if (spi->dma_tx)
  1663. dma_release_channel(spi->dma_tx);
  1664. if (spi->dma_rx)
  1665. dma_release_channel(spi->dma_rx);
  1666. err_clk_disable:
  1667. clk_disable_unprepare(spi->clk);
  1668. return ret;
  1669. }
  1670. static int stm32_spi_remove(struct platform_device *pdev)
  1671. {
  1672. struct spi_master *master = platform_get_drvdata(pdev);
  1673. struct stm32_spi *spi = spi_master_get_devdata(master);
  1674. pm_runtime_get_sync(&pdev->dev);
  1675. spi_unregister_master(master);
  1676. spi->cfg->disable(spi);
  1677. pm_runtime_disable(&pdev->dev);
  1678. pm_runtime_put_noidle(&pdev->dev);
  1679. pm_runtime_set_suspended(&pdev->dev);
  1680. if (master->dma_tx)
  1681. dma_release_channel(master->dma_tx);
  1682. if (master->dma_rx)
  1683. dma_release_channel(master->dma_rx);
  1684. clk_disable_unprepare(spi->clk);
  1685. pinctrl_pm_select_sleep_state(&pdev->dev);
  1686. return 0;
  1687. }
  1688. #ifdef CONFIG_PM
  1689. static int stm32_spi_runtime_suspend(struct device *dev)
  1690. {
  1691. struct spi_master *master = dev_get_drvdata(dev);
  1692. struct stm32_spi *spi = spi_master_get_devdata(master);
  1693. clk_disable_unprepare(spi->clk);
  1694. return pinctrl_pm_select_sleep_state(dev);
  1695. }
  1696. static int stm32_spi_runtime_resume(struct device *dev)
  1697. {
  1698. struct spi_master *master = dev_get_drvdata(dev);
  1699. struct stm32_spi *spi = spi_master_get_devdata(master);
  1700. int ret;
  1701. ret = pinctrl_pm_select_default_state(dev);
  1702. if (ret)
  1703. return ret;
  1704. return clk_prepare_enable(spi->clk);
  1705. }
  1706. #endif
  1707. #ifdef CONFIG_PM_SLEEP
  1708. static int stm32_spi_suspend(struct device *dev)
  1709. {
  1710. struct spi_master *master = dev_get_drvdata(dev);
  1711. int ret;
  1712. ret = spi_master_suspend(master);
  1713. if (ret)
  1714. return ret;
  1715. return pm_runtime_force_suspend(dev);
  1716. }
  1717. static int stm32_spi_resume(struct device *dev)
  1718. {
  1719. struct spi_master *master = dev_get_drvdata(dev);
  1720. struct stm32_spi *spi = spi_master_get_devdata(master);
  1721. int ret;
  1722. ret = pm_runtime_force_resume(dev);
  1723. if (ret)
  1724. return ret;
  1725. ret = spi_master_resume(master);
  1726. if (ret) {
  1727. clk_disable_unprepare(spi->clk);
  1728. return ret;
  1729. }
  1730. ret = pm_runtime_get_sync(dev);
  1731. if (ret < 0) {
  1732. pm_runtime_put_noidle(dev);
  1733. dev_err(dev, "Unable to power device:%d\n", ret);
  1734. return ret;
  1735. }
  1736. spi->cfg->config(spi);
  1737. pm_runtime_mark_last_busy(dev);
  1738. pm_runtime_put_autosuspend(dev);
  1739. return 0;
  1740. }
  1741. #endif
  1742. static const struct dev_pm_ops stm32_spi_pm_ops = {
  1743. SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
  1744. SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend,
  1745. stm32_spi_runtime_resume, NULL)
  1746. };
  1747. static struct platform_driver stm32_spi_driver = {
  1748. .probe = stm32_spi_probe,
  1749. .remove = stm32_spi_remove,
  1750. .driver = {
  1751. .name = DRIVER_NAME,
  1752. .pm = &stm32_spi_pm_ops,
  1753. .of_match_table = stm32_spi_of_match,
  1754. },
  1755. };
  1756. module_platform_driver(stm32_spi_driver);
  1757. MODULE_ALIAS("platform:" DRIVER_NAME);
  1758. MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
  1759. MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
  1760. MODULE_LICENSE("GPL v2");