spi-stm32-qspi.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
  4. * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
  5. */
  6. #include <linux/bitfield.h>
  7. #include <linux/clk.h>
  8. #include <linux/dmaengine.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/errno.h>
  11. #include <linux/io.h>
  12. #include <linux/iopoll.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/module.h>
  15. #include <linux/mutex.h>
  16. #include <linux/of.h>
  17. #include <linux/of_device.h>
  18. #include <linux/pinctrl/consumer.h>
  19. #include <linux/pm_runtime.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/reset.h>
  22. #include <linux/sizes.h>
  23. #include <linux/spi/spi-mem.h>
  24. #define QSPI_CR 0x00
  25. #define CR_EN BIT(0)
  26. #define CR_ABORT BIT(1)
  27. #define CR_DMAEN BIT(2)
  28. #define CR_TCEN BIT(3)
  29. #define CR_SSHIFT BIT(4)
  30. #define CR_DFM BIT(6)
  31. #define CR_FSEL BIT(7)
  32. #define CR_FTHRES_SHIFT 8
  33. #define CR_TEIE BIT(16)
  34. #define CR_TCIE BIT(17)
  35. #define CR_FTIE BIT(18)
  36. #define CR_SMIE BIT(19)
  37. #define CR_TOIE BIT(20)
  38. #define CR_PRESC_MASK GENMASK(31, 24)
  39. #define QSPI_DCR 0x04
  40. #define DCR_FSIZE_MASK GENMASK(20, 16)
  41. #define QSPI_SR 0x08
  42. #define SR_TEF BIT(0)
  43. #define SR_TCF BIT(1)
  44. #define SR_FTF BIT(2)
  45. #define SR_SMF BIT(3)
  46. #define SR_TOF BIT(4)
  47. #define SR_BUSY BIT(5)
  48. #define SR_FLEVEL_MASK GENMASK(13, 8)
  49. #define QSPI_FCR 0x0c
  50. #define FCR_CTEF BIT(0)
  51. #define FCR_CTCF BIT(1)
  52. #define QSPI_DLR 0x10
  53. #define QSPI_CCR 0x14
  54. #define CCR_INST_MASK GENMASK(7, 0)
  55. #define CCR_IMODE_MASK GENMASK(9, 8)
  56. #define CCR_ADMODE_MASK GENMASK(11, 10)
  57. #define CCR_ADSIZE_MASK GENMASK(13, 12)
  58. #define CCR_DCYC_MASK GENMASK(22, 18)
  59. #define CCR_DMODE_MASK GENMASK(25, 24)
  60. #define CCR_FMODE_MASK GENMASK(27, 26)
  61. #define CCR_FMODE_INDW (0U << 26)
  62. #define CCR_FMODE_INDR (1U << 26)
  63. #define CCR_FMODE_APM (2U << 26)
  64. #define CCR_FMODE_MM (3U << 26)
  65. #define CCR_BUSWIDTH_0 0x0
  66. #define CCR_BUSWIDTH_1 0x1
  67. #define CCR_BUSWIDTH_2 0x2
  68. #define CCR_BUSWIDTH_4 0x3
  69. #define QSPI_AR 0x18
  70. #define QSPI_ABR 0x1c
  71. #define QSPI_DR 0x20
  72. #define QSPI_PSMKR 0x24
  73. #define QSPI_PSMAR 0x28
  74. #define QSPI_PIR 0x2c
  75. #define QSPI_LPTR 0x30
  76. #define STM32_QSPI_MAX_MMAP_SZ SZ_256M
  77. #define STM32_QSPI_MAX_NORCHIP 2
  78. #define STM32_FIFO_TIMEOUT_US 30000
  79. #define STM32_BUSY_TIMEOUT_US 100000
  80. #define STM32_ABT_TIMEOUT_US 100000
  81. #define STM32_COMP_TIMEOUT_MS 1000
  82. #define STM32_AUTOSUSPEND_DELAY -1
  83. struct stm32_qspi_flash {
  84. struct stm32_qspi *qspi;
  85. u32 cs;
  86. u32 presc;
  87. };
  88. struct stm32_qspi {
  89. struct device *dev;
  90. struct spi_controller *ctrl;
  91. phys_addr_t phys_base;
  92. void __iomem *io_base;
  93. void __iomem *mm_base;
  94. resource_size_t mm_size;
  95. struct clk *clk;
  96. u32 clk_rate;
  97. struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP];
  98. struct completion data_completion;
  99. u32 fmode;
  100. struct dma_chan *dma_chtx;
  101. struct dma_chan *dma_chrx;
  102. struct completion dma_completion;
  103. u32 cr_reg;
  104. u32 dcr_reg;
  105. /*
  106. * to protect device configuration, could be different between
  107. * 2 flash access (bk1, bk2)
  108. */
  109. struct mutex lock;
  110. };
  111. static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
  112. {
  113. struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
  114. u32 cr, sr;
  115. sr = readl_relaxed(qspi->io_base + QSPI_SR);
  116. if (sr & (SR_TEF | SR_TCF)) {
  117. /* disable irq */
  118. cr = readl_relaxed(qspi->io_base + QSPI_CR);
  119. cr &= ~CR_TCIE & ~CR_TEIE;
  120. writel_relaxed(cr, qspi->io_base + QSPI_CR);
  121. complete(&qspi->data_completion);
  122. }
  123. return IRQ_HANDLED;
  124. }
  125. static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
  126. {
  127. *val = readb_relaxed(addr);
  128. }
  129. static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
  130. {
  131. writeb_relaxed(*val, addr);
  132. }
  133. static int stm32_qspi_tx_poll(struct stm32_qspi *qspi,
  134. const struct spi_mem_op *op)
  135. {
  136. void (*tx_fifo)(u8 *val, void __iomem *addr);
  137. u32 len = op->data.nbytes, sr;
  138. u8 *buf;
  139. int ret;
  140. if (op->data.dir == SPI_MEM_DATA_IN) {
  141. tx_fifo = stm32_qspi_read_fifo;
  142. buf = op->data.buf.in;
  143. } else {
  144. tx_fifo = stm32_qspi_write_fifo;
  145. buf = (u8 *)op->data.buf.out;
  146. }
  147. while (len--) {
  148. ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR,
  149. sr, (sr & SR_FTF), 1,
  150. STM32_FIFO_TIMEOUT_US);
  151. if (ret) {
  152. dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n",
  153. len, sr);
  154. return ret;
  155. }
  156. tx_fifo(buf++, qspi->io_base + QSPI_DR);
  157. }
  158. return 0;
  159. }
  160. static int stm32_qspi_tx_mm(struct stm32_qspi *qspi,
  161. const struct spi_mem_op *op)
  162. {
  163. memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val,
  164. op->data.nbytes);
  165. return 0;
  166. }
  167. static void stm32_qspi_dma_callback(void *arg)
  168. {
  169. struct completion *dma_completion = arg;
  170. complete(dma_completion);
  171. }
  172. static int stm32_qspi_tx_dma(struct stm32_qspi *qspi,
  173. const struct spi_mem_op *op)
  174. {
  175. struct dma_async_tx_descriptor *desc;
  176. enum dma_transfer_direction dma_dir;
  177. struct dma_chan *dma_ch;
  178. struct sg_table sgt;
  179. dma_cookie_t cookie;
  180. u32 cr, t_out;
  181. int err;
  182. if (op->data.dir == SPI_MEM_DATA_IN) {
  183. dma_dir = DMA_DEV_TO_MEM;
  184. dma_ch = qspi->dma_chrx;
  185. } else {
  186. dma_dir = DMA_MEM_TO_DEV;
  187. dma_ch = qspi->dma_chtx;
  188. }
  189. /*
  190. * spi_map_buf return -EINVAL if the buffer is not DMA-able
  191. * (DMA-able: in vmalloc | kmap | virt_addr_valid)
  192. */
  193. err = spi_controller_dma_map_mem_op_data(qspi->ctrl, op, &sgt);
  194. if (err)
  195. return err;
  196. desc = dmaengine_prep_slave_sg(dma_ch, sgt.sgl, sgt.nents,
  197. dma_dir, DMA_PREP_INTERRUPT);
  198. if (!desc) {
  199. err = -ENOMEM;
  200. goto out_unmap;
  201. }
  202. cr = readl_relaxed(qspi->io_base + QSPI_CR);
  203. reinit_completion(&qspi->dma_completion);
  204. desc->callback = stm32_qspi_dma_callback;
  205. desc->callback_param = &qspi->dma_completion;
  206. cookie = dmaengine_submit(desc);
  207. err = dma_submit_error(cookie);
  208. if (err)
  209. goto out;
  210. dma_async_issue_pending(dma_ch);
  211. writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR);
  212. t_out = sgt.nents * STM32_COMP_TIMEOUT_MS;
  213. if (!wait_for_completion_timeout(&qspi->dma_completion,
  214. msecs_to_jiffies(t_out)))
  215. err = -ETIMEDOUT;
  216. if (err)
  217. dmaengine_terminate_all(dma_ch);
  218. out:
  219. writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR);
  220. out_unmap:
  221. spi_controller_dma_unmap_mem_op_data(qspi->ctrl, op, &sgt);
  222. return err;
  223. }
  224. static int stm32_qspi_tx(struct stm32_qspi *qspi, const struct spi_mem_op *op)
  225. {
  226. if (!op->data.nbytes)
  227. return 0;
  228. if (qspi->fmode == CCR_FMODE_MM)
  229. return stm32_qspi_tx_mm(qspi, op);
  230. else if ((op->data.dir == SPI_MEM_DATA_IN && qspi->dma_chrx) ||
  231. (op->data.dir == SPI_MEM_DATA_OUT && qspi->dma_chtx))
  232. if (!stm32_qspi_tx_dma(qspi, op))
  233. return 0;
  234. return stm32_qspi_tx_poll(qspi, op);
  235. }
  236. static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi)
  237. {
  238. u32 sr;
  239. return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr,
  240. !(sr & SR_BUSY), 1,
  241. STM32_BUSY_TIMEOUT_US);
  242. }
  243. static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi,
  244. const struct spi_mem_op *op)
  245. {
  246. u32 cr, sr;
  247. int err = 0;
  248. if (!op->data.nbytes)
  249. goto wait_nobusy;
  250. if (readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF)
  251. goto out;
  252. reinit_completion(&qspi->data_completion);
  253. cr = readl_relaxed(qspi->io_base + QSPI_CR);
  254. writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR);
  255. if (!wait_for_completion_timeout(&qspi->data_completion,
  256. msecs_to_jiffies(STM32_COMP_TIMEOUT_MS))) {
  257. err = -ETIMEDOUT;
  258. } else {
  259. sr = readl_relaxed(qspi->io_base + QSPI_SR);
  260. if (sr & SR_TEF)
  261. err = -EIO;
  262. }
  263. out:
  264. /* clear flags */
  265. writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR);
  266. wait_nobusy:
  267. if (!err)
  268. err = stm32_qspi_wait_nobusy(qspi);
  269. return err;
  270. }
  271. static int stm32_qspi_get_mode(struct stm32_qspi *qspi, u8 buswidth)
  272. {
  273. if (buswidth == 4)
  274. return CCR_BUSWIDTH_4;
  275. return buswidth;
  276. }
  277. static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
  278. {
  279. struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
  280. struct stm32_qspi_flash *flash = &qspi->flash[mem->spi->chip_select];
  281. u32 ccr, cr, addr_max;
  282. int timeout, err = 0;
  283. dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
  284. op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
  285. op->dummy.buswidth, op->data.buswidth,
  286. op->addr.val, op->data.nbytes);
  287. err = stm32_qspi_wait_nobusy(qspi);
  288. if (err)
  289. goto abort;
  290. addr_max = op->addr.val + op->data.nbytes + 1;
  291. if (op->data.dir == SPI_MEM_DATA_IN) {
  292. if (addr_max < qspi->mm_size &&
  293. op->addr.buswidth)
  294. qspi->fmode = CCR_FMODE_MM;
  295. else
  296. qspi->fmode = CCR_FMODE_INDR;
  297. } else {
  298. qspi->fmode = CCR_FMODE_INDW;
  299. }
  300. cr = readl_relaxed(qspi->io_base + QSPI_CR);
  301. cr &= ~CR_PRESC_MASK & ~CR_FSEL;
  302. cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc);
  303. cr |= FIELD_PREP(CR_FSEL, flash->cs);
  304. writel_relaxed(cr, qspi->io_base + QSPI_CR);
  305. if (op->data.nbytes)
  306. writel_relaxed(op->data.nbytes - 1,
  307. qspi->io_base + QSPI_DLR);
  308. else
  309. qspi->fmode = CCR_FMODE_INDW;
  310. ccr = qspi->fmode;
  311. ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode);
  312. ccr |= FIELD_PREP(CCR_IMODE_MASK,
  313. stm32_qspi_get_mode(qspi, op->cmd.buswidth));
  314. if (op->addr.nbytes) {
  315. ccr |= FIELD_PREP(CCR_ADMODE_MASK,
  316. stm32_qspi_get_mode(qspi, op->addr.buswidth));
  317. ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1);
  318. }
  319. if (op->dummy.buswidth && op->dummy.nbytes)
  320. ccr |= FIELD_PREP(CCR_DCYC_MASK,
  321. op->dummy.nbytes * 8 / op->dummy.buswidth);
  322. if (op->data.nbytes) {
  323. ccr |= FIELD_PREP(CCR_DMODE_MASK,
  324. stm32_qspi_get_mode(qspi, op->data.buswidth));
  325. }
  326. writel_relaxed(ccr, qspi->io_base + QSPI_CCR);
  327. if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM)
  328. writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR);
  329. err = stm32_qspi_tx(qspi, op);
  330. /*
  331. * Abort in:
  332. * -error case
  333. * -read memory map: prefetching must be stopped if we read the last
  334. * byte of device (device size - fifo size). like device size is not
  335. * knows, the prefetching is always stop.
  336. */
  337. if (err || qspi->fmode == CCR_FMODE_MM)
  338. goto abort;
  339. /* wait end of tx in indirect mode */
  340. err = stm32_qspi_wait_cmd(qspi, op);
  341. if (err)
  342. goto abort;
  343. return 0;
  344. abort:
  345. cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT;
  346. writel_relaxed(cr, qspi->io_base + QSPI_CR);
  347. /* wait clear of abort bit by hw */
  348. timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR,
  349. cr, !(cr & CR_ABORT), 1,
  350. STM32_ABT_TIMEOUT_US);
  351. writel_relaxed(FCR_CTCF, qspi->io_base + QSPI_FCR);
  352. if (err || timeout)
  353. dev_err(qspi->dev, "%s err:%d abort timeout:%d\n",
  354. __func__, err, timeout);
  355. return err;
  356. }
  357. static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
  358. {
  359. struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
  360. int ret;
  361. ret = pm_runtime_get_sync(qspi->dev);
  362. if (ret < 0) {
  363. pm_runtime_put_noidle(qspi->dev);
  364. return ret;
  365. }
  366. mutex_lock(&qspi->lock);
  367. ret = stm32_qspi_send(mem, op);
  368. mutex_unlock(&qspi->lock);
  369. pm_runtime_mark_last_busy(qspi->dev);
  370. pm_runtime_put_autosuspend(qspi->dev);
  371. return ret;
  372. }
  373. static int stm32_qspi_setup(struct spi_device *spi)
  374. {
  375. struct spi_controller *ctrl = spi->master;
  376. struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl);
  377. struct stm32_qspi_flash *flash;
  378. u32 presc;
  379. int ret;
  380. if (ctrl->busy)
  381. return -EBUSY;
  382. if (!spi->max_speed_hz)
  383. return -EINVAL;
  384. ret = pm_runtime_get_sync(qspi->dev);
  385. if (ret < 0) {
  386. pm_runtime_put_noidle(qspi->dev);
  387. return ret;
  388. }
  389. presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1;
  390. flash = &qspi->flash[spi->chip_select];
  391. flash->qspi = qspi;
  392. flash->cs = spi->chip_select;
  393. flash->presc = presc;
  394. mutex_lock(&qspi->lock);
  395. qspi->cr_reg = 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN;
  396. writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
  397. /* set dcr fsize to max address */
  398. qspi->dcr_reg = DCR_FSIZE_MASK;
  399. writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
  400. mutex_unlock(&qspi->lock);
  401. pm_runtime_mark_last_busy(qspi->dev);
  402. pm_runtime_put_autosuspend(qspi->dev);
  403. return 0;
  404. }
  405. static int stm32_qspi_dma_setup(struct stm32_qspi *qspi)
  406. {
  407. struct dma_slave_config dma_cfg;
  408. struct device *dev = qspi->dev;
  409. int ret = 0;
  410. memset(&dma_cfg, 0, sizeof(dma_cfg));
  411. dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  412. dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  413. dma_cfg.src_addr = qspi->phys_base + QSPI_DR;
  414. dma_cfg.dst_addr = qspi->phys_base + QSPI_DR;
  415. dma_cfg.src_maxburst = 4;
  416. dma_cfg.dst_maxburst = 4;
  417. qspi->dma_chrx = dma_request_chan(dev, "rx");
  418. if (IS_ERR(qspi->dma_chrx)) {
  419. ret = PTR_ERR(qspi->dma_chrx);
  420. qspi->dma_chrx = NULL;
  421. if (ret == -EPROBE_DEFER)
  422. goto out;
  423. } else {
  424. if (dmaengine_slave_config(qspi->dma_chrx, &dma_cfg)) {
  425. dev_err(dev, "dma rx config failed\n");
  426. dma_release_channel(qspi->dma_chrx);
  427. qspi->dma_chrx = NULL;
  428. }
  429. }
  430. qspi->dma_chtx = dma_request_chan(dev, "tx");
  431. if (IS_ERR(qspi->dma_chtx)) {
  432. ret = PTR_ERR(qspi->dma_chtx);
  433. qspi->dma_chtx = NULL;
  434. } else {
  435. if (dmaengine_slave_config(qspi->dma_chtx, &dma_cfg)) {
  436. dev_err(dev, "dma tx config failed\n");
  437. dma_release_channel(qspi->dma_chtx);
  438. qspi->dma_chtx = NULL;
  439. }
  440. }
  441. out:
  442. init_completion(&qspi->dma_completion);
  443. if (ret != -EPROBE_DEFER)
  444. ret = 0;
  445. return ret;
  446. }
  447. static void stm32_qspi_dma_free(struct stm32_qspi *qspi)
  448. {
  449. if (qspi->dma_chtx)
  450. dma_release_channel(qspi->dma_chtx);
  451. if (qspi->dma_chrx)
  452. dma_release_channel(qspi->dma_chrx);
  453. }
  454. /*
  455. * no special host constraint, so use default spi_mem_default_supports_op
  456. * to check supported mode.
  457. */
  458. static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
  459. .exec_op = stm32_qspi_exec_op,
  460. };
  461. static int stm32_qspi_probe(struct platform_device *pdev)
  462. {
  463. struct device *dev = &pdev->dev;
  464. struct spi_controller *ctrl;
  465. struct reset_control *rstc;
  466. struct stm32_qspi *qspi;
  467. struct resource *res;
  468. int ret, irq;
  469. ctrl = spi_alloc_master(dev, sizeof(*qspi));
  470. if (!ctrl)
  471. return -ENOMEM;
  472. qspi = spi_controller_get_devdata(ctrl);
  473. qspi->ctrl = ctrl;
  474. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
  475. qspi->io_base = devm_ioremap_resource(dev, res);
  476. if (IS_ERR(qspi->io_base)) {
  477. ret = PTR_ERR(qspi->io_base);
  478. goto err_master_put;
  479. }
  480. qspi->phys_base = res->start;
  481. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
  482. qspi->mm_base = devm_ioremap_resource(dev, res);
  483. if (IS_ERR(qspi->mm_base)) {
  484. ret = PTR_ERR(qspi->mm_base);
  485. goto err_master_put;
  486. }
  487. qspi->mm_size = resource_size(res);
  488. if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ) {
  489. ret = -EINVAL;
  490. goto err_master_put;
  491. }
  492. irq = platform_get_irq(pdev, 0);
  493. if (irq < 0) {
  494. ret = irq;
  495. goto err_master_put;
  496. }
  497. ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
  498. dev_name(dev), qspi);
  499. if (ret) {
  500. dev_err(dev, "failed to request irq\n");
  501. goto err_master_put;
  502. }
  503. init_completion(&qspi->data_completion);
  504. qspi->clk = devm_clk_get(dev, NULL);
  505. if (IS_ERR(qspi->clk)) {
  506. ret = PTR_ERR(qspi->clk);
  507. goto err_master_put;
  508. }
  509. qspi->clk_rate = clk_get_rate(qspi->clk);
  510. if (!qspi->clk_rate) {
  511. ret = -EINVAL;
  512. goto err_master_put;
  513. }
  514. ret = clk_prepare_enable(qspi->clk);
  515. if (ret) {
  516. dev_err(dev, "can not enable the clock\n");
  517. goto err_master_put;
  518. }
  519. rstc = devm_reset_control_get_exclusive(dev, NULL);
  520. if (IS_ERR(rstc)) {
  521. ret = PTR_ERR(rstc);
  522. if (ret == -EPROBE_DEFER)
  523. goto err_clk_disable;
  524. } else {
  525. reset_control_assert(rstc);
  526. udelay(2);
  527. reset_control_deassert(rstc);
  528. }
  529. qspi->dev = dev;
  530. platform_set_drvdata(pdev, qspi);
  531. ret = stm32_qspi_dma_setup(qspi);
  532. if (ret)
  533. goto err_dma_free;
  534. mutex_init(&qspi->lock);
  535. ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD
  536. | SPI_TX_DUAL | SPI_TX_QUAD;
  537. ctrl->setup = stm32_qspi_setup;
  538. ctrl->bus_num = -1;
  539. ctrl->mem_ops = &stm32_qspi_mem_ops;
  540. ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP;
  541. ctrl->dev.of_node = dev->of_node;
  542. pm_runtime_set_autosuspend_delay(dev, STM32_AUTOSUSPEND_DELAY);
  543. pm_runtime_use_autosuspend(dev);
  544. pm_runtime_set_active(dev);
  545. pm_runtime_enable(dev);
  546. pm_runtime_get_noresume(dev);
  547. ret = devm_spi_register_master(dev, ctrl);
  548. if (ret)
  549. goto err_pm_runtime_free;
  550. pm_runtime_mark_last_busy(dev);
  551. pm_runtime_put_autosuspend(dev);
  552. return 0;
  553. err_pm_runtime_free:
  554. pm_runtime_get_sync(qspi->dev);
  555. /* disable qspi */
  556. writel_relaxed(0, qspi->io_base + QSPI_CR);
  557. mutex_destroy(&qspi->lock);
  558. pm_runtime_put_noidle(qspi->dev);
  559. pm_runtime_disable(qspi->dev);
  560. pm_runtime_set_suspended(qspi->dev);
  561. pm_runtime_dont_use_autosuspend(qspi->dev);
  562. err_dma_free:
  563. stm32_qspi_dma_free(qspi);
  564. err_clk_disable:
  565. clk_disable_unprepare(qspi->clk);
  566. err_master_put:
  567. spi_master_put(qspi->ctrl);
  568. return ret;
  569. }
  570. static int stm32_qspi_remove(struct platform_device *pdev)
  571. {
  572. struct stm32_qspi *qspi = platform_get_drvdata(pdev);
  573. pm_runtime_get_sync(qspi->dev);
  574. /* disable qspi */
  575. writel_relaxed(0, qspi->io_base + QSPI_CR);
  576. stm32_qspi_dma_free(qspi);
  577. mutex_destroy(&qspi->lock);
  578. pm_runtime_put_noidle(qspi->dev);
  579. pm_runtime_disable(qspi->dev);
  580. pm_runtime_set_suspended(qspi->dev);
  581. pm_runtime_dont_use_autosuspend(qspi->dev);
  582. clk_disable_unprepare(qspi->clk);
  583. return 0;
  584. }
  585. static int __maybe_unused stm32_qspi_runtime_suspend(struct device *dev)
  586. {
  587. struct stm32_qspi *qspi = dev_get_drvdata(dev);
  588. clk_disable_unprepare(qspi->clk);
  589. return 0;
  590. }
  591. static int __maybe_unused stm32_qspi_runtime_resume(struct device *dev)
  592. {
  593. struct stm32_qspi *qspi = dev_get_drvdata(dev);
  594. return clk_prepare_enable(qspi->clk);
  595. }
  596. static int __maybe_unused stm32_qspi_suspend(struct device *dev)
  597. {
  598. pinctrl_pm_select_sleep_state(dev);
  599. return pm_runtime_force_suspend(dev);
  600. }
  601. static int __maybe_unused stm32_qspi_resume(struct device *dev)
  602. {
  603. struct stm32_qspi *qspi = dev_get_drvdata(dev);
  604. int ret;
  605. ret = pm_runtime_force_resume(dev);
  606. if (ret < 0)
  607. return ret;
  608. pinctrl_pm_select_default_state(dev);
  609. ret = pm_runtime_get_sync(dev);
  610. if (ret < 0) {
  611. pm_runtime_put_noidle(dev);
  612. return ret;
  613. }
  614. writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
  615. writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
  616. pm_runtime_mark_last_busy(dev);
  617. pm_runtime_put_autosuspend(dev);
  618. return 0;
  619. }
  620. static const struct dev_pm_ops stm32_qspi_pm_ops = {
  621. SET_RUNTIME_PM_OPS(stm32_qspi_runtime_suspend,
  622. stm32_qspi_runtime_resume, NULL)
  623. SET_SYSTEM_SLEEP_PM_OPS(stm32_qspi_suspend, stm32_qspi_resume)
  624. };
  625. static const struct of_device_id stm32_qspi_match[] = {
  626. {.compatible = "st,stm32f469-qspi"},
  627. {}
  628. };
  629. MODULE_DEVICE_TABLE(of, stm32_qspi_match);
  630. static struct platform_driver stm32_qspi_driver = {
  631. .probe = stm32_qspi_probe,
  632. .remove = stm32_qspi_remove,
  633. .driver = {
  634. .name = "stm32-qspi",
  635. .of_match_table = stm32_qspi_match,
  636. .pm = &stm32_qspi_pm_ops,
  637. },
  638. };
  639. module_platform_driver(stm32_qspi_driver);
  640. MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
  641. MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver");
  642. MODULE_LICENSE("GPL v2");