spi-st-ssc4.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2008-2014 STMicroelectronics Limited
  4. *
  5. * Author: Angus Clark <Angus.Clark@st.com>
  6. * Patrice Chotard <patrice.chotard@st.com>
  7. * Lee Jones <lee.jones@linaro.org>
  8. *
  9. * SPI master mode controller driver, used in STMicroelectronics devices.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/delay.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/module.h>
  16. #include <linux/pinctrl/consumer.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/of.h>
  19. #include <linux/of_gpio.h>
  20. #include <linux/of_irq.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/spi/spi.h>
  23. #include <linux/spi/spi_bitbang.h>
  24. /* SSC registers */
  25. #define SSC_BRG 0x000
  26. #define SSC_TBUF 0x004
  27. #define SSC_RBUF 0x008
  28. #define SSC_CTL 0x00C
  29. #define SSC_IEN 0x010
  30. #define SSC_I2C 0x018
  31. /* SSC Control */
  32. #define SSC_CTL_DATA_WIDTH_9 0x8
  33. #define SSC_CTL_DATA_WIDTH_MSK 0xf
  34. #define SSC_CTL_BM 0xf
  35. #define SSC_CTL_HB BIT(4)
  36. #define SSC_CTL_PH BIT(5)
  37. #define SSC_CTL_PO BIT(6)
  38. #define SSC_CTL_SR BIT(7)
  39. #define SSC_CTL_MS BIT(8)
  40. #define SSC_CTL_EN BIT(9)
  41. #define SSC_CTL_LPB BIT(10)
  42. #define SSC_CTL_EN_TX_FIFO BIT(11)
  43. #define SSC_CTL_EN_RX_FIFO BIT(12)
  44. #define SSC_CTL_EN_CLST_RX BIT(13)
  45. /* SSC Interrupt Enable */
  46. #define SSC_IEN_TEEN BIT(2)
  47. #define FIFO_SIZE 8
  48. struct spi_st {
  49. /* SSC SPI Controller */
  50. void __iomem *base;
  51. struct clk *clk;
  52. struct device *dev;
  53. /* SSC SPI current transaction */
  54. const u8 *tx_ptr;
  55. u8 *rx_ptr;
  56. u16 bytes_per_word;
  57. unsigned int words_remaining;
  58. unsigned int baud;
  59. struct completion done;
  60. };
  61. /* Load the TX FIFO */
  62. static void ssc_write_tx_fifo(struct spi_st *spi_st)
  63. {
  64. unsigned int count, i;
  65. uint32_t word = 0;
  66. if (spi_st->words_remaining > FIFO_SIZE)
  67. count = FIFO_SIZE;
  68. else
  69. count = spi_st->words_remaining;
  70. for (i = 0; i < count; i++) {
  71. if (spi_st->tx_ptr) {
  72. if (spi_st->bytes_per_word == 1) {
  73. word = *spi_st->tx_ptr++;
  74. } else {
  75. word = *spi_st->tx_ptr++;
  76. word = *spi_st->tx_ptr++ | (word << 8);
  77. }
  78. }
  79. writel_relaxed(word, spi_st->base + SSC_TBUF);
  80. }
  81. }
  82. /* Read the RX FIFO */
  83. static void ssc_read_rx_fifo(struct spi_st *spi_st)
  84. {
  85. unsigned int count, i;
  86. uint32_t word = 0;
  87. if (spi_st->words_remaining > FIFO_SIZE)
  88. count = FIFO_SIZE;
  89. else
  90. count = spi_st->words_remaining;
  91. for (i = 0; i < count; i++) {
  92. word = readl_relaxed(spi_st->base + SSC_RBUF);
  93. if (spi_st->rx_ptr) {
  94. if (spi_st->bytes_per_word == 1) {
  95. *spi_st->rx_ptr++ = (uint8_t)word;
  96. } else {
  97. *spi_st->rx_ptr++ = (word >> 8);
  98. *spi_st->rx_ptr++ = word & 0xff;
  99. }
  100. }
  101. }
  102. spi_st->words_remaining -= count;
  103. }
  104. static int spi_st_transfer_one(struct spi_master *master,
  105. struct spi_device *spi, struct spi_transfer *t)
  106. {
  107. struct spi_st *spi_st = spi_master_get_devdata(master);
  108. uint32_t ctl = 0;
  109. /* Setup transfer */
  110. spi_st->tx_ptr = t->tx_buf;
  111. spi_st->rx_ptr = t->rx_buf;
  112. if (spi->bits_per_word > 8) {
  113. /*
  114. * Anything greater than 8 bits-per-word requires 2
  115. * bytes-per-word in the RX/TX buffers
  116. */
  117. spi_st->bytes_per_word = 2;
  118. spi_st->words_remaining = t->len / 2;
  119. } else if (spi->bits_per_word == 8 && !(t->len & 0x1)) {
  120. /*
  121. * If transfer is even-length, and 8 bits-per-word, then
  122. * implement as half-length 16 bits-per-word transfer
  123. */
  124. spi_st->bytes_per_word = 2;
  125. spi_st->words_remaining = t->len / 2;
  126. /* Set SSC_CTL to 16 bits-per-word */
  127. ctl = readl_relaxed(spi_st->base + SSC_CTL);
  128. writel_relaxed((ctl | 0xf), spi_st->base + SSC_CTL);
  129. readl_relaxed(spi_st->base + SSC_RBUF);
  130. } else {
  131. spi_st->bytes_per_word = 1;
  132. spi_st->words_remaining = t->len;
  133. }
  134. reinit_completion(&spi_st->done);
  135. /* Start transfer by writing to the TX FIFO */
  136. ssc_write_tx_fifo(spi_st);
  137. writel_relaxed(SSC_IEN_TEEN, spi_st->base + SSC_IEN);
  138. /* Wait for transfer to complete */
  139. wait_for_completion(&spi_st->done);
  140. /* Restore SSC_CTL if necessary */
  141. if (ctl)
  142. writel_relaxed(ctl, spi_st->base + SSC_CTL);
  143. spi_finalize_current_transfer(spi->master);
  144. return t->len;
  145. }
  146. static void spi_st_cleanup(struct spi_device *spi)
  147. {
  148. gpio_free(spi->cs_gpio);
  149. }
  150. /* the spi->mode bits understood by this driver: */
  151. #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_HIGH)
  152. static int spi_st_setup(struct spi_device *spi)
  153. {
  154. struct spi_st *spi_st = spi_master_get_devdata(spi->master);
  155. u32 spi_st_clk, sscbrg, var;
  156. u32 hz = spi->max_speed_hz;
  157. int cs = spi->cs_gpio;
  158. int ret;
  159. if (!hz) {
  160. dev_err(&spi->dev, "max_speed_hz unspecified\n");
  161. return -EINVAL;
  162. }
  163. if (!gpio_is_valid(cs)) {
  164. dev_err(&spi->dev, "%d is not a valid gpio\n", cs);
  165. return -EINVAL;
  166. }
  167. ret = gpio_request(cs, dev_name(&spi->dev));
  168. if (ret) {
  169. dev_err(&spi->dev, "could not request gpio:%d\n", cs);
  170. return ret;
  171. }
  172. ret = gpio_direction_output(cs, spi->mode & SPI_CS_HIGH);
  173. if (ret)
  174. goto out_free_gpio;
  175. spi_st_clk = clk_get_rate(spi_st->clk);
  176. /* Set SSC_BRF */
  177. sscbrg = spi_st_clk / (2 * hz);
  178. if (sscbrg < 0x07 || sscbrg > BIT(16)) {
  179. dev_err(&spi->dev,
  180. "baudrate %d outside valid range %d\n", sscbrg, hz);
  181. ret = -EINVAL;
  182. goto out_free_gpio;
  183. }
  184. spi_st->baud = spi_st_clk / (2 * sscbrg);
  185. if (sscbrg == BIT(16)) /* 16-bit counter wraps */
  186. sscbrg = 0x0;
  187. writel_relaxed(sscbrg, spi_st->base + SSC_BRG);
  188. dev_dbg(&spi->dev,
  189. "setting baudrate:target= %u hz, actual= %u hz, sscbrg= %u\n",
  190. hz, spi_st->baud, sscbrg);
  191. /* Set SSC_CTL and enable SSC */
  192. var = readl_relaxed(spi_st->base + SSC_CTL);
  193. var |= SSC_CTL_MS;
  194. if (spi->mode & SPI_CPOL)
  195. var |= SSC_CTL_PO;
  196. else
  197. var &= ~SSC_CTL_PO;
  198. if (spi->mode & SPI_CPHA)
  199. var |= SSC_CTL_PH;
  200. else
  201. var &= ~SSC_CTL_PH;
  202. if ((spi->mode & SPI_LSB_FIRST) == 0)
  203. var |= SSC_CTL_HB;
  204. else
  205. var &= ~SSC_CTL_HB;
  206. if (spi->mode & SPI_LOOP)
  207. var |= SSC_CTL_LPB;
  208. else
  209. var &= ~SSC_CTL_LPB;
  210. var &= ~SSC_CTL_DATA_WIDTH_MSK;
  211. var |= (spi->bits_per_word - 1);
  212. var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO;
  213. var |= SSC_CTL_EN;
  214. writel_relaxed(var, spi_st->base + SSC_CTL);
  215. /* Clear the status register */
  216. readl_relaxed(spi_st->base + SSC_RBUF);
  217. return 0;
  218. out_free_gpio:
  219. gpio_free(cs);
  220. return ret;
  221. }
  222. /* Interrupt fired when TX shift register becomes empty */
  223. static irqreturn_t spi_st_irq(int irq, void *dev_id)
  224. {
  225. struct spi_st *spi_st = (struct spi_st *)dev_id;
  226. /* Read RX FIFO */
  227. ssc_read_rx_fifo(spi_st);
  228. /* Fill TX FIFO */
  229. if (spi_st->words_remaining) {
  230. ssc_write_tx_fifo(spi_st);
  231. } else {
  232. /* TX/RX complete */
  233. writel_relaxed(0x0, spi_st->base + SSC_IEN);
  234. /*
  235. * read SSC_IEN to ensure that this bit is set
  236. * before re-enabling interrupt
  237. */
  238. readl(spi_st->base + SSC_IEN);
  239. complete(&spi_st->done);
  240. }
  241. return IRQ_HANDLED;
  242. }
  243. static int spi_st_probe(struct platform_device *pdev)
  244. {
  245. struct device_node *np = pdev->dev.of_node;
  246. struct spi_master *master;
  247. struct spi_st *spi_st;
  248. int irq, ret = 0;
  249. u32 var;
  250. master = spi_alloc_master(&pdev->dev, sizeof(*spi_st));
  251. if (!master)
  252. return -ENOMEM;
  253. master->dev.of_node = np;
  254. master->mode_bits = MODEBITS;
  255. master->setup = spi_st_setup;
  256. master->cleanup = spi_st_cleanup;
  257. master->transfer_one = spi_st_transfer_one;
  258. master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
  259. master->auto_runtime_pm = true;
  260. master->bus_num = pdev->id;
  261. spi_st = spi_master_get_devdata(master);
  262. spi_st->clk = devm_clk_get(&pdev->dev, "ssc");
  263. if (IS_ERR(spi_st->clk)) {
  264. dev_err(&pdev->dev, "Unable to request clock\n");
  265. ret = PTR_ERR(spi_st->clk);
  266. goto put_master;
  267. }
  268. ret = clk_prepare_enable(spi_st->clk);
  269. if (ret)
  270. goto put_master;
  271. init_completion(&spi_st->done);
  272. /* Get resources */
  273. spi_st->base = devm_platform_ioremap_resource(pdev, 0);
  274. if (IS_ERR(spi_st->base)) {
  275. ret = PTR_ERR(spi_st->base);
  276. goto clk_disable;
  277. }
  278. /* Disable I2C and Reset SSC */
  279. writel_relaxed(0x0, spi_st->base + SSC_I2C);
  280. var = readw_relaxed(spi_st->base + SSC_CTL);
  281. var |= SSC_CTL_SR;
  282. writel_relaxed(var, spi_st->base + SSC_CTL);
  283. udelay(1);
  284. var = readl_relaxed(spi_st->base + SSC_CTL);
  285. var &= ~SSC_CTL_SR;
  286. writel_relaxed(var, spi_st->base + SSC_CTL);
  287. /* Set SSC into slave mode before reconfiguring PIO pins */
  288. var = readl_relaxed(spi_st->base + SSC_CTL);
  289. var &= ~SSC_CTL_MS;
  290. writel_relaxed(var, spi_st->base + SSC_CTL);
  291. irq = irq_of_parse_and_map(np, 0);
  292. if (!irq) {
  293. dev_err(&pdev->dev, "IRQ missing or invalid\n");
  294. ret = -EINVAL;
  295. goto clk_disable;
  296. }
  297. ret = devm_request_irq(&pdev->dev, irq, spi_st_irq, 0,
  298. pdev->name, spi_st);
  299. if (ret) {
  300. dev_err(&pdev->dev, "Failed to request irq %d\n", irq);
  301. goto clk_disable;
  302. }
  303. /* by default the device is on */
  304. pm_runtime_set_active(&pdev->dev);
  305. pm_runtime_enable(&pdev->dev);
  306. platform_set_drvdata(pdev, master);
  307. ret = devm_spi_register_master(&pdev->dev, master);
  308. if (ret) {
  309. dev_err(&pdev->dev, "Failed to register master\n");
  310. goto rpm_disable;
  311. }
  312. return 0;
  313. rpm_disable:
  314. pm_runtime_disable(&pdev->dev);
  315. clk_disable:
  316. clk_disable_unprepare(spi_st->clk);
  317. put_master:
  318. spi_master_put(master);
  319. return ret;
  320. }
  321. static int spi_st_remove(struct platform_device *pdev)
  322. {
  323. struct spi_master *master = platform_get_drvdata(pdev);
  324. struct spi_st *spi_st = spi_master_get_devdata(master);
  325. pm_runtime_disable(&pdev->dev);
  326. clk_disable_unprepare(spi_st->clk);
  327. pinctrl_pm_select_sleep_state(&pdev->dev);
  328. return 0;
  329. }
  330. #ifdef CONFIG_PM
  331. static int spi_st_runtime_suspend(struct device *dev)
  332. {
  333. struct spi_master *master = dev_get_drvdata(dev);
  334. struct spi_st *spi_st = spi_master_get_devdata(master);
  335. writel_relaxed(0, spi_st->base + SSC_IEN);
  336. pinctrl_pm_select_sleep_state(dev);
  337. clk_disable_unprepare(spi_st->clk);
  338. return 0;
  339. }
  340. static int spi_st_runtime_resume(struct device *dev)
  341. {
  342. struct spi_master *master = dev_get_drvdata(dev);
  343. struct spi_st *spi_st = spi_master_get_devdata(master);
  344. int ret;
  345. ret = clk_prepare_enable(spi_st->clk);
  346. pinctrl_pm_select_default_state(dev);
  347. return ret;
  348. }
  349. #endif
  350. #ifdef CONFIG_PM_SLEEP
  351. static int spi_st_suspend(struct device *dev)
  352. {
  353. struct spi_master *master = dev_get_drvdata(dev);
  354. int ret;
  355. ret = spi_master_suspend(master);
  356. if (ret)
  357. return ret;
  358. return pm_runtime_force_suspend(dev);
  359. }
  360. static int spi_st_resume(struct device *dev)
  361. {
  362. struct spi_master *master = dev_get_drvdata(dev);
  363. int ret;
  364. ret = spi_master_resume(master);
  365. if (ret)
  366. return ret;
  367. return pm_runtime_force_resume(dev);
  368. }
  369. #endif
  370. static const struct dev_pm_ops spi_st_pm = {
  371. SET_SYSTEM_SLEEP_PM_OPS(spi_st_suspend, spi_st_resume)
  372. SET_RUNTIME_PM_OPS(spi_st_runtime_suspend, spi_st_runtime_resume, NULL)
  373. };
  374. static const struct of_device_id stm_spi_match[] = {
  375. { .compatible = "st,comms-ssc4-spi", },
  376. {},
  377. };
  378. MODULE_DEVICE_TABLE(of, stm_spi_match);
  379. static struct platform_driver spi_st_driver = {
  380. .driver = {
  381. .name = "spi-st",
  382. .pm = &spi_st_pm,
  383. .of_match_table = of_match_ptr(stm_spi_match),
  384. },
  385. .probe = spi_st_probe,
  386. .remove = spi_st_remove,
  387. };
  388. module_platform_driver(spi_st_driver);
  389. MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
  390. MODULE_DESCRIPTION("STM SSC SPI driver");
  391. MODULE_LICENSE("GPL v2");