spi-sprd.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (C) 2018 Spreadtrum Communications Inc.
  3. #include <linux/clk.h>
  4. #include <linux/dmaengine.h>
  5. #include <linux/dma-mapping.h>
  6. #include <linux/dma/sprd-dma.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/io.h>
  9. #include <linux/iopoll.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/of_device.h>
  14. #include <linux/of_dma.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/spi/spi.h>
  18. #define SPRD_SPI_TXD 0x0
  19. #define SPRD_SPI_CLKD 0x4
  20. #define SPRD_SPI_CTL0 0x8
  21. #define SPRD_SPI_CTL1 0xc
  22. #define SPRD_SPI_CTL2 0x10
  23. #define SPRD_SPI_CTL3 0x14
  24. #define SPRD_SPI_CTL4 0x18
  25. #define SPRD_SPI_CTL5 0x1c
  26. #define SPRD_SPI_INT_EN 0x20
  27. #define SPRD_SPI_INT_CLR 0x24
  28. #define SPRD_SPI_INT_RAW_STS 0x28
  29. #define SPRD_SPI_INT_MASK_STS 0x2c
  30. #define SPRD_SPI_STS1 0x30
  31. #define SPRD_SPI_STS2 0x34
  32. #define SPRD_SPI_DSP_WAIT 0x38
  33. #define SPRD_SPI_STS3 0x3c
  34. #define SPRD_SPI_CTL6 0x40
  35. #define SPRD_SPI_STS4 0x44
  36. #define SPRD_SPI_FIFO_RST 0x48
  37. #define SPRD_SPI_CTL7 0x4c
  38. #define SPRD_SPI_STS5 0x50
  39. #define SPRD_SPI_CTL8 0x54
  40. #define SPRD_SPI_CTL9 0x58
  41. #define SPRD_SPI_CTL10 0x5c
  42. #define SPRD_SPI_CTL11 0x60
  43. #define SPRD_SPI_CTL12 0x64
  44. #define SPRD_SPI_STS6 0x68
  45. #define SPRD_SPI_STS7 0x6c
  46. #define SPRD_SPI_STS8 0x70
  47. #define SPRD_SPI_STS9 0x74
  48. /* Bits & mask definition for register CTL0 */
  49. #define SPRD_SPI_SCK_REV BIT(13)
  50. #define SPRD_SPI_NG_TX BIT(1)
  51. #define SPRD_SPI_NG_RX BIT(0)
  52. #define SPRD_SPI_CHNL_LEN_MASK GENMASK(4, 0)
  53. #define SPRD_SPI_CSN_MASK GENMASK(11, 8)
  54. #define SPRD_SPI_CS0_VALID BIT(8)
  55. /* Bits & mask definition for register SPI_INT_EN */
  56. #define SPRD_SPI_TX_END_INT_EN BIT(8)
  57. #define SPRD_SPI_RX_END_INT_EN BIT(9)
  58. /* Bits & mask definition for register SPI_INT_RAW_STS */
  59. #define SPRD_SPI_TX_END_RAW BIT(8)
  60. #define SPRD_SPI_RX_END_RAW BIT(9)
  61. /* Bits & mask definition for register SPI_INT_CLR */
  62. #define SPRD_SPI_TX_END_CLR BIT(8)
  63. #define SPRD_SPI_RX_END_CLR BIT(9)
  64. /* Bits & mask definition for register INT_MASK_STS */
  65. #define SPRD_SPI_MASK_RX_END BIT(9)
  66. #define SPRD_SPI_MASK_TX_END BIT(8)
  67. /* Bits & mask definition for register STS2 */
  68. #define SPRD_SPI_TX_BUSY BIT(8)
  69. /* Bits & mask definition for register CTL1 */
  70. #define SPRD_SPI_RX_MODE BIT(12)
  71. #define SPRD_SPI_TX_MODE BIT(13)
  72. #define SPRD_SPI_RTX_MD_MASK GENMASK(13, 12)
  73. /* Bits & mask definition for register CTL2 */
  74. #define SPRD_SPI_DMA_EN BIT(6)
  75. /* Bits & mask definition for register CTL4 */
  76. #define SPRD_SPI_START_RX BIT(9)
  77. #define SPRD_SPI_ONLY_RECV_MASK GENMASK(8, 0)
  78. /* Bits & mask definition for register SPI_INT_CLR */
  79. #define SPRD_SPI_RX_END_INT_CLR BIT(9)
  80. #define SPRD_SPI_TX_END_INT_CLR BIT(8)
  81. /* Bits & mask definition for register SPI_INT_RAW */
  82. #define SPRD_SPI_RX_END_IRQ BIT(9)
  83. #define SPRD_SPI_TX_END_IRQ BIT(8)
  84. /* Bits & mask definition for register CTL12 */
  85. #define SPRD_SPI_SW_RX_REQ BIT(0)
  86. #define SPRD_SPI_SW_TX_REQ BIT(1)
  87. /* Bits & mask definition for register CTL7 */
  88. #define SPRD_SPI_DATA_LINE2_EN BIT(15)
  89. #define SPRD_SPI_MODE_MASK GENMASK(5, 3)
  90. #define SPRD_SPI_MODE_OFFSET 3
  91. #define SPRD_SPI_3WIRE_MODE 4
  92. #define SPRD_SPI_4WIRE_MODE 0
  93. /* Bits & mask definition for register CTL8 */
  94. #define SPRD_SPI_TX_MAX_LEN_MASK GENMASK(19, 0)
  95. #define SPRD_SPI_TX_LEN_H_MASK GENMASK(3, 0)
  96. #define SPRD_SPI_TX_LEN_H_OFFSET 16
  97. /* Bits & mask definition for register CTL9 */
  98. #define SPRD_SPI_TX_LEN_L_MASK GENMASK(15, 0)
  99. /* Bits & mask definition for register CTL10 */
  100. #define SPRD_SPI_RX_MAX_LEN_MASK GENMASK(19, 0)
  101. #define SPRD_SPI_RX_LEN_H_MASK GENMASK(3, 0)
  102. #define SPRD_SPI_RX_LEN_H_OFFSET 16
  103. /* Bits & mask definition for register CTL11 */
  104. #define SPRD_SPI_RX_LEN_L_MASK GENMASK(15, 0)
  105. /* Default & maximum word delay cycles */
  106. #define SPRD_SPI_MIN_DELAY_CYCLE 14
  107. #define SPRD_SPI_MAX_DELAY_CYCLE 130
  108. #define SPRD_SPI_FIFO_SIZE 32
  109. #define SPRD_SPI_CHIP_CS_NUM 0x4
  110. #define SPRD_SPI_CHNL_LEN 2
  111. #define SPRD_SPI_DEFAULT_SOURCE 26000000
  112. #define SPRD_SPI_MAX_SPEED_HZ 48000000
  113. #define SPRD_SPI_AUTOSUSPEND_DELAY 100
  114. #define SPRD_SPI_DMA_STEP 8
  115. enum sprd_spi_dma_channel {
  116. SPRD_SPI_RX,
  117. SPRD_SPI_TX,
  118. SPRD_SPI_MAX,
  119. };
  120. struct sprd_spi_dma {
  121. bool enable;
  122. struct dma_chan *dma_chan[SPRD_SPI_MAX];
  123. enum dma_slave_buswidth width;
  124. u32 fragmens_len;
  125. u32 rx_len;
  126. };
  127. struct sprd_spi {
  128. void __iomem *base;
  129. phys_addr_t phy_base;
  130. struct device *dev;
  131. struct clk *clk;
  132. int irq;
  133. u32 src_clk;
  134. u32 hw_mode;
  135. u32 trans_len;
  136. u32 trans_mode;
  137. u32 word_delay;
  138. u32 hw_speed_hz;
  139. u32 len;
  140. int status;
  141. struct sprd_spi_dma dma;
  142. struct completion xfer_completion;
  143. const void *tx_buf;
  144. void *rx_buf;
  145. int (*read_bufs)(struct sprd_spi *ss, u32 len);
  146. int (*write_bufs)(struct sprd_spi *ss, u32 len);
  147. };
  148. static u32 sprd_spi_transfer_max_timeout(struct sprd_spi *ss,
  149. struct spi_transfer *t)
  150. {
  151. /*
  152. * The time spent on transmission of the full FIFO data is the maximum
  153. * SPI transmission time.
  154. */
  155. u32 size = t->bits_per_word * SPRD_SPI_FIFO_SIZE;
  156. u32 bit_time_us = DIV_ROUND_UP(USEC_PER_SEC, ss->hw_speed_hz);
  157. u32 total_time_us = size * bit_time_us;
  158. /*
  159. * There is an interval between data and the data in our SPI hardware,
  160. * so the total transmission time need add the interval time.
  161. */
  162. u32 interval_cycle = SPRD_SPI_FIFO_SIZE * ss->word_delay;
  163. u32 interval_time_us = DIV_ROUND_UP(interval_cycle * USEC_PER_SEC,
  164. ss->src_clk);
  165. return total_time_us + interval_time_us;
  166. }
  167. static int sprd_spi_wait_for_tx_end(struct sprd_spi *ss, struct spi_transfer *t)
  168. {
  169. u32 val, us;
  170. int ret;
  171. us = sprd_spi_transfer_max_timeout(ss, t);
  172. ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val,
  173. val & SPRD_SPI_TX_END_IRQ, 0, us);
  174. if (ret) {
  175. dev_err(ss->dev, "SPI error, spi send timeout!\n");
  176. return ret;
  177. }
  178. ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_STS2, val,
  179. !(val & SPRD_SPI_TX_BUSY), 0, us);
  180. if (ret) {
  181. dev_err(ss->dev, "SPI error, spi busy timeout!\n");
  182. return ret;
  183. }
  184. writel_relaxed(SPRD_SPI_TX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR);
  185. return 0;
  186. }
  187. static int sprd_spi_wait_for_rx_end(struct sprd_spi *ss, struct spi_transfer *t)
  188. {
  189. u32 val, us;
  190. int ret;
  191. us = sprd_spi_transfer_max_timeout(ss, t);
  192. ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val,
  193. val & SPRD_SPI_RX_END_IRQ, 0, us);
  194. if (ret) {
  195. dev_err(ss->dev, "SPI error, spi rx timeout!\n");
  196. return ret;
  197. }
  198. writel_relaxed(SPRD_SPI_RX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR);
  199. return 0;
  200. }
  201. static void sprd_spi_tx_req(struct sprd_spi *ss)
  202. {
  203. writel_relaxed(SPRD_SPI_SW_TX_REQ, ss->base + SPRD_SPI_CTL12);
  204. }
  205. static void sprd_spi_rx_req(struct sprd_spi *ss)
  206. {
  207. writel_relaxed(SPRD_SPI_SW_RX_REQ, ss->base + SPRD_SPI_CTL12);
  208. }
  209. static void sprd_spi_enter_idle(struct sprd_spi *ss)
  210. {
  211. u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL1);
  212. val &= ~SPRD_SPI_RTX_MD_MASK;
  213. writel_relaxed(val, ss->base + SPRD_SPI_CTL1);
  214. }
  215. static void sprd_spi_set_transfer_bits(struct sprd_spi *ss, u32 bits)
  216. {
  217. u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
  218. /* Set the valid bits for every transaction */
  219. val &= ~(SPRD_SPI_CHNL_LEN_MASK << SPRD_SPI_CHNL_LEN);
  220. val |= bits << SPRD_SPI_CHNL_LEN;
  221. writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
  222. }
  223. static void sprd_spi_set_tx_length(struct sprd_spi *ss, u32 length)
  224. {
  225. u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL8);
  226. length &= SPRD_SPI_TX_MAX_LEN_MASK;
  227. val &= ~SPRD_SPI_TX_LEN_H_MASK;
  228. val |= length >> SPRD_SPI_TX_LEN_H_OFFSET;
  229. writel_relaxed(val, ss->base + SPRD_SPI_CTL8);
  230. val = length & SPRD_SPI_TX_LEN_L_MASK;
  231. writel_relaxed(val, ss->base + SPRD_SPI_CTL9);
  232. }
  233. static void sprd_spi_set_rx_length(struct sprd_spi *ss, u32 length)
  234. {
  235. u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL10);
  236. length &= SPRD_SPI_RX_MAX_LEN_MASK;
  237. val &= ~SPRD_SPI_RX_LEN_H_MASK;
  238. val |= length >> SPRD_SPI_RX_LEN_H_OFFSET;
  239. writel_relaxed(val, ss->base + SPRD_SPI_CTL10);
  240. val = length & SPRD_SPI_RX_LEN_L_MASK;
  241. writel_relaxed(val, ss->base + SPRD_SPI_CTL11);
  242. }
  243. static void sprd_spi_chipselect(struct spi_device *sdev, bool cs)
  244. {
  245. struct spi_controller *sctlr = sdev->controller;
  246. struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
  247. u32 val;
  248. val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
  249. /* The SPI controller will pull down CS pin if cs is 0 */
  250. if (!cs) {
  251. val &= ~SPRD_SPI_CS0_VALID;
  252. writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
  253. } else {
  254. val |= SPRD_SPI_CSN_MASK;
  255. writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
  256. }
  257. }
  258. static int sprd_spi_write_only_receive(struct sprd_spi *ss, u32 len)
  259. {
  260. u32 val;
  261. /* Clear the start receive bit and reset receive data number */
  262. val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
  263. val &= ~(SPRD_SPI_START_RX | SPRD_SPI_ONLY_RECV_MASK);
  264. writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
  265. /* Set the receive data length */
  266. val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
  267. val |= len & SPRD_SPI_ONLY_RECV_MASK;
  268. writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
  269. /* Trigger to receive data */
  270. val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
  271. val |= SPRD_SPI_START_RX;
  272. writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
  273. return len;
  274. }
  275. static int sprd_spi_write_bufs_u8(struct sprd_spi *ss, u32 len)
  276. {
  277. u8 *tx_p = (u8 *)ss->tx_buf;
  278. int i;
  279. for (i = 0; i < len; i++)
  280. writeb_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD);
  281. ss->tx_buf += i;
  282. return i;
  283. }
  284. static int sprd_spi_write_bufs_u16(struct sprd_spi *ss, u32 len)
  285. {
  286. u16 *tx_p = (u16 *)ss->tx_buf;
  287. int i;
  288. for (i = 0; i < len; i++)
  289. writew_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD);
  290. ss->tx_buf += i << 1;
  291. return i << 1;
  292. }
  293. static int sprd_spi_write_bufs_u32(struct sprd_spi *ss, u32 len)
  294. {
  295. u32 *tx_p = (u32 *)ss->tx_buf;
  296. int i;
  297. for (i = 0; i < len; i++)
  298. writel_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD);
  299. ss->tx_buf += i << 2;
  300. return i << 2;
  301. }
  302. static int sprd_spi_read_bufs_u8(struct sprd_spi *ss, u32 len)
  303. {
  304. u8 *rx_p = (u8 *)ss->rx_buf;
  305. int i;
  306. for (i = 0; i < len; i++)
  307. rx_p[i] = readb_relaxed(ss->base + SPRD_SPI_TXD);
  308. ss->rx_buf += i;
  309. return i;
  310. }
  311. static int sprd_spi_read_bufs_u16(struct sprd_spi *ss, u32 len)
  312. {
  313. u16 *rx_p = (u16 *)ss->rx_buf;
  314. int i;
  315. for (i = 0; i < len; i++)
  316. rx_p[i] = readw_relaxed(ss->base + SPRD_SPI_TXD);
  317. ss->rx_buf += i << 1;
  318. return i << 1;
  319. }
  320. static int sprd_spi_read_bufs_u32(struct sprd_spi *ss, u32 len)
  321. {
  322. u32 *rx_p = (u32 *)ss->rx_buf;
  323. int i;
  324. for (i = 0; i < len; i++)
  325. rx_p[i] = readl_relaxed(ss->base + SPRD_SPI_TXD);
  326. ss->rx_buf += i << 2;
  327. return i << 2;
  328. }
  329. static int sprd_spi_txrx_bufs(struct spi_device *sdev, struct spi_transfer *t)
  330. {
  331. struct sprd_spi *ss = spi_controller_get_devdata(sdev->controller);
  332. u32 trans_len = ss->trans_len, len;
  333. int ret, write_size = 0, read_size = 0;
  334. while (trans_len) {
  335. len = trans_len > SPRD_SPI_FIFO_SIZE ? SPRD_SPI_FIFO_SIZE :
  336. trans_len;
  337. if (ss->trans_mode & SPRD_SPI_TX_MODE) {
  338. sprd_spi_set_tx_length(ss, len);
  339. write_size += ss->write_bufs(ss, len);
  340. /*
  341. * For our 3 wires mode or dual TX line mode, we need
  342. * to request the controller to transfer.
  343. */
  344. if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL)
  345. sprd_spi_tx_req(ss);
  346. ret = sprd_spi_wait_for_tx_end(ss, t);
  347. } else {
  348. sprd_spi_set_rx_length(ss, len);
  349. /*
  350. * For our 3 wires mode or dual TX line mode, we need
  351. * to request the controller to read.
  352. */
  353. if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL)
  354. sprd_spi_rx_req(ss);
  355. else
  356. write_size += ss->write_bufs(ss, len);
  357. ret = sprd_spi_wait_for_rx_end(ss, t);
  358. }
  359. if (ret)
  360. goto complete;
  361. if (ss->trans_mode & SPRD_SPI_RX_MODE)
  362. read_size += ss->read_bufs(ss, len);
  363. trans_len -= len;
  364. }
  365. if (ss->trans_mode & SPRD_SPI_TX_MODE)
  366. ret = write_size;
  367. else
  368. ret = read_size;
  369. complete:
  370. sprd_spi_enter_idle(ss);
  371. return ret;
  372. }
  373. static void sprd_spi_irq_enable(struct sprd_spi *ss)
  374. {
  375. u32 val;
  376. /* Clear interrupt status before enabling interrupt. */
  377. writel_relaxed(SPRD_SPI_TX_END_CLR | SPRD_SPI_RX_END_CLR,
  378. ss->base + SPRD_SPI_INT_CLR);
  379. /* Enable SPI interrupt only in DMA mode. */
  380. val = readl_relaxed(ss->base + SPRD_SPI_INT_EN);
  381. writel_relaxed(val | SPRD_SPI_TX_END_INT_EN |
  382. SPRD_SPI_RX_END_INT_EN,
  383. ss->base + SPRD_SPI_INT_EN);
  384. }
  385. static void sprd_spi_irq_disable(struct sprd_spi *ss)
  386. {
  387. writel_relaxed(0, ss->base + SPRD_SPI_INT_EN);
  388. }
  389. static void sprd_spi_dma_enable(struct sprd_spi *ss, bool enable)
  390. {
  391. u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL2);
  392. if (enable)
  393. val |= SPRD_SPI_DMA_EN;
  394. else
  395. val &= ~SPRD_SPI_DMA_EN;
  396. writel_relaxed(val, ss->base + SPRD_SPI_CTL2);
  397. }
  398. static int sprd_spi_dma_submit(struct dma_chan *dma_chan,
  399. struct dma_slave_config *c,
  400. struct sg_table *sg,
  401. enum dma_transfer_direction dir)
  402. {
  403. struct dma_async_tx_descriptor *desc;
  404. dma_cookie_t cookie;
  405. unsigned long flags;
  406. int ret;
  407. ret = dmaengine_slave_config(dma_chan, c);
  408. if (ret < 0)
  409. return ret;
  410. flags = SPRD_DMA_FLAGS(SPRD_DMA_CHN_MODE_NONE, SPRD_DMA_NO_TRG,
  411. SPRD_DMA_FRAG_REQ, SPRD_DMA_TRANS_INT);
  412. desc = dmaengine_prep_slave_sg(dma_chan, sg->sgl, sg->nents, dir, flags);
  413. if (!desc)
  414. return -ENODEV;
  415. cookie = dmaengine_submit(desc);
  416. if (dma_submit_error(cookie))
  417. return dma_submit_error(cookie);
  418. dma_async_issue_pending(dma_chan);
  419. return 0;
  420. }
  421. static int sprd_spi_dma_rx_config(struct sprd_spi *ss, struct spi_transfer *t)
  422. {
  423. struct dma_chan *dma_chan = ss->dma.dma_chan[SPRD_SPI_RX];
  424. struct dma_slave_config config = {
  425. .src_addr = ss->phy_base,
  426. .src_addr_width = ss->dma.width,
  427. .dst_addr_width = ss->dma.width,
  428. .dst_maxburst = ss->dma.fragmens_len,
  429. };
  430. int ret;
  431. ret = sprd_spi_dma_submit(dma_chan, &config, &t->rx_sg, DMA_DEV_TO_MEM);
  432. if (ret)
  433. return ret;
  434. return ss->dma.rx_len;
  435. }
  436. static int sprd_spi_dma_tx_config(struct sprd_spi *ss, struct spi_transfer *t)
  437. {
  438. struct dma_chan *dma_chan = ss->dma.dma_chan[SPRD_SPI_TX];
  439. struct dma_slave_config config = {
  440. .dst_addr = ss->phy_base,
  441. .src_addr_width = ss->dma.width,
  442. .dst_addr_width = ss->dma.width,
  443. .src_maxburst = ss->dma.fragmens_len,
  444. };
  445. int ret;
  446. ret = sprd_spi_dma_submit(dma_chan, &config, &t->tx_sg, DMA_MEM_TO_DEV);
  447. if (ret)
  448. return ret;
  449. return t->len;
  450. }
  451. static int sprd_spi_dma_request(struct sprd_spi *ss)
  452. {
  453. ss->dma.dma_chan[SPRD_SPI_RX] = dma_request_chan(ss->dev, "rx_chn");
  454. if (IS_ERR_OR_NULL(ss->dma.dma_chan[SPRD_SPI_RX]))
  455. return dev_err_probe(ss->dev, PTR_ERR(ss->dma.dma_chan[SPRD_SPI_RX]),
  456. "request RX DMA channel failed!\n");
  457. ss->dma.dma_chan[SPRD_SPI_TX] = dma_request_chan(ss->dev, "tx_chn");
  458. if (IS_ERR_OR_NULL(ss->dma.dma_chan[SPRD_SPI_TX])) {
  459. dma_release_channel(ss->dma.dma_chan[SPRD_SPI_RX]);
  460. return dev_err_probe(ss->dev, PTR_ERR(ss->dma.dma_chan[SPRD_SPI_TX]),
  461. "request TX DMA channel failed!\n");
  462. }
  463. return 0;
  464. }
  465. static void sprd_spi_dma_release(struct sprd_spi *ss)
  466. {
  467. if (ss->dma.dma_chan[SPRD_SPI_RX])
  468. dma_release_channel(ss->dma.dma_chan[SPRD_SPI_RX]);
  469. if (ss->dma.dma_chan[SPRD_SPI_TX])
  470. dma_release_channel(ss->dma.dma_chan[SPRD_SPI_TX]);
  471. }
  472. static int sprd_spi_dma_txrx_bufs(struct spi_device *sdev,
  473. struct spi_transfer *t)
  474. {
  475. struct sprd_spi *ss = spi_master_get_devdata(sdev->master);
  476. u32 trans_len = ss->trans_len;
  477. int ret, write_size = 0;
  478. reinit_completion(&ss->xfer_completion);
  479. sprd_spi_irq_enable(ss);
  480. if (ss->trans_mode & SPRD_SPI_TX_MODE) {
  481. write_size = sprd_spi_dma_tx_config(ss, t);
  482. sprd_spi_set_tx_length(ss, trans_len);
  483. /*
  484. * For our 3 wires mode or dual TX line mode, we need
  485. * to request the controller to transfer.
  486. */
  487. if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL)
  488. sprd_spi_tx_req(ss);
  489. } else {
  490. sprd_spi_set_rx_length(ss, trans_len);
  491. /*
  492. * For our 3 wires mode or dual TX line mode, we need
  493. * to request the controller to read.
  494. */
  495. if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL)
  496. sprd_spi_rx_req(ss);
  497. else
  498. write_size = ss->write_bufs(ss, trans_len);
  499. }
  500. if (write_size < 0) {
  501. ret = write_size;
  502. dev_err(ss->dev, "failed to write, ret = %d\n", ret);
  503. goto trans_complete;
  504. }
  505. if (ss->trans_mode & SPRD_SPI_RX_MODE) {
  506. /*
  507. * Set up the DMA receive data length, which must be an
  508. * integral multiple of fragment length. But when the length
  509. * of received data is less than fragment length, DMA can be
  510. * configured to receive data according to the actual length
  511. * of received data.
  512. */
  513. ss->dma.rx_len = t->len > ss->dma.fragmens_len ?
  514. (t->len - t->len % ss->dma.fragmens_len) :
  515. t->len;
  516. ret = sprd_spi_dma_rx_config(ss, t);
  517. if (ret < 0) {
  518. dev_err(&sdev->dev,
  519. "failed to configure rx DMA, ret = %d\n", ret);
  520. goto trans_complete;
  521. }
  522. }
  523. sprd_spi_dma_enable(ss, true);
  524. wait_for_completion(&(ss->xfer_completion));
  525. if (ss->trans_mode & SPRD_SPI_TX_MODE)
  526. ret = write_size;
  527. else
  528. ret = ss->dma.rx_len;
  529. trans_complete:
  530. sprd_spi_dma_enable(ss, false);
  531. sprd_spi_enter_idle(ss);
  532. sprd_spi_irq_disable(ss);
  533. return ret;
  534. }
  535. static void sprd_spi_set_speed(struct sprd_spi *ss, u32 speed_hz)
  536. {
  537. /*
  538. * From SPI datasheet, the prescale calculation formula:
  539. * prescale = SPI source clock / (2 * SPI_freq) - 1;
  540. */
  541. u32 clk_div = DIV_ROUND_UP(ss->src_clk, speed_hz << 1) - 1;
  542. /* Save the real hardware speed */
  543. ss->hw_speed_hz = (ss->src_clk >> 1) / (clk_div + 1);
  544. writel_relaxed(clk_div, ss->base + SPRD_SPI_CLKD);
  545. }
  546. static int sprd_spi_init_hw(struct sprd_spi *ss, struct spi_transfer *t)
  547. {
  548. struct spi_delay *d = &t->word_delay;
  549. u16 word_delay, interval;
  550. u32 val;
  551. if (d->unit != SPI_DELAY_UNIT_SCK)
  552. return -EINVAL;
  553. val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
  554. val &= ~(SPRD_SPI_SCK_REV | SPRD_SPI_NG_TX | SPRD_SPI_NG_RX);
  555. /* Set default chip selection, clock phase and clock polarity */
  556. val |= ss->hw_mode & SPI_CPHA ? SPRD_SPI_NG_RX : SPRD_SPI_NG_TX;
  557. val |= ss->hw_mode & SPI_CPOL ? SPRD_SPI_SCK_REV : 0;
  558. writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
  559. /*
  560. * Set the intervals of two SPI frames, and the inteval calculation
  561. * formula as below per datasheet:
  562. * interval time (source clock cycles) = interval * 4 + 10.
  563. */
  564. word_delay = clamp_t(u16, d->value, SPRD_SPI_MIN_DELAY_CYCLE,
  565. SPRD_SPI_MAX_DELAY_CYCLE);
  566. interval = DIV_ROUND_UP(word_delay - 10, 4);
  567. ss->word_delay = interval * 4 + 10;
  568. writel_relaxed(interval, ss->base + SPRD_SPI_CTL5);
  569. /* Reset SPI fifo */
  570. writel_relaxed(1, ss->base + SPRD_SPI_FIFO_RST);
  571. writel_relaxed(0, ss->base + SPRD_SPI_FIFO_RST);
  572. /* Set SPI work mode */
  573. val = readl_relaxed(ss->base + SPRD_SPI_CTL7);
  574. val &= ~SPRD_SPI_MODE_MASK;
  575. if (ss->hw_mode & SPI_3WIRE)
  576. val |= SPRD_SPI_3WIRE_MODE << SPRD_SPI_MODE_OFFSET;
  577. else
  578. val |= SPRD_SPI_4WIRE_MODE << SPRD_SPI_MODE_OFFSET;
  579. if (ss->hw_mode & SPI_TX_DUAL)
  580. val |= SPRD_SPI_DATA_LINE2_EN;
  581. else
  582. val &= ~SPRD_SPI_DATA_LINE2_EN;
  583. writel_relaxed(val, ss->base + SPRD_SPI_CTL7);
  584. return 0;
  585. }
  586. static int sprd_spi_setup_transfer(struct spi_device *sdev,
  587. struct spi_transfer *t)
  588. {
  589. struct sprd_spi *ss = spi_controller_get_devdata(sdev->controller);
  590. u8 bits_per_word = t->bits_per_word;
  591. u32 val, mode = 0;
  592. int ret;
  593. ss->len = t->len;
  594. ss->tx_buf = t->tx_buf;
  595. ss->rx_buf = t->rx_buf;
  596. ss->hw_mode = sdev->mode;
  597. ret = sprd_spi_init_hw(ss, t);
  598. if (ret)
  599. return ret;
  600. /* Set tansfer speed and valid bits */
  601. sprd_spi_set_speed(ss, t->speed_hz);
  602. sprd_spi_set_transfer_bits(ss, bits_per_word);
  603. if (bits_per_word > 16)
  604. bits_per_word = round_up(bits_per_word, 16);
  605. else
  606. bits_per_word = round_up(bits_per_word, 8);
  607. switch (bits_per_word) {
  608. case 8:
  609. ss->trans_len = t->len;
  610. ss->read_bufs = sprd_spi_read_bufs_u8;
  611. ss->write_bufs = sprd_spi_write_bufs_u8;
  612. ss->dma.width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  613. ss->dma.fragmens_len = SPRD_SPI_DMA_STEP;
  614. break;
  615. case 16:
  616. ss->trans_len = t->len >> 1;
  617. ss->read_bufs = sprd_spi_read_bufs_u16;
  618. ss->write_bufs = sprd_spi_write_bufs_u16;
  619. ss->dma.width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  620. ss->dma.fragmens_len = SPRD_SPI_DMA_STEP << 1;
  621. break;
  622. case 32:
  623. ss->trans_len = t->len >> 2;
  624. ss->read_bufs = sprd_spi_read_bufs_u32;
  625. ss->write_bufs = sprd_spi_write_bufs_u32;
  626. ss->dma.width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  627. ss->dma.fragmens_len = SPRD_SPI_DMA_STEP << 2;
  628. break;
  629. default:
  630. return -EINVAL;
  631. }
  632. /* Set transfer read or write mode */
  633. val = readl_relaxed(ss->base + SPRD_SPI_CTL1);
  634. val &= ~SPRD_SPI_RTX_MD_MASK;
  635. if (t->tx_buf)
  636. mode |= SPRD_SPI_TX_MODE;
  637. if (t->rx_buf)
  638. mode |= SPRD_SPI_RX_MODE;
  639. writel_relaxed(val | mode, ss->base + SPRD_SPI_CTL1);
  640. ss->trans_mode = mode;
  641. /*
  642. * If in only receive mode, we need to trigger the SPI controller to
  643. * receive data automatically.
  644. */
  645. if (ss->trans_mode == SPRD_SPI_RX_MODE)
  646. ss->write_bufs = sprd_spi_write_only_receive;
  647. return 0;
  648. }
  649. static int sprd_spi_transfer_one(struct spi_controller *sctlr,
  650. struct spi_device *sdev,
  651. struct spi_transfer *t)
  652. {
  653. int ret;
  654. ret = sprd_spi_setup_transfer(sdev, t);
  655. if (ret)
  656. goto setup_err;
  657. if (sctlr->can_dma(sctlr, sdev, t))
  658. ret = sprd_spi_dma_txrx_bufs(sdev, t);
  659. else
  660. ret = sprd_spi_txrx_bufs(sdev, t);
  661. if (ret == t->len)
  662. ret = 0;
  663. else if (ret >= 0)
  664. ret = -EREMOTEIO;
  665. setup_err:
  666. spi_finalize_current_transfer(sctlr);
  667. return ret;
  668. }
  669. static irqreturn_t sprd_spi_handle_irq(int irq, void *data)
  670. {
  671. struct sprd_spi *ss = (struct sprd_spi *)data;
  672. u32 val = readl_relaxed(ss->base + SPRD_SPI_INT_MASK_STS);
  673. if (val & SPRD_SPI_MASK_TX_END) {
  674. writel_relaxed(SPRD_SPI_TX_END_CLR, ss->base + SPRD_SPI_INT_CLR);
  675. if (!(ss->trans_mode & SPRD_SPI_RX_MODE))
  676. complete(&ss->xfer_completion);
  677. return IRQ_HANDLED;
  678. }
  679. if (val & SPRD_SPI_MASK_RX_END) {
  680. writel_relaxed(SPRD_SPI_RX_END_CLR, ss->base + SPRD_SPI_INT_CLR);
  681. if (ss->dma.rx_len < ss->len) {
  682. ss->rx_buf += ss->dma.rx_len;
  683. ss->dma.rx_len +=
  684. ss->read_bufs(ss, ss->len - ss->dma.rx_len);
  685. }
  686. complete(&ss->xfer_completion);
  687. return IRQ_HANDLED;
  688. }
  689. return IRQ_NONE;
  690. }
  691. static int sprd_spi_irq_init(struct platform_device *pdev, struct sprd_spi *ss)
  692. {
  693. int ret;
  694. ss->irq = platform_get_irq(pdev, 0);
  695. if (ss->irq < 0)
  696. return ss->irq;
  697. ret = devm_request_irq(&pdev->dev, ss->irq, sprd_spi_handle_irq,
  698. 0, pdev->name, ss);
  699. if (ret)
  700. dev_err(&pdev->dev, "failed to request spi irq %d, ret = %d\n",
  701. ss->irq, ret);
  702. return ret;
  703. }
  704. static int sprd_spi_clk_init(struct platform_device *pdev, struct sprd_spi *ss)
  705. {
  706. struct clk *clk_spi, *clk_parent;
  707. clk_spi = devm_clk_get(&pdev->dev, "spi");
  708. if (IS_ERR(clk_spi)) {
  709. dev_warn(&pdev->dev, "can't get the spi clock\n");
  710. clk_spi = NULL;
  711. }
  712. clk_parent = devm_clk_get(&pdev->dev, "source");
  713. if (IS_ERR(clk_parent)) {
  714. dev_warn(&pdev->dev, "can't get the source clock\n");
  715. clk_parent = NULL;
  716. }
  717. ss->clk = devm_clk_get(&pdev->dev, "enable");
  718. if (IS_ERR(ss->clk)) {
  719. dev_err(&pdev->dev, "can't get the enable clock\n");
  720. return PTR_ERR(ss->clk);
  721. }
  722. if (!clk_set_parent(clk_spi, clk_parent))
  723. ss->src_clk = clk_get_rate(clk_spi);
  724. else
  725. ss->src_clk = SPRD_SPI_DEFAULT_SOURCE;
  726. return 0;
  727. }
  728. static bool sprd_spi_can_dma(struct spi_controller *sctlr,
  729. struct spi_device *spi, struct spi_transfer *t)
  730. {
  731. struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
  732. return ss->dma.enable && (t->len > SPRD_SPI_FIFO_SIZE);
  733. }
  734. static int sprd_spi_dma_init(struct platform_device *pdev, struct sprd_spi *ss)
  735. {
  736. int ret;
  737. ret = sprd_spi_dma_request(ss);
  738. if (ret) {
  739. if (ret == -EPROBE_DEFER)
  740. return ret;
  741. dev_warn(&pdev->dev,
  742. "failed to request dma, enter no dma mode, ret = %d\n",
  743. ret);
  744. return 0;
  745. }
  746. ss->dma.enable = true;
  747. return 0;
  748. }
  749. static int sprd_spi_probe(struct platform_device *pdev)
  750. {
  751. struct spi_controller *sctlr;
  752. struct resource *res;
  753. struct sprd_spi *ss;
  754. int ret;
  755. pdev->id = of_alias_get_id(pdev->dev.of_node, "spi");
  756. sctlr = spi_alloc_master(&pdev->dev, sizeof(*ss));
  757. if (!sctlr)
  758. return -ENOMEM;
  759. ss = spi_controller_get_devdata(sctlr);
  760. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  761. ss->base = devm_ioremap_resource(&pdev->dev, res);
  762. if (IS_ERR(ss->base)) {
  763. ret = PTR_ERR(ss->base);
  764. goto free_controller;
  765. }
  766. ss->phy_base = res->start;
  767. ss->dev = &pdev->dev;
  768. sctlr->dev.of_node = pdev->dev.of_node;
  769. sctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_3WIRE | SPI_TX_DUAL;
  770. sctlr->bus_num = pdev->id;
  771. sctlr->set_cs = sprd_spi_chipselect;
  772. sctlr->transfer_one = sprd_spi_transfer_one;
  773. sctlr->can_dma = sprd_spi_can_dma;
  774. sctlr->auto_runtime_pm = true;
  775. sctlr->max_speed_hz = min_t(u32, ss->src_clk >> 1,
  776. SPRD_SPI_MAX_SPEED_HZ);
  777. init_completion(&ss->xfer_completion);
  778. platform_set_drvdata(pdev, sctlr);
  779. ret = sprd_spi_clk_init(pdev, ss);
  780. if (ret)
  781. goto free_controller;
  782. ret = sprd_spi_irq_init(pdev, ss);
  783. if (ret)
  784. goto free_controller;
  785. ret = sprd_spi_dma_init(pdev, ss);
  786. if (ret)
  787. goto free_controller;
  788. ret = clk_prepare_enable(ss->clk);
  789. if (ret)
  790. goto release_dma;
  791. ret = pm_runtime_set_active(&pdev->dev);
  792. if (ret < 0)
  793. goto disable_clk;
  794. pm_runtime_set_autosuspend_delay(&pdev->dev,
  795. SPRD_SPI_AUTOSUSPEND_DELAY);
  796. pm_runtime_use_autosuspend(&pdev->dev);
  797. pm_runtime_enable(&pdev->dev);
  798. ret = pm_runtime_get_sync(&pdev->dev);
  799. if (ret < 0) {
  800. dev_err(&pdev->dev, "failed to resume SPI controller\n");
  801. goto err_rpm_put;
  802. }
  803. ret = devm_spi_register_controller(&pdev->dev, sctlr);
  804. if (ret)
  805. goto err_rpm_put;
  806. pm_runtime_mark_last_busy(&pdev->dev);
  807. pm_runtime_put_autosuspend(&pdev->dev);
  808. return 0;
  809. err_rpm_put:
  810. pm_runtime_put_noidle(&pdev->dev);
  811. pm_runtime_disable(&pdev->dev);
  812. disable_clk:
  813. clk_disable_unprepare(ss->clk);
  814. release_dma:
  815. sprd_spi_dma_release(ss);
  816. free_controller:
  817. spi_controller_put(sctlr);
  818. return ret;
  819. }
  820. static int sprd_spi_remove(struct platform_device *pdev)
  821. {
  822. struct spi_controller *sctlr = platform_get_drvdata(pdev);
  823. struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
  824. int ret;
  825. ret = pm_runtime_get_sync(ss->dev);
  826. if (ret < 0) {
  827. pm_runtime_put_noidle(ss->dev);
  828. dev_err(ss->dev, "failed to resume SPI controller\n");
  829. return ret;
  830. }
  831. spi_controller_suspend(sctlr);
  832. if (ss->dma.enable)
  833. sprd_spi_dma_release(ss);
  834. clk_disable_unprepare(ss->clk);
  835. pm_runtime_put_noidle(&pdev->dev);
  836. pm_runtime_disable(&pdev->dev);
  837. return 0;
  838. }
  839. static int __maybe_unused sprd_spi_runtime_suspend(struct device *dev)
  840. {
  841. struct spi_controller *sctlr = dev_get_drvdata(dev);
  842. struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
  843. if (ss->dma.enable)
  844. sprd_spi_dma_release(ss);
  845. clk_disable_unprepare(ss->clk);
  846. return 0;
  847. }
  848. static int __maybe_unused sprd_spi_runtime_resume(struct device *dev)
  849. {
  850. struct spi_controller *sctlr = dev_get_drvdata(dev);
  851. struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
  852. int ret;
  853. ret = clk_prepare_enable(ss->clk);
  854. if (ret)
  855. return ret;
  856. if (!ss->dma.enable)
  857. return 0;
  858. ret = sprd_spi_dma_request(ss);
  859. if (ret)
  860. clk_disable_unprepare(ss->clk);
  861. return ret;
  862. }
  863. static const struct dev_pm_ops sprd_spi_pm_ops = {
  864. SET_RUNTIME_PM_OPS(sprd_spi_runtime_suspend,
  865. sprd_spi_runtime_resume, NULL)
  866. };
  867. static const struct of_device_id sprd_spi_of_match[] = {
  868. { .compatible = "sprd,sc9860-spi", },
  869. { /* sentinel */ }
  870. };
  871. MODULE_DEVICE_TABLE(of, sprd_spi_of_match);
  872. static struct platform_driver sprd_spi_driver = {
  873. .driver = {
  874. .name = "sprd-spi",
  875. .of_match_table = sprd_spi_of_match,
  876. .pm = &sprd_spi_pm_ops,
  877. },
  878. .probe = sprd_spi_probe,
  879. .remove = sprd_spi_remove,
  880. };
  881. module_platform_driver(sprd_spi_driver);
  882. MODULE_DESCRIPTION("Spreadtrum SPI Controller driver");
  883. MODULE_AUTHOR("Lanqing Liu <lanqing.liu@spreadtrum.com>");
  884. MODULE_LICENSE("GPL v2");