spi-sprd-adi.c 15 KB

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  1. /*
  2. * Copyright (C) 2017 Spreadtrum Communications Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/hwspinlock.h>
  8. #include <linux/init.h>
  9. #include <linux/io.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/of_device.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/reboot.h>
  16. #include <linux/spi/spi.h>
  17. #include <linux/sizes.h>
  18. /* Registers definitions for ADI controller */
  19. #define REG_ADI_CTRL0 0x4
  20. #define REG_ADI_CHN_PRIL 0x8
  21. #define REG_ADI_CHN_PRIH 0xc
  22. #define REG_ADI_INT_EN 0x10
  23. #define REG_ADI_INT_RAW 0x14
  24. #define REG_ADI_INT_MASK 0x18
  25. #define REG_ADI_INT_CLR 0x1c
  26. #define REG_ADI_GSSI_CFG0 0x20
  27. #define REG_ADI_GSSI_CFG1 0x24
  28. #define REG_ADI_RD_CMD 0x28
  29. #define REG_ADI_RD_DATA 0x2c
  30. #define REG_ADI_ARM_FIFO_STS 0x30
  31. #define REG_ADI_STS 0x34
  32. #define REG_ADI_EVT_FIFO_STS 0x38
  33. #define REG_ADI_ARM_CMD_STS 0x3c
  34. #define REG_ADI_CHN_EN 0x40
  35. #define REG_ADI_CHN_ADDR(id) (0x44 + (id - 2) * 4)
  36. #define REG_ADI_CHN_EN1 0x20c
  37. /* Bits definitions for register REG_ADI_GSSI_CFG0 */
  38. #define BIT_CLK_ALL_ON BIT(30)
  39. /* Bits definitions for register REG_ADI_RD_DATA */
  40. #define BIT_RD_CMD_BUSY BIT(31)
  41. #define RD_ADDR_SHIFT 16
  42. #define RD_VALUE_MASK GENMASK(15, 0)
  43. #define RD_ADDR_MASK GENMASK(30, 16)
  44. /* Bits definitions for register REG_ADI_ARM_FIFO_STS */
  45. #define BIT_FIFO_FULL BIT(11)
  46. #define BIT_FIFO_EMPTY BIT(10)
  47. /*
  48. * ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
  49. * The slave devices address offset is always 0x8000 and size is 4K.
  50. */
  51. #define ADI_SLAVE_ADDR_SIZE SZ_4K
  52. #define ADI_SLAVE_OFFSET 0x8000
  53. /* Timeout (ms) for the trylock of hardware spinlocks */
  54. #define ADI_HWSPINLOCK_TIMEOUT 5000
  55. /*
  56. * ADI controller has 50 channels including 2 software channels
  57. * and 48 hardware channels.
  58. */
  59. #define ADI_HW_CHNS 50
  60. #define ADI_FIFO_DRAIN_TIMEOUT 1000
  61. #define ADI_READ_TIMEOUT 2000
  62. #define REG_ADDR_LOW_MASK GENMASK(11, 0)
  63. /* Registers definitions for PMIC watchdog controller */
  64. #define REG_WDG_LOAD_LOW 0x80
  65. #define REG_WDG_LOAD_HIGH 0x84
  66. #define REG_WDG_CTRL 0x88
  67. #define REG_WDG_LOCK 0xa0
  68. /* Bits definitions for register REG_WDG_CTRL */
  69. #define BIT_WDG_RUN BIT(1)
  70. #define BIT_WDG_NEW BIT(2)
  71. #define BIT_WDG_RST BIT(3)
  72. /* Registers definitions for PMIC */
  73. #define PMIC_RST_STATUS 0xee8
  74. #define PMIC_MODULE_EN 0xc08
  75. #define PMIC_CLK_EN 0xc18
  76. #define BIT_WDG_EN BIT(2)
  77. /* Definition of PMIC reset status register */
  78. #define HWRST_STATUS_SECURITY 0x02
  79. #define HWRST_STATUS_RECOVERY 0x20
  80. #define HWRST_STATUS_NORMAL 0x40
  81. #define HWRST_STATUS_ALARM 0x50
  82. #define HWRST_STATUS_SLEEP 0x60
  83. #define HWRST_STATUS_FASTBOOT 0x30
  84. #define HWRST_STATUS_SPECIAL 0x70
  85. #define HWRST_STATUS_PANIC 0x80
  86. #define HWRST_STATUS_CFTREBOOT 0x90
  87. #define HWRST_STATUS_AUTODLOADER 0xa0
  88. #define HWRST_STATUS_IQMODE 0xb0
  89. #define HWRST_STATUS_SPRDISK 0xc0
  90. #define HWRST_STATUS_FACTORYTEST 0xe0
  91. #define HWRST_STATUS_WATCHDOG 0xf0
  92. /* Use default timeout 50 ms that converts to watchdog values */
  93. #define WDG_LOAD_VAL ((50 * 32768) / 1000)
  94. #define WDG_LOAD_MASK GENMASK(15, 0)
  95. #define WDG_UNLOCK_KEY 0xe551
  96. struct sprd_adi {
  97. struct spi_controller *ctlr;
  98. struct device *dev;
  99. void __iomem *base;
  100. struct hwspinlock *hwlock;
  101. unsigned long slave_vbase;
  102. unsigned long slave_pbase;
  103. struct notifier_block restart_handler;
  104. };
  105. static int sprd_adi_check_paddr(struct sprd_adi *sadi, u32 paddr)
  106. {
  107. if (paddr < sadi->slave_pbase || paddr >
  108. (sadi->slave_pbase + ADI_SLAVE_ADDR_SIZE)) {
  109. dev_err(sadi->dev,
  110. "slave physical address is incorrect, addr = 0x%x\n",
  111. paddr);
  112. return -EINVAL;
  113. }
  114. return 0;
  115. }
  116. static unsigned long sprd_adi_to_vaddr(struct sprd_adi *sadi, u32 paddr)
  117. {
  118. return (paddr - sadi->slave_pbase + sadi->slave_vbase);
  119. }
  120. static int sprd_adi_drain_fifo(struct sprd_adi *sadi)
  121. {
  122. u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
  123. u32 sts;
  124. do {
  125. sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS);
  126. if (sts & BIT_FIFO_EMPTY)
  127. break;
  128. cpu_relax();
  129. } while (--timeout);
  130. if (timeout == 0) {
  131. dev_err(sadi->dev, "drain write fifo timeout\n");
  132. return -EBUSY;
  133. }
  134. return 0;
  135. }
  136. static int sprd_adi_fifo_is_full(struct sprd_adi *sadi)
  137. {
  138. return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL;
  139. }
  140. static int sprd_adi_read(struct sprd_adi *sadi, u32 reg_paddr, u32 *read_val)
  141. {
  142. int read_timeout = ADI_READ_TIMEOUT;
  143. unsigned long flags;
  144. u32 val, rd_addr;
  145. int ret = 0;
  146. if (sadi->hwlock) {
  147. ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
  148. ADI_HWSPINLOCK_TIMEOUT,
  149. &flags);
  150. if (ret) {
  151. dev_err(sadi->dev, "get the hw lock failed\n");
  152. return ret;
  153. }
  154. }
  155. /*
  156. * Set the physical register address need to read into RD_CMD register,
  157. * then ADI controller will start to transfer automatically.
  158. */
  159. writel_relaxed(reg_paddr, sadi->base + REG_ADI_RD_CMD);
  160. /*
  161. * Wait read operation complete, the BIT_RD_CMD_BUSY will be set
  162. * simultaneously when writing read command to register, and the
  163. * BIT_RD_CMD_BUSY will be cleared after the read operation is
  164. * completed.
  165. */
  166. do {
  167. val = readl_relaxed(sadi->base + REG_ADI_RD_DATA);
  168. if (!(val & BIT_RD_CMD_BUSY))
  169. break;
  170. cpu_relax();
  171. } while (--read_timeout);
  172. if (read_timeout == 0) {
  173. dev_err(sadi->dev, "ADI read timeout\n");
  174. ret = -EBUSY;
  175. goto out;
  176. }
  177. /*
  178. * The return value includes data and read register address, from bit 0
  179. * to bit 15 are data, and from bit 16 to bit 30 are read register
  180. * address. Then we can check the returned register address to validate
  181. * data.
  182. */
  183. rd_addr = (val & RD_ADDR_MASK ) >> RD_ADDR_SHIFT;
  184. if (rd_addr != (reg_paddr & REG_ADDR_LOW_MASK)) {
  185. dev_err(sadi->dev, "read error, reg addr = 0x%x, val = 0x%x\n",
  186. reg_paddr, val);
  187. ret = -EIO;
  188. goto out;
  189. }
  190. *read_val = val & RD_VALUE_MASK;
  191. out:
  192. if (sadi->hwlock)
  193. hwspin_unlock_irqrestore(sadi->hwlock, &flags);
  194. return ret;
  195. }
  196. static int sprd_adi_write(struct sprd_adi *sadi, u32 reg_paddr, u32 val)
  197. {
  198. unsigned long reg = sprd_adi_to_vaddr(sadi, reg_paddr);
  199. u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
  200. unsigned long flags;
  201. int ret;
  202. if (sadi->hwlock) {
  203. ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
  204. ADI_HWSPINLOCK_TIMEOUT,
  205. &flags);
  206. if (ret) {
  207. dev_err(sadi->dev, "get the hw lock failed\n");
  208. return ret;
  209. }
  210. }
  211. ret = sprd_adi_drain_fifo(sadi);
  212. if (ret < 0)
  213. goto out;
  214. /*
  215. * we should wait for write fifo is empty before writing data to PMIC
  216. * registers.
  217. */
  218. do {
  219. if (!sprd_adi_fifo_is_full(sadi)) {
  220. writel_relaxed(val, (void __iomem *)reg);
  221. break;
  222. }
  223. cpu_relax();
  224. } while (--timeout);
  225. if (timeout == 0) {
  226. dev_err(sadi->dev, "write fifo is full\n");
  227. ret = -EBUSY;
  228. }
  229. out:
  230. if (sadi->hwlock)
  231. hwspin_unlock_irqrestore(sadi->hwlock, &flags);
  232. return ret;
  233. }
  234. static int sprd_adi_transfer_one(struct spi_controller *ctlr,
  235. struct spi_device *spi_dev,
  236. struct spi_transfer *t)
  237. {
  238. struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
  239. u32 phy_reg, val;
  240. int ret;
  241. if (t->rx_buf) {
  242. phy_reg = *(u32 *)t->rx_buf + sadi->slave_pbase;
  243. ret = sprd_adi_check_paddr(sadi, phy_reg);
  244. if (ret)
  245. return ret;
  246. ret = sprd_adi_read(sadi, phy_reg, &val);
  247. if (ret)
  248. return ret;
  249. *(u32 *)t->rx_buf = val;
  250. } else if (t->tx_buf) {
  251. u32 *p = (u32 *)t->tx_buf;
  252. /*
  253. * Get the physical register address need to write and convert
  254. * the physical address to virtual address. Since we need
  255. * virtual register address to write.
  256. */
  257. phy_reg = *p++ + sadi->slave_pbase;
  258. ret = sprd_adi_check_paddr(sadi, phy_reg);
  259. if (ret)
  260. return ret;
  261. val = *p;
  262. ret = sprd_adi_write(sadi, phy_reg, val);
  263. if (ret)
  264. return ret;
  265. } else {
  266. dev_err(sadi->dev, "no buffer for transfer\n");
  267. return -EINVAL;
  268. }
  269. return 0;
  270. }
  271. static void sprd_adi_set_wdt_rst_mode(struct sprd_adi *sadi)
  272. {
  273. #if IS_ENABLED(CONFIG_SPRD_WATCHDOG)
  274. u32 val;
  275. /* Set default watchdog reboot mode */
  276. sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
  277. val |= HWRST_STATUS_WATCHDOG;
  278. sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
  279. #endif
  280. }
  281. static int sprd_adi_restart_handler(struct notifier_block *this,
  282. unsigned long mode, void *cmd)
  283. {
  284. struct sprd_adi *sadi = container_of(this, struct sprd_adi,
  285. restart_handler);
  286. u32 val, reboot_mode = 0;
  287. if (!cmd)
  288. reboot_mode = HWRST_STATUS_NORMAL;
  289. else if (!strncmp(cmd, "recovery", 8))
  290. reboot_mode = HWRST_STATUS_RECOVERY;
  291. else if (!strncmp(cmd, "alarm", 5))
  292. reboot_mode = HWRST_STATUS_ALARM;
  293. else if (!strncmp(cmd, "fastsleep", 9))
  294. reboot_mode = HWRST_STATUS_SLEEP;
  295. else if (!strncmp(cmd, "bootloader", 10))
  296. reboot_mode = HWRST_STATUS_FASTBOOT;
  297. else if (!strncmp(cmd, "panic", 5))
  298. reboot_mode = HWRST_STATUS_PANIC;
  299. else if (!strncmp(cmd, "special", 7))
  300. reboot_mode = HWRST_STATUS_SPECIAL;
  301. else if (!strncmp(cmd, "cftreboot", 9))
  302. reboot_mode = HWRST_STATUS_CFTREBOOT;
  303. else if (!strncmp(cmd, "autodloader", 11))
  304. reboot_mode = HWRST_STATUS_AUTODLOADER;
  305. else if (!strncmp(cmd, "iqmode", 6))
  306. reboot_mode = HWRST_STATUS_IQMODE;
  307. else if (!strncmp(cmd, "sprdisk", 7))
  308. reboot_mode = HWRST_STATUS_SPRDISK;
  309. else if (!strncmp(cmd, "tospanic", 8))
  310. reboot_mode = HWRST_STATUS_SECURITY;
  311. else if (!strncmp(cmd, "factorytest", 11))
  312. reboot_mode = HWRST_STATUS_FACTORYTEST;
  313. else
  314. reboot_mode = HWRST_STATUS_NORMAL;
  315. /* Record the reboot mode */
  316. sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
  317. val &= ~HWRST_STATUS_WATCHDOG;
  318. val |= reboot_mode;
  319. sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
  320. /* Enable the interface clock of the watchdog */
  321. sprd_adi_read(sadi, sadi->slave_pbase + PMIC_MODULE_EN, &val);
  322. val |= BIT_WDG_EN;
  323. sprd_adi_write(sadi, sadi->slave_pbase + PMIC_MODULE_EN, val);
  324. /* Enable the work clock of the watchdog */
  325. sprd_adi_read(sadi, sadi->slave_pbase + PMIC_CLK_EN, &val);
  326. val |= BIT_WDG_EN;
  327. sprd_adi_write(sadi, sadi->slave_pbase + PMIC_CLK_EN, val);
  328. /* Unlock the watchdog */
  329. sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, WDG_UNLOCK_KEY);
  330. sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val);
  331. val |= BIT_WDG_NEW;
  332. sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val);
  333. /* Load the watchdog timeout value, 50ms is always enough. */
  334. sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_HIGH, 0);
  335. sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_LOW,
  336. WDG_LOAD_VAL & WDG_LOAD_MASK);
  337. /* Start the watchdog to reset system */
  338. sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val);
  339. val |= BIT_WDG_RUN | BIT_WDG_RST;
  340. sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val);
  341. /* Lock the watchdog */
  342. sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, ~WDG_UNLOCK_KEY);
  343. mdelay(1000);
  344. dev_emerg(sadi->dev, "Unable to restart system\n");
  345. return NOTIFY_DONE;
  346. }
  347. static void sprd_adi_hw_init(struct sprd_adi *sadi)
  348. {
  349. struct device_node *np = sadi->dev->of_node;
  350. int i, size, chn_cnt;
  351. const __be32 *list;
  352. u32 tmp;
  353. /* Set all channels as default priority */
  354. writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
  355. writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);
  356. /* Set clock auto gate mode */
  357. tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0);
  358. tmp &= ~BIT_CLK_ALL_ON;
  359. writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0);
  360. /* Set hardware channels setting */
  361. list = of_get_property(np, "sprd,hw-channels", &size);
  362. if (!list || !size) {
  363. dev_info(sadi->dev, "no hw channels setting in node\n");
  364. return;
  365. }
  366. chn_cnt = size / 8;
  367. for (i = 0; i < chn_cnt; i++) {
  368. u32 value;
  369. u32 chn_id = be32_to_cpu(*list++);
  370. u32 chn_config = be32_to_cpu(*list++);
  371. /* Channel 0 and 1 are software channels */
  372. if (chn_id < 2)
  373. continue;
  374. writel_relaxed(chn_config, sadi->base +
  375. REG_ADI_CHN_ADDR(chn_id));
  376. if (chn_id < 32) {
  377. value = readl_relaxed(sadi->base + REG_ADI_CHN_EN);
  378. value |= BIT(chn_id);
  379. writel_relaxed(value, sadi->base + REG_ADI_CHN_EN);
  380. } else if (chn_id < ADI_HW_CHNS) {
  381. value = readl_relaxed(sadi->base + REG_ADI_CHN_EN1);
  382. value |= BIT(chn_id - 32);
  383. writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1);
  384. }
  385. }
  386. }
  387. static int sprd_adi_probe(struct platform_device *pdev)
  388. {
  389. struct device_node *np = pdev->dev.of_node;
  390. struct spi_controller *ctlr;
  391. struct sprd_adi *sadi;
  392. struct resource *res;
  393. u32 num_chipselect;
  394. int ret;
  395. if (!np) {
  396. dev_err(&pdev->dev, "can not find the adi bus node\n");
  397. return -ENODEV;
  398. }
  399. pdev->id = of_alias_get_id(np, "spi");
  400. num_chipselect = of_get_child_count(np);
  401. ctlr = spi_alloc_master(&pdev->dev, sizeof(struct sprd_adi));
  402. if (!ctlr)
  403. return -ENOMEM;
  404. dev_set_drvdata(&pdev->dev, ctlr);
  405. sadi = spi_controller_get_devdata(ctlr);
  406. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  407. sadi->base = devm_ioremap_resource(&pdev->dev, res);
  408. if (IS_ERR(sadi->base)) {
  409. ret = PTR_ERR(sadi->base);
  410. goto put_ctlr;
  411. }
  412. sadi->slave_vbase = (unsigned long)sadi->base + ADI_SLAVE_OFFSET;
  413. sadi->slave_pbase = res->start + ADI_SLAVE_OFFSET;
  414. sadi->ctlr = ctlr;
  415. sadi->dev = &pdev->dev;
  416. ret = of_hwspin_lock_get_id(np, 0);
  417. if (ret > 0 || (IS_ENABLED(CONFIG_HWSPINLOCK) && ret == 0)) {
  418. sadi->hwlock =
  419. devm_hwspin_lock_request_specific(&pdev->dev, ret);
  420. if (!sadi->hwlock) {
  421. ret = -ENXIO;
  422. goto put_ctlr;
  423. }
  424. } else {
  425. switch (ret) {
  426. case -ENOENT:
  427. dev_info(&pdev->dev, "no hardware spinlock supplied\n");
  428. break;
  429. default:
  430. dev_err_probe(&pdev->dev, ret, "failed to find hwlock id\n");
  431. goto put_ctlr;
  432. }
  433. }
  434. sprd_adi_hw_init(sadi);
  435. sprd_adi_set_wdt_rst_mode(sadi);
  436. ctlr->dev.of_node = pdev->dev.of_node;
  437. ctlr->bus_num = pdev->id;
  438. ctlr->num_chipselect = num_chipselect;
  439. ctlr->flags = SPI_MASTER_HALF_DUPLEX;
  440. ctlr->bits_per_word_mask = 0;
  441. ctlr->transfer_one = sprd_adi_transfer_one;
  442. ret = devm_spi_register_controller(&pdev->dev, ctlr);
  443. if (ret) {
  444. dev_err(&pdev->dev, "failed to register SPI controller\n");
  445. goto put_ctlr;
  446. }
  447. sadi->restart_handler.notifier_call = sprd_adi_restart_handler;
  448. sadi->restart_handler.priority = 128;
  449. ret = register_restart_handler(&sadi->restart_handler);
  450. if (ret) {
  451. dev_err(&pdev->dev, "can not register restart handler\n");
  452. goto put_ctlr;
  453. }
  454. return 0;
  455. put_ctlr:
  456. spi_controller_put(ctlr);
  457. return ret;
  458. }
  459. static int sprd_adi_remove(struct platform_device *pdev)
  460. {
  461. struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev);
  462. struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
  463. unregister_restart_handler(&sadi->restart_handler);
  464. return 0;
  465. }
  466. static const struct of_device_id sprd_adi_of_match[] = {
  467. {
  468. .compatible = "sprd,sc9860-adi",
  469. },
  470. { },
  471. };
  472. MODULE_DEVICE_TABLE(of, sprd_adi_of_match);
  473. static struct platform_driver sprd_adi_driver = {
  474. .driver = {
  475. .name = "sprd-adi",
  476. .of_match_table = sprd_adi_of_match,
  477. },
  478. .probe = sprd_adi_probe,
  479. .remove = sprd_adi_remove,
  480. };
  481. module_platform_driver(sprd_adi_driver);
  482. MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver");
  483. MODULE_AUTHOR("Baolin Wang <Baolin.Wang@spreadtrum.com>");
  484. MODULE_LICENSE("GPL v2");