spi-sifive.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright 2018 SiFive, Inc.
  4. //
  5. // SiFive SPI controller driver (master mode only)
  6. //
  7. // Author: SiFive, Inc.
  8. // sifive@sifive.com
  9. #include <linux/clk.h>
  10. #include <linux/module.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/of.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/spi/spi.h>
  15. #include <linux/io.h>
  16. #include <linux/log2.h>
  17. #define SIFIVE_SPI_DRIVER_NAME "sifive_spi"
  18. #define SIFIVE_SPI_MAX_CS 32
  19. #define SIFIVE_SPI_DEFAULT_DEPTH 8
  20. #define SIFIVE_SPI_DEFAULT_MAX_BITS 8
  21. /* register offsets */
  22. #define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */
  23. #define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
  24. #define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */
  25. #define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */
  26. #define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */
  27. #define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */
  28. #define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */
  29. #define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */
  30. #define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
  31. #define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
  32. #define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
  33. #define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
  34. #define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
  35. #define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
  36. #define SIFIVE_SPI_REG_IE 0x70 /* Interrupt Enable Register */
  37. #define SIFIVE_SPI_REG_IP 0x74 /* Interrupt Pendings Register */
  38. /* sckdiv bits */
  39. #define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU
  40. /* sckmode bits */
  41. #define SIFIVE_SPI_SCKMODE_PHA BIT(0)
  42. #define SIFIVE_SPI_SCKMODE_POL BIT(1)
  43. #define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \
  44. SIFIVE_SPI_SCKMODE_POL)
  45. /* csmode bits */
  46. #define SIFIVE_SPI_CSMODE_MODE_AUTO 0U
  47. #define SIFIVE_SPI_CSMODE_MODE_HOLD 2U
  48. #define SIFIVE_SPI_CSMODE_MODE_OFF 3U
  49. /* delay0 bits */
  50. #define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x))
  51. #define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU
  52. #define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16)
  53. #define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
  54. /* delay1 bits */
  55. #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x))
  56. #define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU
  57. #define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16)
  58. #define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
  59. /* fmt bits */
  60. #define SIFIVE_SPI_FMT_PROTO_SINGLE 0U
  61. #define SIFIVE_SPI_FMT_PROTO_DUAL 1U
  62. #define SIFIVE_SPI_FMT_PROTO_QUAD 2U
  63. #define SIFIVE_SPI_FMT_PROTO_MASK 3U
  64. #define SIFIVE_SPI_FMT_ENDIAN BIT(2)
  65. #define SIFIVE_SPI_FMT_DIR BIT(3)
  66. #define SIFIVE_SPI_FMT_LEN(x) ((u32)(x) << 16)
  67. #define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16)
  68. /* txdata bits */
  69. #define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU
  70. #define SIFIVE_SPI_TXDATA_FULL BIT(31)
  71. /* rxdata bits */
  72. #define SIFIVE_SPI_RXDATA_DATA_MASK 0xffU
  73. #define SIFIVE_SPI_RXDATA_EMPTY BIT(31)
  74. /* ie and ip bits */
  75. #define SIFIVE_SPI_IP_TXWM BIT(0)
  76. #define SIFIVE_SPI_IP_RXWM BIT(1)
  77. struct sifive_spi {
  78. void __iomem *regs; /* virt. address of control registers */
  79. struct clk *clk; /* bus clock */
  80. unsigned int fifo_depth; /* fifo depth in words */
  81. u32 cs_inactive; /* level of the CS pins when inactive */
  82. struct completion done; /* wake-up from interrupt */
  83. };
  84. static void sifive_spi_write(struct sifive_spi *spi, int offset, u32 value)
  85. {
  86. iowrite32(value, spi->regs + offset);
  87. }
  88. static u32 sifive_spi_read(struct sifive_spi *spi, int offset)
  89. {
  90. return ioread32(spi->regs + offset);
  91. }
  92. static void sifive_spi_init(struct sifive_spi *spi)
  93. {
  94. /* Watermark interrupts are disabled by default */
  95. sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
  96. /* Default watermark FIFO threshold values */
  97. sifive_spi_write(spi, SIFIVE_SPI_REG_TXMARK, 1);
  98. sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK, 0);
  99. /* Set CS/SCK Delays and Inactive Time to defaults */
  100. sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY0,
  101. SIFIVE_SPI_DELAY0_CSSCK(1) |
  102. SIFIVE_SPI_DELAY0_SCKCS(1));
  103. sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY1,
  104. SIFIVE_SPI_DELAY1_INTERCS(1) |
  105. SIFIVE_SPI_DELAY1_INTERXFR(0));
  106. /* Exit specialized memory-mapped SPI flash mode */
  107. sifive_spi_write(spi, SIFIVE_SPI_REG_FCTRL, 0);
  108. }
  109. static int
  110. sifive_spi_prepare_message(struct spi_master *master, struct spi_message *msg)
  111. {
  112. struct sifive_spi *spi = spi_master_get_devdata(master);
  113. struct spi_device *device = msg->spi;
  114. /* Update the chip select polarity */
  115. if (device->mode & SPI_CS_HIGH)
  116. spi->cs_inactive &= ~BIT(device->chip_select);
  117. else
  118. spi->cs_inactive |= BIT(device->chip_select);
  119. sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
  120. /* Select the correct device */
  121. sifive_spi_write(spi, SIFIVE_SPI_REG_CSID, device->chip_select);
  122. /* Set clock mode */
  123. sifive_spi_write(spi, SIFIVE_SPI_REG_SCKMODE,
  124. device->mode & SIFIVE_SPI_SCKMODE_MODE_MASK);
  125. return 0;
  126. }
  127. static void sifive_spi_set_cs(struct spi_device *device, bool is_high)
  128. {
  129. struct sifive_spi *spi = spi_master_get_devdata(device->master);
  130. /* Reverse polarity is handled by SCMR/CPOL. Not inverted CS. */
  131. if (device->mode & SPI_CS_HIGH)
  132. is_high = !is_high;
  133. sifive_spi_write(spi, SIFIVE_SPI_REG_CSMODE, is_high ?
  134. SIFIVE_SPI_CSMODE_MODE_AUTO :
  135. SIFIVE_SPI_CSMODE_MODE_HOLD);
  136. }
  137. static int
  138. sifive_spi_prep_transfer(struct sifive_spi *spi, struct spi_device *device,
  139. struct spi_transfer *t)
  140. {
  141. u32 cr;
  142. unsigned int mode;
  143. /* Calculate and program the clock rate */
  144. cr = DIV_ROUND_UP(clk_get_rate(spi->clk) >> 1, t->speed_hz) - 1;
  145. cr &= SIFIVE_SPI_SCKDIV_DIV_MASK;
  146. sifive_spi_write(spi, SIFIVE_SPI_REG_SCKDIV, cr);
  147. mode = max_t(unsigned int, t->rx_nbits, t->tx_nbits);
  148. /* Set frame format */
  149. cr = SIFIVE_SPI_FMT_LEN(t->bits_per_word);
  150. switch (mode) {
  151. case SPI_NBITS_QUAD:
  152. cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
  153. break;
  154. case SPI_NBITS_DUAL:
  155. cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
  156. break;
  157. default:
  158. cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
  159. break;
  160. }
  161. if (device->mode & SPI_LSB_FIRST)
  162. cr |= SIFIVE_SPI_FMT_ENDIAN;
  163. if (!t->rx_buf)
  164. cr |= SIFIVE_SPI_FMT_DIR;
  165. sifive_spi_write(spi, SIFIVE_SPI_REG_FMT, cr);
  166. /* We will want to poll if the time we need to wait is
  167. * less than the context switching time.
  168. * Let's call that threshold 5us. The operation will take:
  169. * (8/mode) * fifo_depth / hz <= 5 * 10^-6
  170. * 1600000 * fifo_depth <= hz * mode
  171. */
  172. return 1600000 * spi->fifo_depth <= t->speed_hz * mode;
  173. }
  174. static irqreturn_t sifive_spi_irq(int irq, void *dev_id)
  175. {
  176. struct sifive_spi *spi = dev_id;
  177. u32 ip = sifive_spi_read(spi, SIFIVE_SPI_REG_IP);
  178. if (ip & (SIFIVE_SPI_IP_TXWM | SIFIVE_SPI_IP_RXWM)) {
  179. /* Disable interrupts until next transfer */
  180. sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
  181. complete(&spi->done);
  182. return IRQ_HANDLED;
  183. }
  184. return IRQ_NONE;
  185. }
  186. static void sifive_spi_wait(struct sifive_spi *spi, u32 bit, int poll)
  187. {
  188. if (poll) {
  189. u32 cr;
  190. do {
  191. cr = sifive_spi_read(spi, SIFIVE_SPI_REG_IP);
  192. } while (!(cr & bit));
  193. } else {
  194. reinit_completion(&spi->done);
  195. sifive_spi_write(spi, SIFIVE_SPI_REG_IE, bit);
  196. wait_for_completion(&spi->done);
  197. }
  198. }
  199. static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
  200. {
  201. WARN_ON_ONCE((sifive_spi_read(spi, SIFIVE_SPI_REG_TXDATA)
  202. & SIFIVE_SPI_TXDATA_FULL) != 0);
  203. sifive_spi_write(spi, SIFIVE_SPI_REG_TXDATA,
  204. *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK);
  205. }
  206. static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
  207. {
  208. u32 data = sifive_spi_read(spi, SIFIVE_SPI_REG_RXDATA);
  209. WARN_ON_ONCE((data & SIFIVE_SPI_RXDATA_EMPTY) != 0);
  210. *rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
  211. }
  212. static int
  213. sifive_spi_transfer_one(struct spi_master *master, struct spi_device *device,
  214. struct spi_transfer *t)
  215. {
  216. struct sifive_spi *spi = spi_master_get_devdata(master);
  217. int poll = sifive_spi_prep_transfer(spi, device, t);
  218. const u8 *tx_ptr = t->tx_buf;
  219. u8 *rx_ptr = t->rx_buf;
  220. unsigned int remaining_words = t->len;
  221. while (remaining_words) {
  222. unsigned int n_words = min(remaining_words, spi->fifo_depth);
  223. unsigned int i;
  224. /* Enqueue n_words for transmission */
  225. for (i = 0; i < n_words; i++)
  226. sifive_spi_tx(spi, tx_ptr++);
  227. if (rx_ptr) {
  228. /* Wait for transmission + reception to complete */
  229. sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK,
  230. n_words - 1);
  231. sifive_spi_wait(spi, SIFIVE_SPI_IP_RXWM, poll);
  232. /* Read out all the data from the RX FIFO */
  233. for (i = 0; i < n_words; i++)
  234. sifive_spi_rx(spi, rx_ptr++);
  235. } else {
  236. /* Wait for transmission to complete */
  237. sifive_spi_wait(spi, SIFIVE_SPI_IP_TXWM, poll);
  238. }
  239. remaining_words -= n_words;
  240. }
  241. return 0;
  242. }
  243. static int sifive_spi_probe(struct platform_device *pdev)
  244. {
  245. struct sifive_spi *spi;
  246. int ret, irq, num_cs;
  247. u32 cs_bits, max_bits_per_word;
  248. struct spi_master *master;
  249. master = spi_alloc_master(&pdev->dev, sizeof(struct sifive_spi));
  250. if (!master) {
  251. dev_err(&pdev->dev, "out of memory\n");
  252. return -ENOMEM;
  253. }
  254. spi = spi_master_get_devdata(master);
  255. init_completion(&spi->done);
  256. platform_set_drvdata(pdev, master);
  257. spi->regs = devm_platform_ioremap_resource(pdev, 0);
  258. if (IS_ERR(spi->regs)) {
  259. ret = PTR_ERR(spi->regs);
  260. goto put_master;
  261. }
  262. spi->clk = devm_clk_get(&pdev->dev, NULL);
  263. if (IS_ERR(spi->clk)) {
  264. dev_err(&pdev->dev, "Unable to find bus clock\n");
  265. ret = PTR_ERR(spi->clk);
  266. goto put_master;
  267. }
  268. irq = platform_get_irq(pdev, 0);
  269. if (irq < 0) {
  270. ret = irq;
  271. goto put_master;
  272. }
  273. /* Optional parameters */
  274. ret =
  275. of_property_read_u32(pdev->dev.of_node, "sifive,fifo-depth",
  276. &spi->fifo_depth);
  277. if (ret < 0)
  278. spi->fifo_depth = SIFIVE_SPI_DEFAULT_DEPTH;
  279. ret =
  280. of_property_read_u32(pdev->dev.of_node, "sifive,max-bits-per-word",
  281. &max_bits_per_word);
  282. if (!ret && max_bits_per_word < 8) {
  283. dev_err(&pdev->dev, "Only 8bit SPI words supported by the driver\n");
  284. ret = -EINVAL;
  285. goto put_master;
  286. }
  287. /* Spin up the bus clock before hitting registers */
  288. ret = clk_prepare_enable(spi->clk);
  289. if (ret) {
  290. dev_err(&pdev->dev, "Unable to enable bus clock\n");
  291. goto put_master;
  292. }
  293. /* probe the number of CS lines */
  294. spi->cs_inactive = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
  295. sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, 0xffffffffU);
  296. cs_bits = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
  297. sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
  298. if (!cs_bits) {
  299. dev_err(&pdev->dev, "Could not auto probe CS lines\n");
  300. ret = -EINVAL;
  301. goto disable_clk;
  302. }
  303. num_cs = ilog2(cs_bits) + 1;
  304. if (num_cs > SIFIVE_SPI_MAX_CS) {
  305. dev_err(&pdev->dev, "Invalid number of spi slaves\n");
  306. ret = -EINVAL;
  307. goto disable_clk;
  308. }
  309. /* Define our master */
  310. master->dev.of_node = pdev->dev.of_node;
  311. master->bus_num = pdev->id;
  312. master->num_chipselect = num_cs;
  313. master->mode_bits = SPI_CPHA | SPI_CPOL
  314. | SPI_CS_HIGH | SPI_LSB_FIRST
  315. | SPI_TX_DUAL | SPI_TX_QUAD
  316. | SPI_RX_DUAL | SPI_RX_QUAD;
  317. /* TODO: add driver support for bits_per_word < 8
  318. * we need to "left-align" the bits (unless SPI_LSB_FIRST)
  319. */
  320. master->bits_per_word_mask = SPI_BPW_MASK(8);
  321. master->flags = SPI_CONTROLLER_MUST_TX | SPI_MASTER_GPIO_SS;
  322. master->prepare_message = sifive_spi_prepare_message;
  323. master->set_cs = sifive_spi_set_cs;
  324. master->transfer_one = sifive_spi_transfer_one;
  325. pdev->dev.dma_mask = NULL;
  326. /* Configure the SPI master hardware */
  327. sifive_spi_init(spi);
  328. /* Register for SPI Interrupt */
  329. ret = devm_request_irq(&pdev->dev, irq, sifive_spi_irq, 0,
  330. dev_name(&pdev->dev), spi);
  331. if (ret) {
  332. dev_err(&pdev->dev, "Unable to bind to interrupt\n");
  333. goto disable_clk;
  334. }
  335. dev_info(&pdev->dev, "mapped; irq=%d, cs=%d\n",
  336. irq, master->num_chipselect);
  337. ret = devm_spi_register_master(&pdev->dev, master);
  338. if (ret < 0) {
  339. dev_err(&pdev->dev, "spi_register_master failed\n");
  340. goto disable_clk;
  341. }
  342. return 0;
  343. disable_clk:
  344. clk_disable_unprepare(spi->clk);
  345. put_master:
  346. spi_master_put(master);
  347. return ret;
  348. }
  349. static int sifive_spi_remove(struct platform_device *pdev)
  350. {
  351. struct spi_master *master = platform_get_drvdata(pdev);
  352. struct sifive_spi *spi = spi_master_get_devdata(master);
  353. /* Disable all the interrupts just in case */
  354. sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
  355. clk_disable_unprepare(spi->clk);
  356. return 0;
  357. }
  358. static const struct of_device_id sifive_spi_of_match[] = {
  359. { .compatible = "sifive,spi0", },
  360. {}
  361. };
  362. MODULE_DEVICE_TABLE(of, sifive_spi_of_match);
  363. static struct platform_driver sifive_spi_driver = {
  364. .probe = sifive_spi_probe,
  365. .remove = sifive_spi_remove,
  366. .driver = {
  367. .name = SIFIVE_SPI_DRIVER_NAME,
  368. .of_match_table = sifive_spi_of_match,
  369. },
  370. };
  371. module_platform_driver(sifive_spi_driver);
  372. MODULE_AUTHOR("SiFive, Inc. <sifive@sifive.com>");
  373. MODULE_DESCRIPTION("SiFive SPI driver");
  374. MODULE_LICENSE("GPL");