spi-sh.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SH SPI bus driver
  4. *
  5. * Copyright (C) 2011 Renesas Solutions Corp.
  6. *
  7. * Based on pxa2xx_spi.c:
  8. * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/sched.h>
  13. #include <linux/errno.h>
  14. #include <linux/timer.h>
  15. #include <linux/delay.h>
  16. #include <linux/list.h>
  17. #include <linux/workqueue.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/io.h>
  21. #include <linux/spi/spi.h>
  22. #define SPI_SH_TBR 0x00
  23. #define SPI_SH_RBR 0x00
  24. #define SPI_SH_CR1 0x08
  25. #define SPI_SH_CR2 0x10
  26. #define SPI_SH_CR3 0x18
  27. #define SPI_SH_CR4 0x20
  28. #define SPI_SH_CR5 0x28
  29. /* CR1 */
  30. #define SPI_SH_TBE 0x80
  31. #define SPI_SH_TBF 0x40
  32. #define SPI_SH_RBE 0x20
  33. #define SPI_SH_RBF 0x10
  34. #define SPI_SH_PFONRD 0x08
  35. #define SPI_SH_SSDB 0x04
  36. #define SPI_SH_SSD 0x02
  37. #define SPI_SH_SSA 0x01
  38. /* CR2 */
  39. #define SPI_SH_RSTF 0x80
  40. #define SPI_SH_LOOPBK 0x40
  41. #define SPI_SH_CPOL 0x20
  42. #define SPI_SH_CPHA 0x10
  43. #define SPI_SH_L1M0 0x08
  44. /* CR3 */
  45. #define SPI_SH_MAX_BYTE 0xFF
  46. /* CR4 */
  47. #define SPI_SH_TBEI 0x80
  48. #define SPI_SH_TBFI 0x40
  49. #define SPI_SH_RBEI 0x20
  50. #define SPI_SH_RBFI 0x10
  51. #define SPI_SH_WPABRT 0x04
  52. #define SPI_SH_SSS 0x01
  53. /* CR8 */
  54. #define SPI_SH_P1L0 0x80
  55. #define SPI_SH_PP1L0 0x40
  56. #define SPI_SH_MUXI 0x20
  57. #define SPI_SH_MUXIRQ 0x10
  58. #define SPI_SH_FIFO_SIZE 32
  59. #define SPI_SH_SEND_TIMEOUT (3 * HZ)
  60. #define SPI_SH_RECEIVE_TIMEOUT (HZ >> 3)
  61. #undef DEBUG
  62. struct spi_sh_data {
  63. void __iomem *addr;
  64. int irq;
  65. struct spi_master *master;
  66. struct list_head queue;
  67. struct work_struct ws;
  68. unsigned long cr1;
  69. wait_queue_head_t wait;
  70. spinlock_t lock;
  71. int width;
  72. };
  73. static void spi_sh_write(struct spi_sh_data *ss, unsigned long data,
  74. unsigned long offset)
  75. {
  76. if (ss->width == 8)
  77. iowrite8(data, ss->addr + (offset >> 2));
  78. else if (ss->width == 32)
  79. iowrite32(data, ss->addr + offset);
  80. }
  81. static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset)
  82. {
  83. if (ss->width == 8)
  84. return ioread8(ss->addr + (offset >> 2));
  85. else if (ss->width == 32)
  86. return ioread32(ss->addr + offset);
  87. else
  88. return 0;
  89. }
  90. static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val,
  91. unsigned long offset)
  92. {
  93. unsigned long tmp;
  94. tmp = spi_sh_read(ss, offset);
  95. tmp |= val;
  96. spi_sh_write(ss, tmp, offset);
  97. }
  98. static void spi_sh_clear_bit(struct spi_sh_data *ss, unsigned long val,
  99. unsigned long offset)
  100. {
  101. unsigned long tmp;
  102. tmp = spi_sh_read(ss, offset);
  103. tmp &= ~val;
  104. spi_sh_write(ss, tmp, offset);
  105. }
  106. static void clear_fifo(struct spi_sh_data *ss)
  107. {
  108. spi_sh_set_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
  109. spi_sh_clear_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
  110. }
  111. static int spi_sh_wait_receive_buffer(struct spi_sh_data *ss)
  112. {
  113. int timeout = 100000;
  114. while (spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
  115. udelay(10);
  116. if (timeout-- < 0)
  117. return -ETIMEDOUT;
  118. }
  119. return 0;
  120. }
  121. static int spi_sh_wait_write_buffer_empty(struct spi_sh_data *ss)
  122. {
  123. int timeout = 100000;
  124. while (!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBE)) {
  125. udelay(10);
  126. if (timeout-- < 0)
  127. return -ETIMEDOUT;
  128. }
  129. return 0;
  130. }
  131. static int spi_sh_send(struct spi_sh_data *ss, struct spi_message *mesg,
  132. struct spi_transfer *t)
  133. {
  134. int i, retval = 0;
  135. int remain = t->len;
  136. int cur_len;
  137. unsigned char *data;
  138. long ret;
  139. if (t->len)
  140. spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
  141. data = (unsigned char *)t->tx_buf;
  142. while (remain > 0) {
  143. cur_len = min(SPI_SH_FIFO_SIZE, remain);
  144. for (i = 0; i < cur_len &&
  145. !(spi_sh_read(ss, SPI_SH_CR4) &
  146. SPI_SH_WPABRT) &&
  147. !(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBF);
  148. i++)
  149. spi_sh_write(ss, (unsigned long)data[i], SPI_SH_TBR);
  150. if (spi_sh_read(ss, SPI_SH_CR4) & SPI_SH_WPABRT) {
  151. /* Abort SPI operation */
  152. spi_sh_set_bit(ss, SPI_SH_WPABRT, SPI_SH_CR4);
  153. retval = -EIO;
  154. break;
  155. }
  156. cur_len = i;
  157. remain -= cur_len;
  158. data += cur_len;
  159. if (remain > 0) {
  160. ss->cr1 &= ~SPI_SH_TBE;
  161. spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
  162. ret = wait_event_interruptible_timeout(ss->wait,
  163. ss->cr1 & SPI_SH_TBE,
  164. SPI_SH_SEND_TIMEOUT);
  165. if (ret == 0 && !(ss->cr1 & SPI_SH_TBE)) {
  166. printk(KERN_ERR "%s: timeout\n", __func__);
  167. return -ETIMEDOUT;
  168. }
  169. }
  170. }
  171. if (list_is_last(&t->transfer_list, &mesg->transfers)) {
  172. spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
  173. spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
  174. ss->cr1 &= ~SPI_SH_TBE;
  175. spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
  176. ret = wait_event_interruptible_timeout(ss->wait,
  177. ss->cr1 & SPI_SH_TBE,
  178. SPI_SH_SEND_TIMEOUT);
  179. if (ret == 0 && (ss->cr1 & SPI_SH_TBE)) {
  180. printk(KERN_ERR "%s: timeout\n", __func__);
  181. return -ETIMEDOUT;
  182. }
  183. }
  184. return retval;
  185. }
  186. static int spi_sh_receive(struct spi_sh_data *ss, struct spi_message *mesg,
  187. struct spi_transfer *t)
  188. {
  189. int i;
  190. int remain = t->len;
  191. int cur_len;
  192. unsigned char *data;
  193. long ret;
  194. if (t->len > SPI_SH_MAX_BYTE)
  195. spi_sh_write(ss, SPI_SH_MAX_BYTE, SPI_SH_CR3);
  196. else
  197. spi_sh_write(ss, t->len, SPI_SH_CR3);
  198. spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
  199. spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
  200. spi_sh_wait_write_buffer_empty(ss);
  201. data = (unsigned char *)t->rx_buf;
  202. while (remain > 0) {
  203. if (remain >= SPI_SH_FIFO_SIZE) {
  204. ss->cr1 &= ~SPI_SH_RBF;
  205. spi_sh_set_bit(ss, SPI_SH_RBF, SPI_SH_CR4);
  206. ret = wait_event_interruptible_timeout(ss->wait,
  207. ss->cr1 & SPI_SH_RBF,
  208. SPI_SH_RECEIVE_TIMEOUT);
  209. if (ret == 0 &&
  210. spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
  211. printk(KERN_ERR "%s: timeout\n", __func__);
  212. return -ETIMEDOUT;
  213. }
  214. }
  215. cur_len = min(SPI_SH_FIFO_SIZE, remain);
  216. for (i = 0; i < cur_len; i++) {
  217. if (spi_sh_wait_receive_buffer(ss))
  218. break;
  219. data[i] = (unsigned char)spi_sh_read(ss, SPI_SH_RBR);
  220. }
  221. remain -= cur_len;
  222. data += cur_len;
  223. }
  224. /* deassert CS when SPI is receiving. */
  225. if (t->len > SPI_SH_MAX_BYTE) {
  226. clear_fifo(ss);
  227. spi_sh_write(ss, 1, SPI_SH_CR3);
  228. } else {
  229. spi_sh_write(ss, 0, SPI_SH_CR3);
  230. }
  231. return 0;
  232. }
  233. static void spi_sh_work(struct work_struct *work)
  234. {
  235. struct spi_sh_data *ss = container_of(work, struct spi_sh_data, ws);
  236. struct spi_message *mesg;
  237. struct spi_transfer *t;
  238. unsigned long flags;
  239. int ret;
  240. pr_debug("%s: enter\n", __func__);
  241. spin_lock_irqsave(&ss->lock, flags);
  242. while (!list_empty(&ss->queue)) {
  243. mesg = list_entry(ss->queue.next, struct spi_message, queue);
  244. list_del_init(&mesg->queue);
  245. spin_unlock_irqrestore(&ss->lock, flags);
  246. list_for_each_entry(t, &mesg->transfers, transfer_list) {
  247. pr_debug("tx_buf = %p, rx_buf = %p\n",
  248. t->tx_buf, t->rx_buf);
  249. pr_debug("len = %d, delay_usecs = %d\n",
  250. t->len, t->delay_usecs);
  251. if (t->tx_buf) {
  252. ret = spi_sh_send(ss, mesg, t);
  253. if (ret < 0)
  254. goto error;
  255. }
  256. if (t->rx_buf) {
  257. ret = spi_sh_receive(ss, mesg, t);
  258. if (ret < 0)
  259. goto error;
  260. }
  261. mesg->actual_length += t->len;
  262. }
  263. spin_lock_irqsave(&ss->lock, flags);
  264. mesg->status = 0;
  265. if (mesg->complete)
  266. mesg->complete(mesg->context);
  267. }
  268. clear_fifo(ss);
  269. spi_sh_set_bit(ss, SPI_SH_SSD, SPI_SH_CR1);
  270. udelay(100);
  271. spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
  272. SPI_SH_CR1);
  273. clear_fifo(ss);
  274. spin_unlock_irqrestore(&ss->lock, flags);
  275. return;
  276. error:
  277. mesg->status = ret;
  278. if (mesg->complete)
  279. mesg->complete(mesg->context);
  280. spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
  281. SPI_SH_CR1);
  282. clear_fifo(ss);
  283. }
  284. static int spi_sh_setup(struct spi_device *spi)
  285. {
  286. struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
  287. pr_debug("%s: enter\n", __func__);
  288. spi_sh_write(ss, 0xfe, SPI_SH_CR1); /* SPI sycle stop */
  289. spi_sh_write(ss, 0x00, SPI_SH_CR1); /* CR1 init */
  290. spi_sh_write(ss, 0x00, SPI_SH_CR3); /* CR3 init */
  291. clear_fifo(ss);
  292. /* 1/8 clock */
  293. spi_sh_write(ss, spi_sh_read(ss, SPI_SH_CR2) | 0x07, SPI_SH_CR2);
  294. udelay(10);
  295. return 0;
  296. }
  297. static int spi_sh_transfer(struct spi_device *spi, struct spi_message *mesg)
  298. {
  299. struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
  300. unsigned long flags;
  301. pr_debug("%s: enter\n", __func__);
  302. pr_debug("\tmode = %02x\n", spi->mode);
  303. spin_lock_irqsave(&ss->lock, flags);
  304. mesg->actual_length = 0;
  305. mesg->status = -EINPROGRESS;
  306. spi_sh_clear_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
  307. list_add_tail(&mesg->queue, &ss->queue);
  308. schedule_work(&ss->ws);
  309. spin_unlock_irqrestore(&ss->lock, flags);
  310. return 0;
  311. }
  312. static void spi_sh_cleanup(struct spi_device *spi)
  313. {
  314. struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
  315. pr_debug("%s: enter\n", __func__);
  316. spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
  317. SPI_SH_CR1);
  318. }
  319. static irqreturn_t spi_sh_irq(int irq, void *_ss)
  320. {
  321. struct spi_sh_data *ss = (struct spi_sh_data *)_ss;
  322. unsigned long cr1;
  323. cr1 = spi_sh_read(ss, SPI_SH_CR1);
  324. if (cr1 & SPI_SH_TBE)
  325. ss->cr1 |= SPI_SH_TBE;
  326. if (cr1 & SPI_SH_TBF)
  327. ss->cr1 |= SPI_SH_TBF;
  328. if (cr1 & SPI_SH_RBE)
  329. ss->cr1 |= SPI_SH_RBE;
  330. if (cr1 & SPI_SH_RBF)
  331. ss->cr1 |= SPI_SH_RBF;
  332. if (ss->cr1) {
  333. spi_sh_clear_bit(ss, ss->cr1, SPI_SH_CR4);
  334. wake_up(&ss->wait);
  335. }
  336. return IRQ_HANDLED;
  337. }
  338. static int spi_sh_remove(struct platform_device *pdev)
  339. {
  340. struct spi_sh_data *ss = platform_get_drvdata(pdev);
  341. spi_unregister_master(ss->master);
  342. flush_work(&ss->ws);
  343. free_irq(ss->irq, ss);
  344. return 0;
  345. }
  346. static int spi_sh_probe(struct platform_device *pdev)
  347. {
  348. struct resource *res;
  349. struct spi_master *master;
  350. struct spi_sh_data *ss;
  351. int ret, irq;
  352. /* get base addr */
  353. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  354. if (unlikely(res == NULL)) {
  355. dev_err(&pdev->dev, "invalid resource\n");
  356. return -EINVAL;
  357. }
  358. irq = platform_get_irq(pdev, 0);
  359. if (irq < 0)
  360. return irq;
  361. master = devm_spi_alloc_master(&pdev->dev, sizeof(struct spi_sh_data));
  362. if (master == NULL) {
  363. dev_err(&pdev->dev, "spi_alloc_master error.\n");
  364. return -ENOMEM;
  365. }
  366. ss = spi_master_get_devdata(master);
  367. platform_set_drvdata(pdev, ss);
  368. switch (res->flags & IORESOURCE_MEM_TYPE_MASK) {
  369. case IORESOURCE_MEM_8BIT:
  370. ss->width = 8;
  371. break;
  372. case IORESOURCE_MEM_32BIT:
  373. ss->width = 32;
  374. break;
  375. default:
  376. dev_err(&pdev->dev, "No support width\n");
  377. return -ENODEV;
  378. }
  379. ss->irq = irq;
  380. ss->master = master;
  381. ss->addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
  382. if (ss->addr == NULL) {
  383. dev_err(&pdev->dev, "ioremap error.\n");
  384. return -ENOMEM;
  385. }
  386. INIT_LIST_HEAD(&ss->queue);
  387. spin_lock_init(&ss->lock);
  388. INIT_WORK(&ss->ws, spi_sh_work);
  389. init_waitqueue_head(&ss->wait);
  390. ret = request_irq(irq, spi_sh_irq, 0, "spi_sh", ss);
  391. if (ret < 0) {
  392. dev_err(&pdev->dev, "request_irq error\n");
  393. return ret;
  394. }
  395. master->num_chipselect = 2;
  396. master->bus_num = pdev->id;
  397. master->setup = spi_sh_setup;
  398. master->transfer = spi_sh_transfer;
  399. master->cleanup = spi_sh_cleanup;
  400. ret = spi_register_master(master);
  401. if (ret < 0) {
  402. printk(KERN_ERR "spi_register_master error.\n");
  403. goto error3;
  404. }
  405. return 0;
  406. error3:
  407. free_irq(irq, ss);
  408. return ret;
  409. }
  410. static struct platform_driver spi_sh_driver = {
  411. .probe = spi_sh_probe,
  412. .remove = spi_sh_remove,
  413. .driver = {
  414. .name = "sh_spi",
  415. },
  416. };
  417. module_platform_driver(spi_sh_driver);
  418. MODULE_DESCRIPTION("SH SPI bus driver");
  419. MODULE_LICENSE("GPL v2");
  420. MODULE_AUTHOR("Yoshihiro Shimoda");
  421. MODULE_ALIAS("platform:sh_spi");