spi-sh-msiof.c 39 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SuperH MSIOF SPI Controller Interface
  4. *
  5. * Copyright (c) 2009 Magnus Damm
  6. * Copyright (C) 2014 Renesas Electronics Corporation
  7. * Copyright (C) 2014-2017 Glider bvba
  8. */
  9. #include <linux/bitmap.h>
  10. #include <linux/clk.h>
  11. #include <linux/completion.h>
  12. #include <linux/delay.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/dmaengine.h>
  15. #include <linux/err.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <linux/iopoll.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/of.h>
  22. #include <linux/of_device.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/pm_runtime.h>
  25. #include <linux/sh_dma.h>
  26. #include <linux/spi/sh_msiof.h>
  27. #include <linux/spi/spi.h>
  28. #include <asm/unaligned.h>
  29. struct sh_msiof_chipdata {
  30. u32 bits_per_word_mask;
  31. u16 tx_fifo_size;
  32. u16 rx_fifo_size;
  33. u16 ctlr_flags;
  34. u16 min_div_pow;
  35. };
  36. struct sh_msiof_spi_priv {
  37. struct spi_controller *ctlr;
  38. void __iomem *mapbase;
  39. struct clk *clk;
  40. struct platform_device *pdev;
  41. struct sh_msiof_spi_info *info;
  42. struct completion done;
  43. struct completion done_txdma;
  44. unsigned int tx_fifo_size;
  45. unsigned int rx_fifo_size;
  46. unsigned int min_div_pow;
  47. void *tx_dma_page;
  48. void *rx_dma_page;
  49. dma_addr_t tx_dma_addr;
  50. dma_addr_t rx_dma_addr;
  51. bool native_cs_inited;
  52. bool native_cs_high;
  53. bool slave_aborted;
  54. };
  55. #define MAX_SS 3 /* Maximum number of native chip selects */
  56. #define SITMDR1 0x00 /* Transmit Mode Register 1 */
  57. #define SITMDR2 0x04 /* Transmit Mode Register 2 */
  58. #define SITMDR3 0x08 /* Transmit Mode Register 3 */
  59. #define SIRMDR1 0x10 /* Receive Mode Register 1 */
  60. #define SIRMDR2 0x14 /* Receive Mode Register 2 */
  61. #define SIRMDR3 0x18 /* Receive Mode Register 3 */
  62. #define SITSCR 0x20 /* Transmit Clock Select Register */
  63. #define SIRSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
  64. #define SICTR 0x28 /* Control Register */
  65. #define SIFCTR 0x30 /* FIFO Control Register */
  66. #define SISTR 0x40 /* Status Register */
  67. #define SIIER 0x44 /* Interrupt Enable Register */
  68. #define SITDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
  69. #define SITDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
  70. #define SITFDR 0x50 /* Transmit FIFO Data Register */
  71. #define SIRDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
  72. #define SIRDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
  73. #define SIRFDR 0x60 /* Receive FIFO Data Register */
  74. /* SITMDR1 and SIRMDR1 */
  75. #define SIMDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */
  76. #define SIMDR1_SYNCMD_MASK GENMASK(29, 28) /* SYNC Mode */
  77. #define SIMDR1_SYNCMD_SPI (2 << 28) /* Level mode/SPI */
  78. #define SIMDR1_SYNCMD_LR (3 << 28) /* L/R mode */
  79. #define SIMDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
  80. #define SIMDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
  81. #define SIMDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
  82. #define SIMDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
  83. #define SIMDR1_FLD_MASK GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
  84. #define SIMDR1_FLD_SHIFT 2
  85. #define SIMDR1_XXSTP BIT(0) /* Transmission/Reception Stop on FIFO */
  86. /* SITMDR1 */
  87. #define SITMDR1_PCON BIT(30) /* Transfer Signal Connection */
  88. #define SITMDR1_SYNCCH_MASK GENMASK(27, 26) /* Sync Signal Channel Select */
  89. #define SITMDR1_SYNCCH_SHIFT 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
  90. /* SITMDR2 and SIRMDR2 */
  91. #define SIMDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
  92. #define SIMDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
  93. #define SIMDR2_GRPMASK1 BIT(0) /* Group Output Mask 1 (SH, A1) */
  94. /* SITSCR and SIRSCR */
  95. #define SISCR_BRPS_MASK GENMASK(12, 8) /* Prescaler Setting (1-32) */
  96. #define SISCR_BRPS(i) (((i) - 1) << 8)
  97. #define SISCR_BRDV_MASK GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */
  98. #define SISCR_BRDV_DIV_2 0
  99. #define SISCR_BRDV_DIV_4 1
  100. #define SISCR_BRDV_DIV_8 2
  101. #define SISCR_BRDV_DIV_16 3
  102. #define SISCR_BRDV_DIV_32 4
  103. #define SISCR_BRDV_DIV_1 7
  104. /* SICTR */
  105. #define SICTR_TSCKIZ_MASK GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */
  106. #define SICTR_TSCKIZ_SCK BIT(31) /* Disable SCK when TX disabled */
  107. #define SICTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
  108. #define SICTR_RSCKIZ_MASK GENMASK(29, 28) /* Receive Clock Polarity Select */
  109. #define SICTR_RSCKIZ_SCK BIT(29) /* Must match CTR_TSCKIZ_SCK */
  110. #define SICTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
  111. #define SICTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
  112. #define SICTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
  113. #define SICTR_TXDIZ_MASK GENMASK(23, 22) /* Pin Output When TX is Disabled */
  114. #define SICTR_TXDIZ_LOW (0 << 22) /* 0 */
  115. #define SICTR_TXDIZ_HIGH (1 << 22) /* 1 */
  116. #define SICTR_TXDIZ_HIZ (2 << 22) /* High-impedance */
  117. #define SICTR_TSCKE BIT(15) /* Transmit Serial Clock Output Enable */
  118. #define SICTR_TFSE BIT(14) /* Transmit Frame Sync Signal Output Enable */
  119. #define SICTR_TXE BIT(9) /* Transmit Enable */
  120. #define SICTR_RXE BIT(8) /* Receive Enable */
  121. #define SICTR_TXRST BIT(1) /* Transmit Reset */
  122. #define SICTR_RXRST BIT(0) /* Receive Reset */
  123. /* SIFCTR */
  124. #define SIFCTR_TFWM_MASK GENMASK(31, 29) /* Transmit FIFO Watermark */
  125. #define SIFCTR_TFWM_64 (0 << 29) /* Transfer Request when 64 empty stages */
  126. #define SIFCTR_TFWM_32 (1 << 29) /* Transfer Request when 32 empty stages */
  127. #define SIFCTR_TFWM_24 (2 << 29) /* Transfer Request when 24 empty stages */
  128. #define SIFCTR_TFWM_16 (3 << 29) /* Transfer Request when 16 empty stages */
  129. #define SIFCTR_TFWM_12 (4 << 29) /* Transfer Request when 12 empty stages */
  130. #define SIFCTR_TFWM_8 (5 << 29) /* Transfer Request when 8 empty stages */
  131. #define SIFCTR_TFWM_4 (6 << 29) /* Transfer Request when 4 empty stages */
  132. #define SIFCTR_TFWM_1 (7 << 29) /* Transfer Request when 1 empty stage */
  133. #define SIFCTR_TFUA_MASK GENMASK(26, 20) /* Transmit FIFO Usable Area */
  134. #define SIFCTR_TFUA_SHIFT 20
  135. #define SIFCTR_TFUA(i) ((i) << SIFCTR_TFUA_SHIFT)
  136. #define SIFCTR_RFWM_MASK GENMASK(15, 13) /* Receive FIFO Watermark */
  137. #define SIFCTR_RFWM_1 (0 << 13) /* Transfer Request when 1 valid stages */
  138. #define SIFCTR_RFWM_4 (1 << 13) /* Transfer Request when 4 valid stages */
  139. #define SIFCTR_RFWM_8 (2 << 13) /* Transfer Request when 8 valid stages */
  140. #define SIFCTR_RFWM_16 (3 << 13) /* Transfer Request when 16 valid stages */
  141. #define SIFCTR_RFWM_32 (4 << 13) /* Transfer Request when 32 valid stages */
  142. #define SIFCTR_RFWM_64 (5 << 13) /* Transfer Request when 64 valid stages */
  143. #define SIFCTR_RFWM_128 (6 << 13) /* Transfer Request when 128 valid stages */
  144. #define SIFCTR_RFWM_256 (7 << 13) /* Transfer Request when 256 valid stages */
  145. #define SIFCTR_RFUA_MASK GENMASK(12, 4) /* Receive FIFO Usable Area (0x40 = full) */
  146. #define SIFCTR_RFUA_SHIFT 4
  147. #define SIFCTR_RFUA(i) ((i) << SIFCTR_RFUA_SHIFT)
  148. /* SISTR */
  149. #define SISTR_TFEMP BIT(29) /* Transmit FIFO Empty */
  150. #define SISTR_TDREQ BIT(28) /* Transmit Data Transfer Request */
  151. #define SISTR_TEOF BIT(23) /* Frame Transmission End */
  152. #define SISTR_TFSERR BIT(21) /* Transmit Frame Synchronization Error */
  153. #define SISTR_TFOVF BIT(20) /* Transmit FIFO Overflow */
  154. #define SISTR_TFUDF BIT(19) /* Transmit FIFO Underflow */
  155. #define SISTR_RFFUL BIT(13) /* Receive FIFO Full */
  156. #define SISTR_RDREQ BIT(12) /* Receive Data Transfer Request */
  157. #define SISTR_REOF BIT(7) /* Frame Reception End */
  158. #define SISTR_RFSERR BIT(5) /* Receive Frame Synchronization Error */
  159. #define SISTR_RFUDF BIT(4) /* Receive FIFO Underflow */
  160. #define SISTR_RFOVF BIT(3) /* Receive FIFO Overflow */
  161. /* SIIER */
  162. #define SIIER_TDMAE BIT(31) /* Transmit Data DMA Transfer Req. Enable */
  163. #define SIIER_TFEMPE BIT(29) /* Transmit FIFO Empty Enable */
  164. #define SIIER_TDREQE BIT(28) /* Transmit Data Transfer Request Enable */
  165. #define SIIER_TEOFE BIT(23) /* Frame Transmission End Enable */
  166. #define SIIER_TFSERRE BIT(21) /* Transmit Frame Sync Error Enable */
  167. #define SIIER_TFOVFE BIT(20) /* Transmit FIFO Overflow Enable */
  168. #define SIIER_TFUDFE BIT(19) /* Transmit FIFO Underflow Enable */
  169. #define SIIER_RDMAE BIT(15) /* Receive Data DMA Transfer Req. Enable */
  170. #define SIIER_RFFULE BIT(13) /* Receive FIFO Full Enable */
  171. #define SIIER_RDREQE BIT(12) /* Receive Data Transfer Request Enable */
  172. #define SIIER_REOFE BIT(7) /* Frame Reception End Enable */
  173. #define SIIER_RFSERRE BIT(5) /* Receive Frame Sync Error Enable */
  174. #define SIIER_RFUDFE BIT(4) /* Receive FIFO Underflow Enable */
  175. #define SIIER_RFOVFE BIT(3) /* Receive FIFO Overflow Enable */
  176. static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
  177. {
  178. switch (reg_offs) {
  179. case SITSCR:
  180. case SIRSCR:
  181. return ioread16(p->mapbase + reg_offs);
  182. default:
  183. return ioread32(p->mapbase + reg_offs);
  184. }
  185. }
  186. static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
  187. u32 value)
  188. {
  189. switch (reg_offs) {
  190. case SITSCR:
  191. case SIRSCR:
  192. iowrite16(value, p->mapbase + reg_offs);
  193. break;
  194. default:
  195. iowrite32(value, p->mapbase + reg_offs);
  196. break;
  197. }
  198. }
  199. static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
  200. u32 clr, u32 set)
  201. {
  202. u32 mask = clr | set;
  203. u32 data;
  204. data = sh_msiof_read(p, SICTR);
  205. data &= ~clr;
  206. data |= set;
  207. sh_msiof_write(p, SICTR, data);
  208. return readl_poll_timeout_atomic(p->mapbase + SICTR, data,
  209. (data & mask) == set, 1, 100);
  210. }
  211. static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
  212. {
  213. struct sh_msiof_spi_priv *p = data;
  214. /* just disable the interrupt and wake up */
  215. sh_msiof_write(p, SIIER, 0);
  216. complete(&p->done);
  217. return IRQ_HANDLED;
  218. }
  219. static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p)
  220. {
  221. u32 mask = SICTR_TXRST | SICTR_RXRST;
  222. u32 data;
  223. data = sh_msiof_read(p, SICTR);
  224. data |= mask;
  225. sh_msiof_write(p, SICTR, data);
  226. readl_poll_timeout_atomic(p->mapbase + SICTR, data, !(data & mask), 1,
  227. 100);
  228. }
  229. static const u32 sh_msiof_spi_div_array[] = {
  230. SISCR_BRDV_DIV_1, SISCR_BRDV_DIV_2, SISCR_BRDV_DIV_4,
  231. SISCR_BRDV_DIV_8, SISCR_BRDV_DIV_16, SISCR_BRDV_DIV_32,
  232. };
  233. static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
  234. unsigned long parent_rate, u32 spi_hz)
  235. {
  236. unsigned long div;
  237. u32 brps, scr;
  238. unsigned int div_pow = p->min_div_pow;
  239. if (!spi_hz || !parent_rate) {
  240. WARN(1, "Invalid clock rate parameters %lu and %u\n",
  241. parent_rate, spi_hz);
  242. return;
  243. }
  244. div = DIV_ROUND_UP(parent_rate, spi_hz);
  245. if (div <= 1024) {
  246. /* SISCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
  247. if (!div_pow && div <= 32 && div > 2)
  248. div_pow = 1;
  249. if (div_pow)
  250. brps = (div + 1) >> div_pow;
  251. else
  252. brps = div;
  253. for (; brps > 32; div_pow++)
  254. brps = (brps + 1) >> 1;
  255. } else {
  256. /* Set transfer rate composite divisor to 2^5 * 32 = 1024 */
  257. dev_err(&p->pdev->dev,
  258. "Requested SPI transfer rate %d is too low\n", spi_hz);
  259. div_pow = 5;
  260. brps = 32;
  261. }
  262. scr = sh_msiof_spi_div_array[div_pow] | SISCR_BRPS(brps);
  263. sh_msiof_write(p, SITSCR, scr);
  264. if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
  265. sh_msiof_write(p, SIRSCR, scr);
  266. }
  267. static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
  268. {
  269. /*
  270. * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
  271. * b'000 : 0
  272. * b'001 : 100
  273. * b'010 : 200
  274. * b'011 (SYNCDL only) : 300
  275. * b'101 : 50
  276. * b'110 : 150
  277. */
  278. if (dtdl_or_syncdl % 100)
  279. return dtdl_or_syncdl / 100 + 5;
  280. else
  281. return dtdl_or_syncdl / 100;
  282. }
  283. static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
  284. {
  285. u32 val;
  286. if (!p->info)
  287. return 0;
  288. /* check if DTDL and SYNCDL is allowed value */
  289. if (p->info->dtdl > 200 || p->info->syncdl > 300) {
  290. dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
  291. return 0;
  292. }
  293. /* check if the sum of DTDL and SYNCDL becomes an integer value */
  294. if ((p->info->dtdl + p->info->syncdl) % 100) {
  295. dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
  296. return 0;
  297. }
  298. val = sh_msiof_get_delay_bit(p->info->dtdl) << SIMDR1_DTDL_SHIFT;
  299. val |= sh_msiof_get_delay_bit(p->info->syncdl) << SIMDR1_SYNCDL_SHIFT;
  300. return val;
  301. }
  302. static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss,
  303. u32 cpol, u32 cpha,
  304. u32 tx_hi_z, u32 lsb_first, u32 cs_high)
  305. {
  306. u32 tmp;
  307. int edge;
  308. /*
  309. * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
  310. * 0 0 10 10 1 1
  311. * 0 1 10 10 0 0
  312. * 1 0 11 11 0 0
  313. * 1 1 11 11 1 1
  314. */
  315. tmp = SIMDR1_SYNCMD_SPI | 1 << SIMDR1_FLD_SHIFT | SIMDR1_XXSTP;
  316. tmp |= !cs_high << SIMDR1_SYNCAC_SHIFT;
  317. tmp |= lsb_first << SIMDR1_BITLSB_SHIFT;
  318. tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
  319. if (spi_controller_is_slave(p->ctlr)) {
  320. sh_msiof_write(p, SITMDR1, tmp | SITMDR1_PCON);
  321. } else {
  322. sh_msiof_write(p, SITMDR1,
  323. tmp | SIMDR1_TRMD | SITMDR1_PCON |
  324. (ss < MAX_SS ? ss : 0) << SITMDR1_SYNCCH_SHIFT);
  325. }
  326. if (p->ctlr->flags & SPI_CONTROLLER_MUST_TX) {
  327. /* These bits are reserved if RX needs TX */
  328. tmp &= ~0x0000ffff;
  329. }
  330. sh_msiof_write(p, SIRMDR1, tmp);
  331. tmp = 0;
  332. tmp |= SICTR_TSCKIZ_SCK | cpol << SICTR_TSCKIZ_POL_SHIFT;
  333. tmp |= SICTR_RSCKIZ_SCK | cpol << SICTR_RSCKIZ_POL_SHIFT;
  334. edge = cpol ^ !cpha;
  335. tmp |= edge << SICTR_TEDG_SHIFT;
  336. tmp |= edge << SICTR_REDG_SHIFT;
  337. tmp |= tx_hi_z ? SICTR_TXDIZ_HIZ : SICTR_TXDIZ_LOW;
  338. sh_msiof_write(p, SICTR, tmp);
  339. }
  340. static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
  341. const void *tx_buf, void *rx_buf,
  342. u32 bits, u32 words)
  343. {
  344. u32 dr2 = SIMDR2_BITLEN1(bits) | SIMDR2_WDLEN1(words);
  345. if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
  346. sh_msiof_write(p, SITMDR2, dr2);
  347. else
  348. sh_msiof_write(p, SITMDR2, dr2 | SIMDR2_GRPMASK1);
  349. if (rx_buf)
  350. sh_msiof_write(p, SIRMDR2, dr2);
  351. }
  352. static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
  353. {
  354. sh_msiof_write(p, SISTR,
  355. sh_msiof_read(p, SISTR) & ~(SISTR_TDREQ | SISTR_RDREQ));
  356. }
  357. static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
  358. const void *tx_buf, int words, int fs)
  359. {
  360. const u8 *buf_8 = tx_buf;
  361. int k;
  362. for (k = 0; k < words; k++)
  363. sh_msiof_write(p, SITFDR, buf_8[k] << fs);
  364. }
  365. static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
  366. const void *tx_buf, int words, int fs)
  367. {
  368. const u16 *buf_16 = tx_buf;
  369. int k;
  370. for (k = 0; k < words; k++)
  371. sh_msiof_write(p, SITFDR, buf_16[k] << fs);
  372. }
  373. static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
  374. const void *tx_buf, int words, int fs)
  375. {
  376. const u16 *buf_16 = tx_buf;
  377. int k;
  378. for (k = 0; k < words; k++)
  379. sh_msiof_write(p, SITFDR, get_unaligned(&buf_16[k]) << fs);
  380. }
  381. static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
  382. const void *tx_buf, int words, int fs)
  383. {
  384. const u32 *buf_32 = tx_buf;
  385. int k;
  386. for (k = 0; k < words; k++)
  387. sh_msiof_write(p, SITFDR, buf_32[k] << fs);
  388. }
  389. static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
  390. const void *tx_buf, int words, int fs)
  391. {
  392. const u32 *buf_32 = tx_buf;
  393. int k;
  394. for (k = 0; k < words; k++)
  395. sh_msiof_write(p, SITFDR, get_unaligned(&buf_32[k]) << fs);
  396. }
  397. static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
  398. const void *tx_buf, int words, int fs)
  399. {
  400. const u32 *buf_32 = tx_buf;
  401. int k;
  402. for (k = 0; k < words; k++)
  403. sh_msiof_write(p, SITFDR, swab32(buf_32[k] << fs));
  404. }
  405. static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
  406. const void *tx_buf, int words, int fs)
  407. {
  408. const u32 *buf_32 = tx_buf;
  409. int k;
  410. for (k = 0; k < words; k++)
  411. sh_msiof_write(p, SITFDR, swab32(get_unaligned(&buf_32[k]) << fs));
  412. }
  413. static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
  414. void *rx_buf, int words, int fs)
  415. {
  416. u8 *buf_8 = rx_buf;
  417. int k;
  418. for (k = 0; k < words; k++)
  419. buf_8[k] = sh_msiof_read(p, SIRFDR) >> fs;
  420. }
  421. static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
  422. void *rx_buf, int words, int fs)
  423. {
  424. u16 *buf_16 = rx_buf;
  425. int k;
  426. for (k = 0; k < words; k++)
  427. buf_16[k] = sh_msiof_read(p, SIRFDR) >> fs;
  428. }
  429. static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
  430. void *rx_buf, int words, int fs)
  431. {
  432. u16 *buf_16 = rx_buf;
  433. int k;
  434. for (k = 0; k < words; k++)
  435. put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_16[k]);
  436. }
  437. static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
  438. void *rx_buf, int words, int fs)
  439. {
  440. u32 *buf_32 = rx_buf;
  441. int k;
  442. for (k = 0; k < words; k++)
  443. buf_32[k] = sh_msiof_read(p, SIRFDR) >> fs;
  444. }
  445. static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
  446. void *rx_buf, int words, int fs)
  447. {
  448. u32 *buf_32 = rx_buf;
  449. int k;
  450. for (k = 0; k < words; k++)
  451. put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_32[k]);
  452. }
  453. static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
  454. void *rx_buf, int words, int fs)
  455. {
  456. u32 *buf_32 = rx_buf;
  457. int k;
  458. for (k = 0; k < words; k++)
  459. buf_32[k] = swab32(sh_msiof_read(p, SIRFDR) >> fs);
  460. }
  461. static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
  462. void *rx_buf, int words, int fs)
  463. {
  464. u32 *buf_32 = rx_buf;
  465. int k;
  466. for (k = 0; k < words; k++)
  467. put_unaligned(swab32(sh_msiof_read(p, SIRFDR) >> fs), &buf_32[k]);
  468. }
  469. static int sh_msiof_spi_setup(struct spi_device *spi)
  470. {
  471. struct sh_msiof_spi_priv *p =
  472. spi_controller_get_devdata(spi->controller);
  473. u32 clr, set, tmp;
  474. if (spi->cs_gpiod || spi_controller_is_slave(p->ctlr))
  475. return 0;
  476. if (p->native_cs_inited &&
  477. (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH)))
  478. return 0;
  479. /* Configure native chip select mode/polarity early */
  480. clr = SIMDR1_SYNCMD_MASK;
  481. set = SIMDR1_SYNCMD_SPI;
  482. if (spi->mode & SPI_CS_HIGH)
  483. clr |= BIT(SIMDR1_SYNCAC_SHIFT);
  484. else
  485. set |= BIT(SIMDR1_SYNCAC_SHIFT);
  486. pm_runtime_get_sync(&p->pdev->dev);
  487. tmp = sh_msiof_read(p, SITMDR1) & ~clr;
  488. sh_msiof_write(p, SITMDR1, tmp | set | SIMDR1_TRMD | SITMDR1_PCON);
  489. tmp = sh_msiof_read(p, SIRMDR1) & ~clr;
  490. sh_msiof_write(p, SIRMDR1, tmp | set);
  491. pm_runtime_put(&p->pdev->dev);
  492. p->native_cs_high = spi->mode & SPI_CS_HIGH;
  493. p->native_cs_inited = true;
  494. return 0;
  495. }
  496. static int sh_msiof_prepare_message(struct spi_controller *ctlr,
  497. struct spi_message *msg)
  498. {
  499. struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
  500. const struct spi_device *spi = msg->spi;
  501. u32 ss, cs_high;
  502. /* Configure pins before asserting CS */
  503. if (spi->cs_gpiod) {
  504. ss = ctlr->unused_native_cs;
  505. cs_high = p->native_cs_high;
  506. } else {
  507. ss = spi->chip_select;
  508. cs_high = !!(spi->mode & SPI_CS_HIGH);
  509. }
  510. sh_msiof_spi_set_pin_regs(p, ss, !!(spi->mode & SPI_CPOL),
  511. !!(spi->mode & SPI_CPHA),
  512. !!(spi->mode & SPI_3WIRE),
  513. !!(spi->mode & SPI_LSB_FIRST), cs_high);
  514. return 0;
  515. }
  516. static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
  517. {
  518. bool slave = spi_controller_is_slave(p->ctlr);
  519. int ret = 0;
  520. /* setup clock and rx/tx signals */
  521. if (!slave)
  522. ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TSCKE);
  523. if (rx_buf && !ret)
  524. ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_RXE);
  525. if (!ret)
  526. ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TXE);
  527. /* start by setting frame bit */
  528. if (!ret && !slave)
  529. ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TFSE);
  530. return ret;
  531. }
  532. static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
  533. {
  534. bool slave = spi_controller_is_slave(p->ctlr);
  535. int ret = 0;
  536. /* shut down frame, rx/tx and clock signals */
  537. if (!slave)
  538. ret = sh_msiof_modify_ctr_wait(p, SICTR_TFSE, 0);
  539. if (!ret)
  540. ret = sh_msiof_modify_ctr_wait(p, SICTR_TXE, 0);
  541. if (rx_buf && !ret)
  542. ret = sh_msiof_modify_ctr_wait(p, SICTR_RXE, 0);
  543. if (!ret && !slave)
  544. ret = sh_msiof_modify_ctr_wait(p, SICTR_TSCKE, 0);
  545. return ret;
  546. }
  547. static int sh_msiof_slave_abort(struct spi_controller *ctlr)
  548. {
  549. struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
  550. p->slave_aborted = true;
  551. complete(&p->done);
  552. complete(&p->done_txdma);
  553. return 0;
  554. }
  555. static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p,
  556. struct completion *x)
  557. {
  558. if (spi_controller_is_slave(p->ctlr)) {
  559. if (wait_for_completion_interruptible(x) ||
  560. p->slave_aborted) {
  561. dev_dbg(&p->pdev->dev, "interrupted\n");
  562. return -EINTR;
  563. }
  564. } else {
  565. if (!wait_for_completion_timeout(x, HZ)) {
  566. dev_err(&p->pdev->dev, "timeout\n");
  567. return -ETIMEDOUT;
  568. }
  569. }
  570. return 0;
  571. }
  572. static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
  573. void (*tx_fifo)(struct sh_msiof_spi_priv *,
  574. const void *, int, int),
  575. void (*rx_fifo)(struct sh_msiof_spi_priv *,
  576. void *, int, int),
  577. const void *tx_buf, void *rx_buf,
  578. int words, int bits)
  579. {
  580. int fifo_shift;
  581. int ret;
  582. /* limit maximum word transfer to rx/tx fifo size */
  583. if (tx_buf)
  584. words = min_t(int, words, p->tx_fifo_size);
  585. if (rx_buf)
  586. words = min_t(int, words, p->rx_fifo_size);
  587. /* the fifo contents need shifting */
  588. fifo_shift = 32 - bits;
  589. /* default FIFO watermarks for PIO */
  590. sh_msiof_write(p, SIFCTR, 0);
  591. /* setup msiof transfer mode registers */
  592. sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
  593. sh_msiof_write(p, SIIER, SIIER_TEOFE | SIIER_REOFE);
  594. /* write tx fifo */
  595. if (tx_buf)
  596. tx_fifo(p, tx_buf, words, fifo_shift);
  597. reinit_completion(&p->done);
  598. p->slave_aborted = false;
  599. ret = sh_msiof_spi_start(p, rx_buf);
  600. if (ret) {
  601. dev_err(&p->pdev->dev, "failed to start hardware\n");
  602. goto stop_ier;
  603. }
  604. /* wait for tx fifo to be emptied / rx fifo to be filled */
  605. ret = sh_msiof_wait_for_completion(p, &p->done);
  606. if (ret)
  607. goto stop_reset;
  608. /* read rx fifo */
  609. if (rx_buf)
  610. rx_fifo(p, rx_buf, words, fifo_shift);
  611. /* clear status bits */
  612. sh_msiof_reset_str(p);
  613. ret = sh_msiof_spi_stop(p, rx_buf);
  614. if (ret) {
  615. dev_err(&p->pdev->dev, "failed to shut down hardware\n");
  616. return ret;
  617. }
  618. return words;
  619. stop_reset:
  620. sh_msiof_reset_str(p);
  621. sh_msiof_spi_stop(p, rx_buf);
  622. stop_ier:
  623. sh_msiof_write(p, SIIER, 0);
  624. return ret;
  625. }
  626. static void sh_msiof_dma_complete(void *arg)
  627. {
  628. complete(arg);
  629. }
  630. static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
  631. void *rx, unsigned int len)
  632. {
  633. u32 ier_bits = 0;
  634. struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
  635. dma_cookie_t cookie;
  636. int ret;
  637. /* First prepare and submit the DMA request(s), as this may fail */
  638. if (rx) {
  639. ier_bits |= SIIER_RDREQE | SIIER_RDMAE;
  640. desc_rx = dmaengine_prep_slave_single(p->ctlr->dma_rx,
  641. p->rx_dma_addr, len, DMA_DEV_TO_MEM,
  642. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  643. if (!desc_rx)
  644. return -EAGAIN;
  645. desc_rx->callback = sh_msiof_dma_complete;
  646. desc_rx->callback_param = &p->done;
  647. cookie = dmaengine_submit(desc_rx);
  648. if (dma_submit_error(cookie))
  649. return cookie;
  650. }
  651. if (tx) {
  652. ier_bits |= SIIER_TDREQE | SIIER_TDMAE;
  653. dma_sync_single_for_device(p->ctlr->dma_tx->device->dev,
  654. p->tx_dma_addr, len, DMA_TO_DEVICE);
  655. desc_tx = dmaengine_prep_slave_single(p->ctlr->dma_tx,
  656. p->tx_dma_addr, len, DMA_MEM_TO_DEV,
  657. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  658. if (!desc_tx) {
  659. ret = -EAGAIN;
  660. goto no_dma_tx;
  661. }
  662. desc_tx->callback = sh_msiof_dma_complete;
  663. desc_tx->callback_param = &p->done_txdma;
  664. cookie = dmaengine_submit(desc_tx);
  665. if (dma_submit_error(cookie)) {
  666. ret = cookie;
  667. goto no_dma_tx;
  668. }
  669. }
  670. /* 1 stage FIFO watermarks for DMA */
  671. sh_msiof_write(p, SIFCTR, SIFCTR_TFWM_1 | SIFCTR_RFWM_1);
  672. /* setup msiof transfer mode registers (32-bit words) */
  673. sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
  674. sh_msiof_write(p, SIIER, ier_bits);
  675. reinit_completion(&p->done);
  676. if (tx)
  677. reinit_completion(&p->done_txdma);
  678. p->slave_aborted = false;
  679. /* Now start DMA */
  680. if (rx)
  681. dma_async_issue_pending(p->ctlr->dma_rx);
  682. if (tx)
  683. dma_async_issue_pending(p->ctlr->dma_tx);
  684. ret = sh_msiof_spi_start(p, rx);
  685. if (ret) {
  686. dev_err(&p->pdev->dev, "failed to start hardware\n");
  687. goto stop_dma;
  688. }
  689. if (tx) {
  690. /* wait for tx DMA completion */
  691. ret = sh_msiof_wait_for_completion(p, &p->done_txdma);
  692. if (ret)
  693. goto stop_reset;
  694. }
  695. if (rx) {
  696. /* wait for rx DMA completion */
  697. ret = sh_msiof_wait_for_completion(p, &p->done);
  698. if (ret)
  699. goto stop_reset;
  700. sh_msiof_write(p, SIIER, 0);
  701. } else {
  702. /* wait for tx fifo to be emptied */
  703. sh_msiof_write(p, SIIER, SIIER_TEOFE);
  704. ret = sh_msiof_wait_for_completion(p, &p->done);
  705. if (ret)
  706. goto stop_reset;
  707. }
  708. /* clear status bits */
  709. sh_msiof_reset_str(p);
  710. ret = sh_msiof_spi_stop(p, rx);
  711. if (ret) {
  712. dev_err(&p->pdev->dev, "failed to shut down hardware\n");
  713. return ret;
  714. }
  715. if (rx)
  716. dma_sync_single_for_cpu(p->ctlr->dma_rx->device->dev,
  717. p->rx_dma_addr, len, DMA_FROM_DEVICE);
  718. return 0;
  719. stop_reset:
  720. sh_msiof_reset_str(p);
  721. sh_msiof_spi_stop(p, rx);
  722. stop_dma:
  723. if (tx)
  724. dmaengine_terminate_all(p->ctlr->dma_tx);
  725. no_dma_tx:
  726. if (rx)
  727. dmaengine_terminate_all(p->ctlr->dma_rx);
  728. sh_msiof_write(p, SIIER, 0);
  729. return ret;
  730. }
  731. static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
  732. {
  733. /* src or dst can be unaligned, but not both */
  734. if ((unsigned long)src & 3) {
  735. while (words--) {
  736. *dst++ = swab32(get_unaligned(src));
  737. src++;
  738. }
  739. } else if ((unsigned long)dst & 3) {
  740. while (words--) {
  741. put_unaligned(swab32(*src++), dst);
  742. dst++;
  743. }
  744. } else {
  745. while (words--)
  746. *dst++ = swab32(*src++);
  747. }
  748. }
  749. static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
  750. {
  751. /* src or dst can be unaligned, but not both */
  752. if ((unsigned long)src & 3) {
  753. while (words--) {
  754. *dst++ = swahw32(get_unaligned(src));
  755. src++;
  756. }
  757. } else if ((unsigned long)dst & 3) {
  758. while (words--) {
  759. put_unaligned(swahw32(*src++), dst);
  760. dst++;
  761. }
  762. } else {
  763. while (words--)
  764. *dst++ = swahw32(*src++);
  765. }
  766. }
  767. static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
  768. {
  769. memcpy(dst, src, words * 4);
  770. }
  771. static int sh_msiof_transfer_one(struct spi_controller *ctlr,
  772. struct spi_device *spi,
  773. struct spi_transfer *t)
  774. {
  775. struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
  776. void (*copy32)(u32 *, const u32 *, unsigned int);
  777. void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
  778. void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
  779. const void *tx_buf = t->tx_buf;
  780. void *rx_buf = t->rx_buf;
  781. unsigned int len = t->len;
  782. unsigned int bits = t->bits_per_word;
  783. unsigned int bytes_per_word;
  784. unsigned int words;
  785. int n;
  786. bool swab;
  787. int ret;
  788. /* reset registers */
  789. sh_msiof_spi_reset_regs(p);
  790. /* setup clocks (clock already enabled in chipselect()) */
  791. if (!spi_controller_is_slave(p->ctlr))
  792. sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
  793. while (ctlr->dma_tx && len > 15) {
  794. /*
  795. * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
  796. * words, with byte resp. word swapping.
  797. */
  798. unsigned int l = 0;
  799. if (tx_buf)
  800. l = min(round_down(len, 4), p->tx_fifo_size * 4);
  801. if (rx_buf)
  802. l = min(round_down(len, 4), p->rx_fifo_size * 4);
  803. if (bits <= 8) {
  804. copy32 = copy_bswap32;
  805. } else if (bits <= 16) {
  806. copy32 = copy_wswap32;
  807. } else {
  808. copy32 = copy_plain32;
  809. }
  810. if (tx_buf)
  811. copy32(p->tx_dma_page, tx_buf, l / 4);
  812. ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
  813. if (ret == -EAGAIN) {
  814. dev_warn_once(&p->pdev->dev,
  815. "DMA not available, falling back to PIO\n");
  816. break;
  817. }
  818. if (ret)
  819. return ret;
  820. if (rx_buf) {
  821. copy32(rx_buf, p->rx_dma_page, l / 4);
  822. rx_buf += l;
  823. }
  824. if (tx_buf)
  825. tx_buf += l;
  826. len -= l;
  827. if (!len)
  828. return 0;
  829. }
  830. if (bits <= 8 && len > 15) {
  831. bits = 32;
  832. swab = true;
  833. } else {
  834. swab = false;
  835. }
  836. /* setup bytes per word and fifo read/write functions */
  837. if (bits <= 8) {
  838. bytes_per_word = 1;
  839. tx_fifo = sh_msiof_spi_write_fifo_8;
  840. rx_fifo = sh_msiof_spi_read_fifo_8;
  841. } else if (bits <= 16) {
  842. bytes_per_word = 2;
  843. if ((unsigned long)tx_buf & 0x01)
  844. tx_fifo = sh_msiof_spi_write_fifo_16u;
  845. else
  846. tx_fifo = sh_msiof_spi_write_fifo_16;
  847. if ((unsigned long)rx_buf & 0x01)
  848. rx_fifo = sh_msiof_spi_read_fifo_16u;
  849. else
  850. rx_fifo = sh_msiof_spi_read_fifo_16;
  851. } else if (swab) {
  852. bytes_per_word = 4;
  853. if ((unsigned long)tx_buf & 0x03)
  854. tx_fifo = sh_msiof_spi_write_fifo_s32u;
  855. else
  856. tx_fifo = sh_msiof_spi_write_fifo_s32;
  857. if ((unsigned long)rx_buf & 0x03)
  858. rx_fifo = sh_msiof_spi_read_fifo_s32u;
  859. else
  860. rx_fifo = sh_msiof_spi_read_fifo_s32;
  861. } else {
  862. bytes_per_word = 4;
  863. if ((unsigned long)tx_buf & 0x03)
  864. tx_fifo = sh_msiof_spi_write_fifo_32u;
  865. else
  866. tx_fifo = sh_msiof_spi_write_fifo_32;
  867. if ((unsigned long)rx_buf & 0x03)
  868. rx_fifo = sh_msiof_spi_read_fifo_32u;
  869. else
  870. rx_fifo = sh_msiof_spi_read_fifo_32;
  871. }
  872. /* transfer in fifo sized chunks */
  873. words = len / bytes_per_word;
  874. while (words > 0) {
  875. n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
  876. words, bits);
  877. if (n < 0)
  878. return n;
  879. if (tx_buf)
  880. tx_buf += n * bytes_per_word;
  881. if (rx_buf)
  882. rx_buf += n * bytes_per_word;
  883. words -= n;
  884. if (words == 0 && (len % bytes_per_word)) {
  885. words = len % bytes_per_word;
  886. bits = t->bits_per_word;
  887. bytes_per_word = 1;
  888. tx_fifo = sh_msiof_spi_write_fifo_8;
  889. rx_fifo = sh_msiof_spi_read_fifo_8;
  890. }
  891. }
  892. return 0;
  893. }
  894. static const struct sh_msiof_chipdata sh_data = {
  895. .bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32),
  896. .tx_fifo_size = 64,
  897. .rx_fifo_size = 64,
  898. .ctlr_flags = 0,
  899. .min_div_pow = 0,
  900. };
  901. static const struct sh_msiof_chipdata rcar_gen2_data = {
  902. .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
  903. SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
  904. .tx_fifo_size = 64,
  905. .rx_fifo_size = 64,
  906. .ctlr_flags = SPI_CONTROLLER_MUST_TX,
  907. .min_div_pow = 0,
  908. };
  909. static const struct sh_msiof_chipdata rcar_gen3_data = {
  910. .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
  911. SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
  912. .tx_fifo_size = 64,
  913. .rx_fifo_size = 64,
  914. .ctlr_flags = SPI_CONTROLLER_MUST_TX,
  915. .min_div_pow = 1,
  916. };
  917. static const struct of_device_id sh_msiof_match[] = {
  918. { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
  919. { .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data },
  920. { .compatible = "renesas,msiof-r8a7745", .data = &rcar_gen2_data },
  921. { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data },
  922. { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data },
  923. { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data },
  924. { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data },
  925. { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data },
  926. { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
  927. { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data },
  928. { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
  929. { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */
  930. {},
  931. };
  932. MODULE_DEVICE_TABLE(of, sh_msiof_match);
  933. #ifdef CONFIG_OF
  934. static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
  935. {
  936. struct sh_msiof_spi_info *info;
  937. struct device_node *np = dev->of_node;
  938. u32 num_cs = 1;
  939. info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
  940. if (!info)
  941. return NULL;
  942. info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE
  943. : MSIOF_SPI_MASTER;
  944. /* Parse the MSIOF properties */
  945. if (info->mode == MSIOF_SPI_MASTER)
  946. of_property_read_u32(np, "num-cs", &num_cs);
  947. of_property_read_u32(np, "renesas,tx-fifo-size",
  948. &info->tx_fifo_override);
  949. of_property_read_u32(np, "renesas,rx-fifo-size",
  950. &info->rx_fifo_override);
  951. of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
  952. of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
  953. info->num_chipselect = num_cs;
  954. return info;
  955. }
  956. #else
  957. static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
  958. {
  959. return NULL;
  960. }
  961. #endif
  962. static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
  963. enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
  964. {
  965. dma_cap_mask_t mask;
  966. struct dma_chan *chan;
  967. struct dma_slave_config cfg;
  968. int ret;
  969. dma_cap_zero(mask);
  970. dma_cap_set(DMA_SLAVE, mask);
  971. chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
  972. (void *)(unsigned long)id, dev,
  973. dir == DMA_MEM_TO_DEV ? "tx" : "rx");
  974. if (!chan) {
  975. dev_warn(dev, "dma_request_slave_channel_compat failed\n");
  976. return NULL;
  977. }
  978. memset(&cfg, 0, sizeof(cfg));
  979. cfg.direction = dir;
  980. if (dir == DMA_MEM_TO_DEV) {
  981. cfg.dst_addr = port_addr;
  982. cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  983. } else {
  984. cfg.src_addr = port_addr;
  985. cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  986. }
  987. ret = dmaengine_slave_config(chan, &cfg);
  988. if (ret) {
  989. dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
  990. dma_release_channel(chan);
  991. return NULL;
  992. }
  993. return chan;
  994. }
  995. static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
  996. {
  997. struct platform_device *pdev = p->pdev;
  998. struct device *dev = &pdev->dev;
  999. const struct sh_msiof_spi_info *info = p->info;
  1000. unsigned int dma_tx_id, dma_rx_id;
  1001. const struct resource *res;
  1002. struct spi_controller *ctlr;
  1003. struct device *tx_dev, *rx_dev;
  1004. if (dev->of_node) {
  1005. /* In the OF case we will get the slave IDs from the DT */
  1006. dma_tx_id = 0;
  1007. dma_rx_id = 0;
  1008. } else if (info && info->dma_tx_id && info->dma_rx_id) {
  1009. dma_tx_id = info->dma_tx_id;
  1010. dma_rx_id = info->dma_rx_id;
  1011. } else {
  1012. /* The driver assumes no error */
  1013. return 0;
  1014. }
  1015. /* The DMA engine uses the second register set, if present */
  1016. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1017. if (!res)
  1018. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1019. ctlr = p->ctlr;
  1020. ctlr->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
  1021. dma_tx_id, res->start + SITFDR);
  1022. if (!ctlr->dma_tx)
  1023. return -ENODEV;
  1024. ctlr->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
  1025. dma_rx_id, res->start + SIRFDR);
  1026. if (!ctlr->dma_rx)
  1027. goto free_tx_chan;
  1028. p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
  1029. if (!p->tx_dma_page)
  1030. goto free_rx_chan;
  1031. p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
  1032. if (!p->rx_dma_page)
  1033. goto free_tx_page;
  1034. tx_dev = ctlr->dma_tx->device->dev;
  1035. p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
  1036. DMA_TO_DEVICE);
  1037. if (dma_mapping_error(tx_dev, p->tx_dma_addr))
  1038. goto free_rx_page;
  1039. rx_dev = ctlr->dma_rx->device->dev;
  1040. p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
  1041. DMA_FROM_DEVICE);
  1042. if (dma_mapping_error(rx_dev, p->rx_dma_addr))
  1043. goto unmap_tx_page;
  1044. dev_info(dev, "DMA available");
  1045. return 0;
  1046. unmap_tx_page:
  1047. dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
  1048. free_rx_page:
  1049. free_page((unsigned long)p->rx_dma_page);
  1050. free_tx_page:
  1051. free_page((unsigned long)p->tx_dma_page);
  1052. free_rx_chan:
  1053. dma_release_channel(ctlr->dma_rx);
  1054. free_tx_chan:
  1055. dma_release_channel(ctlr->dma_tx);
  1056. ctlr->dma_tx = NULL;
  1057. return -ENODEV;
  1058. }
  1059. static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
  1060. {
  1061. struct spi_controller *ctlr = p->ctlr;
  1062. if (!ctlr->dma_tx)
  1063. return;
  1064. dma_unmap_single(ctlr->dma_rx->device->dev, p->rx_dma_addr, PAGE_SIZE,
  1065. DMA_FROM_DEVICE);
  1066. dma_unmap_single(ctlr->dma_tx->device->dev, p->tx_dma_addr, PAGE_SIZE,
  1067. DMA_TO_DEVICE);
  1068. free_page((unsigned long)p->rx_dma_page);
  1069. free_page((unsigned long)p->tx_dma_page);
  1070. dma_release_channel(ctlr->dma_rx);
  1071. dma_release_channel(ctlr->dma_tx);
  1072. }
  1073. static int sh_msiof_spi_probe(struct platform_device *pdev)
  1074. {
  1075. struct spi_controller *ctlr;
  1076. const struct sh_msiof_chipdata *chipdata;
  1077. struct sh_msiof_spi_info *info;
  1078. struct sh_msiof_spi_priv *p;
  1079. int i;
  1080. int ret;
  1081. chipdata = of_device_get_match_data(&pdev->dev);
  1082. if (chipdata) {
  1083. info = sh_msiof_spi_parse_dt(&pdev->dev);
  1084. } else {
  1085. chipdata = (const void *)pdev->id_entry->driver_data;
  1086. info = dev_get_platdata(&pdev->dev);
  1087. }
  1088. if (!info) {
  1089. dev_err(&pdev->dev, "failed to obtain device info\n");
  1090. return -ENXIO;
  1091. }
  1092. if (info->mode == MSIOF_SPI_SLAVE)
  1093. ctlr = spi_alloc_slave(&pdev->dev,
  1094. sizeof(struct sh_msiof_spi_priv));
  1095. else
  1096. ctlr = spi_alloc_master(&pdev->dev,
  1097. sizeof(struct sh_msiof_spi_priv));
  1098. if (ctlr == NULL)
  1099. return -ENOMEM;
  1100. p = spi_controller_get_devdata(ctlr);
  1101. platform_set_drvdata(pdev, p);
  1102. p->ctlr = ctlr;
  1103. p->info = info;
  1104. p->min_div_pow = chipdata->min_div_pow;
  1105. init_completion(&p->done);
  1106. init_completion(&p->done_txdma);
  1107. p->clk = devm_clk_get(&pdev->dev, NULL);
  1108. if (IS_ERR(p->clk)) {
  1109. dev_err(&pdev->dev, "cannot get clock\n");
  1110. ret = PTR_ERR(p->clk);
  1111. goto err1;
  1112. }
  1113. i = platform_get_irq(pdev, 0);
  1114. if (i < 0) {
  1115. ret = i;
  1116. goto err1;
  1117. }
  1118. p->mapbase = devm_platform_ioremap_resource(pdev, 0);
  1119. if (IS_ERR(p->mapbase)) {
  1120. ret = PTR_ERR(p->mapbase);
  1121. goto err1;
  1122. }
  1123. ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
  1124. dev_name(&pdev->dev), p);
  1125. if (ret) {
  1126. dev_err(&pdev->dev, "unable to request irq\n");
  1127. goto err1;
  1128. }
  1129. p->pdev = pdev;
  1130. pm_runtime_enable(&pdev->dev);
  1131. /* Platform data may override FIFO sizes */
  1132. p->tx_fifo_size = chipdata->tx_fifo_size;
  1133. p->rx_fifo_size = chipdata->rx_fifo_size;
  1134. if (p->info->tx_fifo_override)
  1135. p->tx_fifo_size = p->info->tx_fifo_override;
  1136. if (p->info->rx_fifo_override)
  1137. p->rx_fifo_size = p->info->rx_fifo_override;
  1138. /* init controller code */
  1139. ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
  1140. ctlr->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
  1141. ctlr->flags = chipdata->ctlr_flags;
  1142. ctlr->bus_num = pdev->id;
  1143. ctlr->num_chipselect = p->info->num_chipselect;
  1144. ctlr->dev.of_node = pdev->dev.of_node;
  1145. ctlr->setup = sh_msiof_spi_setup;
  1146. ctlr->prepare_message = sh_msiof_prepare_message;
  1147. ctlr->slave_abort = sh_msiof_slave_abort;
  1148. ctlr->bits_per_word_mask = chipdata->bits_per_word_mask;
  1149. ctlr->auto_runtime_pm = true;
  1150. ctlr->transfer_one = sh_msiof_transfer_one;
  1151. ctlr->use_gpio_descriptors = true;
  1152. ctlr->max_native_cs = MAX_SS;
  1153. ret = sh_msiof_request_dma(p);
  1154. if (ret < 0)
  1155. dev_warn(&pdev->dev, "DMA not available, using PIO\n");
  1156. ret = devm_spi_register_controller(&pdev->dev, ctlr);
  1157. if (ret < 0) {
  1158. dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
  1159. goto err2;
  1160. }
  1161. return 0;
  1162. err2:
  1163. sh_msiof_release_dma(p);
  1164. pm_runtime_disable(&pdev->dev);
  1165. err1:
  1166. spi_controller_put(ctlr);
  1167. return ret;
  1168. }
  1169. static int sh_msiof_spi_remove(struct platform_device *pdev)
  1170. {
  1171. struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
  1172. sh_msiof_release_dma(p);
  1173. pm_runtime_disable(&pdev->dev);
  1174. return 0;
  1175. }
  1176. static const struct platform_device_id spi_driver_ids[] = {
  1177. { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
  1178. {},
  1179. };
  1180. MODULE_DEVICE_TABLE(platform, spi_driver_ids);
  1181. #ifdef CONFIG_PM_SLEEP
  1182. static int sh_msiof_spi_suspend(struct device *dev)
  1183. {
  1184. struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
  1185. return spi_controller_suspend(p->ctlr);
  1186. }
  1187. static int sh_msiof_spi_resume(struct device *dev)
  1188. {
  1189. struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
  1190. return spi_controller_resume(p->ctlr);
  1191. }
  1192. static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend,
  1193. sh_msiof_spi_resume);
  1194. #define DEV_PM_OPS (&sh_msiof_spi_pm_ops)
  1195. #else
  1196. #define DEV_PM_OPS NULL
  1197. #endif /* CONFIG_PM_SLEEP */
  1198. static struct platform_driver sh_msiof_spi_drv = {
  1199. .probe = sh_msiof_spi_probe,
  1200. .remove = sh_msiof_spi_remove,
  1201. .id_table = spi_driver_ids,
  1202. .driver = {
  1203. .name = "spi_sh_msiof",
  1204. .pm = DEV_PM_OPS,
  1205. .of_match_table = of_match_ptr(sh_msiof_match),
  1206. },
  1207. };
  1208. module_platform_driver(sh_msiof_spi_drv);
  1209. MODULE_DESCRIPTION("SuperH MSIOF SPI Controller Interface Driver");
  1210. MODULE_AUTHOR("Magnus Damm");
  1211. MODULE_LICENSE("GPL v2");
  1212. MODULE_ALIAS("platform:spi_sh_msiof");