spi-s3c64xx.c 39 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Copyright (c) 2009 Samsung Electronics Co., Ltd.
  4. // Jaswinder Singh <jassi.brar@samsung.com>
  5. #include <linux/init.h>
  6. #include <linux/module.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/delay.h>
  9. #include <linux/clk.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/dmaengine.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/spi/spi.h>
  15. #include <linux/gpio.h>
  16. #include <linux/of.h>
  17. #include <linux/of_gpio.h>
  18. #include <linux/platform_data/spi-s3c64xx.h>
  19. #define MAX_SPI_PORTS 6
  20. #define S3C64XX_SPI_QUIRK_POLL (1 << 0)
  21. #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
  22. #define AUTOSUSPEND_TIMEOUT 2000
  23. /* Registers and bit-fields */
  24. #define S3C64XX_SPI_CH_CFG 0x00
  25. #define S3C64XX_SPI_CLK_CFG 0x04
  26. #define S3C64XX_SPI_MODE_CFG 0x08
  27. #define S3C64XX_SPI_CS_REG 0x0C
  28. #define S3C64XX_SPI_INT_EN 0x10
  29. #define S3C64XX_SPI_STATUS 0x14
  30. #define S3C64XX_SPI_TX_DATA 0x18
  31. #define S3C64XX_SPI_RX_DATA 0x1C
  32. #define S3C64XX_SPI_PACKET_CNT 0x20
  33. #define S3C64XX_SPI_PENDING_CLR 0x24
  34. #define S3C64XX_SPI_SWAP_CFG 0x28
  35. #define S3C64XX_SPI_FB_CLK 0x2C
  36. #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
  37. #define S3C64XX_SPI_CH_SW_RST (1<<5)
  38. #define S3C64XX_SPI_CH_SLAVE (1<<4)
  39. #define S3C64XX_SPI_CPOL_L (1<<3)
  40. #define S3C64XX_SPI_CPHA_B (1<<2)
  41. #define S3C64XX_SPI_CH_RXCH_ON (1<<1)
  42. #define S3C64XX_SPI_CH_TXCH_ON (1<<0)
  43. #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
  44. #define S3C64XX_SPI_CLKSEL_SRCSHFT 9
  45. #define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
  46. #define S3C64XX_SPI_PSR_MASK 0xff
  47. #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
  48. #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
  49. #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
  50. #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
  51. #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
  52. #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
  53. #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
  54. #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
  55. #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
  56. #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
  57. #define S3C64XX_SPI_MODE_4BURST (1<<0)
  58. #define S3C64XX_SPI_CS_NSC_CNT_2 (2<<4)
  59. #define S3C64XX_SPI_CS_AUTO (1<<1)
  60. #define S3C64XX_SPI_CS_SIG_INACT (1<<0)
  61. #define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
  62. #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
  63. #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
  64. #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
  65. #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
  66. #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
  67. #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
  68. #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
  69. #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
  70. #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
  71. #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
  72. #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
  73. #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
  74. #define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
  75. #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
  76. #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
  77. #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
  78. #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
  79. #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
  80. #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
  81. #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
  82. #define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
  83. #define S3C64XX_SPI_SWAP_RX_EN (1<<4)
  84. #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
  85. #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
  86. #define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
  87. #define S3C64XX_SPI_SWAP_TX_EN (1<<0)
  88. #define S3C64XX_SPI_FBCLK_MSK (3<<0)
  89. #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
  90. #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
  91. (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
  92. #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
  93. #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
  94. FIFO_LVL_MASK(i))
  95. #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
  96. #define S3C64XX_SPI_TRAILCNT_OFF 19
  97. #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
  98. #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
  99. #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
  100. #define RXBUSY (1<<2)
  101. #define TXBUSY (1<<3)
  102. struct s3c64xx_spi_dma_data {
  103. struct dma_chan *ch;
  104. dma_cookie_t cookie;
  105. enum dma_transfer_direction direction;
  106. };
  107. /**
  108. * struct s3c64xx_spi_info - SPI Controller hardware info
  109. * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
  110. * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
  111. * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
  112. * @quirks: Bitmask of known quirks
  113. * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
  114. * @clk_from_cmu: True, if the controller does not include a clock mux and
  115. * prescaler unit.
  116. * @clk_ioclk: True if clock is present on this device
  117. *
  118. * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
  119. * differ in some aspects such as the size of the fifo and spi bus clock
  120. * setup. Such differences are specified to the driver using this structure
  121. * which is provided as driver data to the driver.
  122. */
  123. struct s3c64xx_spi_port_config {
  124. int fifo_lvl_mask[MAX_SPI_PORTS];
  125. int rx_lvl_offset;
  126. int tx_st_done;
  127. int quirks;
  128. bool high_speed;
  129. bool clk_from_cmu;
  130. bool clk_ioclk;
  131. };
  132. /**
  133. * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
  134. * @clk: Pointer to the spi clock.
  135. * @src_clk: Pointer to the clock used to generate SPI signals.
  136. * @ioclk: Pointer to the i/o clock between master and slave
  137. * @pdev: Pointer to device's platform device data
  138. * @master: Pointer to the SPI Protocol master.
  139. * @cntrlr_info: Platform specific data for the controller this driver manages.
  140. * @lock: Controller specific lock.
  141. * @state: Set of FLAGS to indicate status.
  142. * @sfr_start: BUS address of SPI controller regs.
  143. * @regs: Pointer to ioremap'ed controller registers.
  144. * @xfer_completion: To indicate completion of xfer task.
  145. * @cur_mode: Stores the active configuration of the controller.
  146. * @cur_bpw: Stores the active bits per word settings.
  147. * @cur_speed: Current clock speed
  148. * @rx_dma: Local receive DMA data (e.g. chan and direction)
  149. * @tx_dma: Local transmit DMA data (e.g. chan and direction)
  150. * @port_conf: Local SPI port configuartion data
  151. * @port_id: Port identification number
  152. */
  153. struct s3c64xx_spi_driver_data {
  154. void __iomem *regs;
  155. struct clk *clk;
  156. struct clk *src_clk;
  157. struct clk *ioclk;
  158. struct platform_device *pdev;
  159. struct spi_master *master;
  160. struct s3c64xx_spi_info *cntrlr_info;
  161. spinlock_t lock;
  162. unsigned long sfr_start;
  163. struct completion xfer_completion;
  164. unsigned state;
  165. unsigned cur_mode, cur_bpw;
  166. unsigned cur_speed;
  167. struct s3c64xx_spi_dma_data rx_dma;
  168. struct s3c64xx_spi_dma_data tx_dma;
  169. struct s3c64xx_spi_port_config *port_conf;
  170. unsigned int port_id;
  171. };
  172. static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd)
  173. {
  174. void __iomem *regs = sdd->regs;
  175. unsigned long loops;
  176. u32 val;
  177. writel(0, regs + S3C64XX_SPI_PACKET_CNT);
  178. val = readl(regs + S3C64XX_SPI_CH_CFG);
  179. val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
  180. writel(val, regs + S3C64XX_SPI_CH_CFG);
  181. val = readl(regs + S3C64XX_SPI_CH_CFG);
  182. val |= S3C64XX_SPI_CH_SW_RST;
  183. val &= ~S3C64XX_SPI_CH_HS_EN;
  184. writel(val, regs + S3C64XX_SPI_CH_CFG);
  185. /* Flush TxFIFO*/
  186. loops = msecs_to_loops(1);
  187. do {
  188. val = readl(regs + S3C64XX_SPI_STATUS);
  189. } while (TX_FIFO_LVL(val, sdd) && loops--);
  190. if (loops == 0)
  191. dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
  192. /* Flush RxFIFO*/
  193. loops = msecs_to_loops(1);
  194. do {
  195. val = readl(regs + S3C64XX_SPI_STATUS);
  196. if (RX_FIFO_LVL(val, sdd))
  197. readl(regs + S3C64XX_SPI_RX_DATA);
  198. else
  199. break;
  200. } while (loops--);
  201. if (loops == 0)
  202. dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
  203. val = readl(regs + S3C64XX_SPI_CH_CFG);
  204. val &= ~S3C64XX_SPI_CH_SW_RST;
  205. writel(val, regs + S3C64XX_SPI_CH_CFG);
  206. val = readl(regs + S3C64XX_SPI_MODE_CFG);
  207. val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
  208. writel(val, regs + S3C64XX_SPI_MODE_CFG);
  209. }
  210. static void s3c64xx_spi_dmacb(void *data)
  211. {
  212. struct s3c64xx_spi_driver_data *sdd;
  213. struct s3c64xx_spi_dma_data *dma = data;
  214. unsigned long flags;
  215. if (dma->direction == DMA_DEV_TO_MEM)
  216. sdd = container_of(data,
  217. struct s3c64xx_spi_driver_data, rx_dma);
  218. else
  219. sdd = container_of(data,
  220. struct s3c64xx_spi_driver_data, tx_dma);
  221. spin_lock_irqsave(&sdd->lock, flags);
  222. if (dma->direction == DMA_DEV_TO_MEM) {
  223. sdd->state &= ~RXBUSY;
  224. if (!(sdd->state & TXBUSY))
  225. complete(&sdd->xfer_completion);
  226. } else {
  227. sdd->state &= ~TXBUSY;
  228. if (!(sdd->state & RXBUSY))
  229. complete(&sdd->xfer_completion);
  230. }
  231. spin_unlock_irqrestore(&sdd->lock, flags);
  232. }
  233. static int prepare_dma(struct s3c64xx_spi_dma_data *dma,
  234. struct sg_table *sgt)
  235. {
  236. struct s3c64xx_spi_driver_data *sdd;
  237. struct dma_slave_config config;
  238. struct dma_async_tx_descriptor *desc;
  239. int ret;
  240. memset(&config, 0, sizeof(config));
  241. if (dma->direction == DMA_DEV_TO_MEM) {
  242. sdd = container_of((void *)dma,
  243. struct s3c64xx_spi_driver_data, rx_dma);
  244. config.direction = dma->direction;
  245. config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
  246. config.src_addr_width = sdd->cur_bpw / 8;
  247. config.src_maxburst = 1;
  248. dmaengine_slave_config(dma->ch, &config);
  249. } else {
  250. sdd = container_of((void *)dma,
  251. struct s3c64xx_spi_driver_data, tx_dma);
  252. config.direction = dma->direction;
  253. config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
  254. config.dst_addr_width = sdd->cur_bpw / 8;
  255. config.dst_maxburst = 1;
  256. dmaengine_slave_config(dma->ch, &config);
  257. }
  258. desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
  259. dma->direction, DMA_PREP_INTERRUPT);
  260. if (!desc) {
  261. dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist",
  262. dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx");
  263. return -ENOMEM;
  264. }
  265. desc->callback = s3c64xx_spi_dmacb;
  266. desc->callback_param = dma;
  267. dma->cookie = dmaengine_submit(desc);
  268. ret = dma_submit_error(dma->cookie);
  269. if (ret) {
  270. dev_err(&sdd->pdev->dev, "DMA submission failed");
  271. return -EIO;
  272. }
  273. dma_async_issue_pending(dma->ch);
  274. return 0;
  275. }
  276. static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
  277. {
  278. struct s3c64xx_spi_driver_data *sdd =
  279. spi_master_get_devdata(spi->master);
  280. if (sdd->cntrlr_info->no_cs)
  281. return;
  282. if (enable) {
  283. if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
  284. writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
  285. } else {
  286. u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG);
  287. ssel |= (S3C64XX_SPI_CS_AUTO |
  288. S3C64XX_SPI_CS_NSC_CNT_2);
  289. writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG);
  290. }
  291. } else {
  292. if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
  293. writel(S3C64XX_SPI_CS_SIG_INACT,
  294. sdd->regs + S3C64XX_SPI_CS_REG);
  295. }
  296. }
  297. static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
  298. {
  299. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
  300. if (is_polling(sdd))
  301. return 0;
  302. spi->dma_rx = sdd->rx_dma.ch;
  303. spi->dma_tx = sdd->tx_dma.ch;
  304. return 0;
  305. }
  306. static bool s3c64xx_spi_can_dma(struct spi_master *master,
  307. struct spi_device *spi,
  308. struct spi_transfer *xfer)
  309. {
  310. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  311. return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
  312. }
  313. static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
  314. struct spi_transfer *xfer, int dma_mode)
  315. {
  316. void __iomem *regs = sdd->regs;
  317. u32 modecfg, chcfg;
  318. int ret = 0;
  319. modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
  320. modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
  321. chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
  322. chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
  323. if (dma_mode) {
  324. chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
  325. } else {
  326. /* Always shift in data in FIFO, even if xfer is Tx only,
  327. * this helps setting PCKT_CNT value for generating clocks
  328. * as exactly needed.
  329. */
  330. chcfg |= S3C64XX_SPI_CH_RXCH_ON;
  331. writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
  332. | S3C64XX_SPI_PACKET_CNT_EN,
  333. regs + S3C64XX_SPI_PACKET_CNT);
  334. }
  335. if (xfer->tx_buf != NULL) {
  336. sdd->state |= TXBUSY;
  337. chcfg |= S3C64XX_SPI_CH_TXCH_ON;
  338. if (dma_mode) {
  339. modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
  340. ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
  341. } else {
  342. switch (sdd->cur_bpw) {
  343. case 32:
  344. iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
  345. xfer->tx_buf, xfer->len / 4);
  346. break;
  347. case 16:
  348. iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
  349. xfer->tx_buf, xfer->len / 2);
  350. break;
  351. default:
  352. iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
  353. xfer->tx_buf, xfer->len);
  354. break;
  355. }
  356. }
  357. }
  358. if (xfer->rx_buf != NULL) {
  359. sdd->state |= RXBUSY;
  360. if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
  361. && !(sdd->cur_mode & SPI_CPHA))
  362. chcfg |= S3C64XX_SPI_CH_HS_EN;
  363. if (dma_mode) {
  364. modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
  365. chcfg |= S3C64XX_SPI_CH_RXCH_ON;
  366. writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
  367. | S3C64XX_SPI_PACKET_CNT_EN,
  368. regs + S3C64XX_SPI_PACKET_CNT);
  369. ret = prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
  370. }
  371. }
  372. if (ret)
  373. return ret;
  374. writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
  375. writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
  376. return 0;
  377. }
  378. static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
  379. int timeout_ms)
  380. {
  381. void __iomem *regs = sdd->regs;
  382. unsigned long val = 1;
  383. u32 status;
  384. /* max fifo depth available */
  385. u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
  386. if (timeout_ms)
  387. val = msecs_to_loops(timeout_ms);
  388. do {
  389. status = readl(regs + S3C64XX_SPI_STATUS);
  390. } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
  391. /* return the actual received data length */
  392. return RX_FIFO_LVL(status, sdd);
  393. }
  394. static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
  395. struct spi_transfer *xfer)
  396. {
  397. void __iomem *regs = sdd->regs;
  398. unsigned long val;
  399. u32 status;
  400. int ms;
  401. /* millisecs to xfer 'len' bytes @ 'cur_speed' */
  402. ms = xfer->len * 8 * 1000 / sdd->cur_speed;
  403. ms += 30; /* some tolerance */
  404. ms = max(ms, 100); /* minimum timeout */
  405. val = msecs_to_jiffies(ms) + 10;
  406. val = wait_for_completion_timeout(&sdd->xfer_completion, val);
  407. /*
  408. * If the previous xfer was completed within timeout, then
  409. * proceed further else return -EIO.
  410. * DmaTx returns after simply writing data in the FIFO,
  411. * w/o waiting for real transmission on the bus to finish.
  412. * DmaRx returns only after Dma read data from FIFO which
  413. * needs bus transmission to finish, so we don't worry if
  414. * Xfer involved Rx(with or without Tx).
  415. */
  416. if (val && !xfer->rx_buf) {
  417. val = msecs_to_loops(10);
  418. status = readl(regs + S3C64XX_SPI_STATUS);
  419. while ((TX_FIFO_LVL(status, sdd)
  420. || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
  421. && --val) {
  422. cpu_relax();
  423. status = readl(regs + S3C64XX_SPI_STATUS);
  424. }
  425. }
  426. /* If timed out while checking rx/tx status return error */
  427. if (!val)
  428. return -EIO;
  429. return 0;
  430. }
  431. static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
  432. struct spi_transfer *xfer)
  433. {
  434. void __iomem *regs = sdd->regs;
  435. unsigned long val;
  436. u32 status;
  437. int loops;
  438. u32 cpy_len;
  439. u8 *buf;
  440. int ms;
  441. /* millisecs to xfer 'len' bytes @ 'cur_speed' */
  442. ms = xfer->len * 8 * 1000 / sdd->cur_speed;
  443. ms += 10; /* some tolerance */
  444. val = msecs_to_loops(ms);
  445. do {
  446. status = readl(regs + S3C64XX_SPI_STATUS);
  447. } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
  448. if (!val)
  449. return -EIO;
  450. /* If it was only Tx */
  451. if (!xfer->rx_buf) {
  452. sdd->state &= ~TXBUSY;
  453. return 0;
  454. }
  455. /*
  456. * If the receive length is bigger than the controller fifo
  457. * size, calculate the loops and read the fifo as many times.
  458. * loops = length / max fifo size (calculated by using the
  459. * fifo mask).
  460. * For any size less than the fifo size the below code is
  461. * executed atleast once.
  462. */
  463. loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
  464. buf = xfer->rx_buf;
  465. do {
  466. /* wait for data to be received in the fifo */
  467. cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
  468. (loops ? ms : 0));
  469. switch (sdd->cur_bpw) {
  470. case 32:
  471. ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
  472. buf, cpy_len / 4);
  473. break;
  474. case 16:
  475. ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
  476. buf, cpy_len / 2);
  477. break;
  478. default:
  479. ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
  480. buf, cpy_len);
  481. break;
  482. }
  483. buf = buf + cpy_len;
  484. } while (loops--);
  485. sdd->state &= ~RXBUSY;
  486. return 0;
  487. }
  488. static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
  489. {
  490. void __iomem *regs = sdd->regs;
  491. int ret;
  492. u32 val;
  493. /* Disable Clock */
  494. if (!sdd->port_conf->clk_from_cmu) {
  495. val = readl(regs + S3C64XX_SPI_CLK_CFG);
  496. val &= ~S3C64XX_SPI_ENCLK_ENABLE;
  497. writel(val, regs + S3C64XX_SPI_CLK_CFG);
  498. }
  499. /* Set Polarity and Phase */
  500. val = readl(regs + S3C64XX_SPI_CH_CFG);
  501. val &= ~(S3C64XX_SPI_CH_SLAVE |
  502. S3C64XX_SPI_CPOL_L |
  503. S3C64XX_SPI_CPHA_B);
  504. if (sdd->cur_mode & SPI_CPOL)
  505. val |= S3C64XX_SPI_CPOL_L;
  506. if (sdd->cur_mode & SPI_CPHA)
  507. val |= S3C64XX_SPI_CPHA_B;
  508. writel(val, regs + S3C64XX_SPI_CH_CFG);
  509. /* Set Channel & DMA Mode */
  510. val = readl(regs + S3C64XX_SPI_MODE_CFG);
  511. val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
  512. | S3C64XX_SPI_MODE_CH_TSZ_MASK);
  513. switch (sdd->cur_bpw) {
  514. case 32:
  515. val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
  516. val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
  517. break;
  518. case 16:
  519. val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
  520. val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
  521. break;
  522. default:
  523. val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
  524. val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
  525. break;
  526. }
  527. writel(val, regs + S3C64XX_SPI_MODE_CFG);
  528. if (sdd->port_conf->clk_from_cmu) {
  529. /* The src_clk clock is divided internally by 2 */
  530. ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
  531. if (ret)
  532. return ret;
  533. sdd->cur_speed = clk_get_rate(sdd->src_clk) / 2;
  534. } else {
  535. /* Configure Clock */
  536. val = readl(regs + S3C64XX_SPI_CLK_CFG);
  537. val &= ~S3C64XX_SPI_PSR_MASK;
  538. val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
  539. & S3C64XX_SPI_PSR_MASK);
  540. writel(val, regs + S3C64XX_SPI_CLK_CFG);
  541. /* Enable Clock */
  542. val = readl(regs + S3C64XX_SPI_CLK_CFG);
  543. val |= S3C64XX_SPI_ENCLK_ENABLE;
  544. writel(val, regs + S3C64XX_SPI_CLK_CFG);
  545. }
  546. return 0;
  547. }
  548. #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
  549. static int s3c64xx_spi_prepare_message(struct spi_master *master,
  550. struct spi_message *msg)
  551. {
  552. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  553. struct spi_device *spi = msg->spi;
  554. struct s3c64xx_spi_csinfo *cs = spi->controller_data;
  555. /* Configure feedback delay */
  556. writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
  557. return 0;
  558. }
  559. static int s3c64xx_spi_transfer_one(struct spi_master *master,
  560. struct spi_device *spi,
  561. struct spi_transfer *xfer)
  562. {
  563. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  564. const unsigned int fifo_len = (FIFO_LVL_MASK(sdd) >> 1) + 1;
  565. const void *tx_buf = NULL;
  566. void *rx_buf = NULL;
  567. int target_len = 0, origin_len = 0;
  568. int use_dma = 0;
  569. int status;
  570. u32 speed;
  571. u8 bpw;
  572. unsigned long flags;
  573. reinit_completion(&sdd->xfer_completion);
  574. /* Only BPW and Speed may change across transfers */
  575. bpw = xfer->bits_per_word;
  576. speed = xfer->speed_hz;
  577. if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
  578. sdd->cur_bpw = bpw;
  579. sdd->cur_speed = speed;
  580. sdd->cur_mode = spi->mode;
  581. status = s3c64xx_spi_config(sdd);
  582. if (status)
  583. return status;
  584. }
  585. if (!is_polling(sdd) && (xfer->len > fifo_len) &&
  586. sdd->rx_dma.ch && sdd->tx_dma.ch) {
  587. use_dma = 1;
  588. } else if (is_polling(sdd) && xfer->len > fifo_len) {
  589. tx_buf = xfer->tx_buf;
  590. rx_buf = xfer->rx_buf;
  591. origin_len = xfer->len;
  592. target_len = xfer->len;
  593. if (xfer->len > fifo_len)
  594. xfer->len = fifo_len;
  595. }
  596. do {
  597. spin_lock_irqsave(&sdd->lock, flags);
  598. /* Pending only which is to be done */
  599. sdd->state &= ~RXBUSY;
  600. sdd->state &= ~TXBUSY;
  601. /* Start the signals */
  602. s3c64xx_spi_set_cs(spi, true);
  603. status = s3c64xx_enable_datapath(sdd, xfer, use_dma);
  604. spin_unlock_irqrestore(&sdd->lock, flags);
  605. if (status) {
  606. dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status);
  607. break;
  608. }
  609. if (use_dma)
  610. status = s3c64xx_wait_for_dma(sdd, xfer);
  611. else
  612. status = s3c64xx_wait_for_pio(sdd, xfer);
  613. if (status) {
  614. dev_err(&spi->dev,
  615. "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n",
  616. xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
  617. (sdd->state & RXBUSY) ? 'f' : 'p',
  618. (sdd->state & TXBUSY) ? 'f' : 'p',
  619. xfer->len, use_dma ? 1 : 0, status);
  620. if (use_dma) {
  621. struct dma_tx_state s;
  622. if (xfer->tx_buf && (sdd->state & TXBUSY)) {
  623. dmaengine_pause(sdd->tx_dma.ch);
  624. dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s);
  625. dmaengine_terminate_all(sdd->tx_dma.ch);
  626. dev_err(&spi->dev, "TX residue: %d\n", s.residue);
  627. }
  628. if (xfer->rx_buf && (sdd->state & RXBUSY)) {
  629. dmaengine_pause(sdd->rx_dma.ch);
  630. dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s);
  631. dmaengine_terminate_all(sdd->rx_dma.ch);
  632. dev_err(&spi->dev, "RX residue: %d\n", s.residue);
  633. }
  634. }
  635. } else {
  636. s3c64xx_flush_fifo(sdd);
  637. }
  638. if (target_len > 0) {
  639. target_len -= xfer->len;
  640. if (xfer->tx_buf)
  641. xfer->tx_buf += xfer->len;
  642. if (xfer->rx_buf)
  643. xfer->rx_buf += xfer->len;
  644. if (target_len > fifo_len)
  645. xfer->len = fifo_len;
  646. else
  647. xfer->len = target_len;
  648. }
  649. } while (target_len > 0);
  650. if (origin_len) {
  651. /* Restore original xfer buffers and length */
  652. xfer->tx_buf = tx_buf;
  653. xfer->rx_buf = rx_buf;
  654. xfer->len = origin_len;
  655. }
  656. return status;
  657. }
  658. static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
  659. struct spi_device *spi)
  660. {
  661. struct s3c64xx_spi_csinfo *cs;
  662. struct device_node *slave_np, *data_np = NULL;
  663. u32 fb_delay = 0;
  664. slave_np = spi->dev.of_node;
  665. if (!slave_np) {
  666. dev_err(&spi->dev, "device node not found\n");
  667. return ERR_PTR(-EINVAL);
  668. }
  669. data_np = of_get_child_by_name(slave_np, "controller-data");
  670. if (!data_np) {
  671. dev_err(&spi->dev, "child node 'controller-data' not found\n");
  672. return ERR_PTR(-EINVAL);
  673. }
  674. cs = kzalloc(sizeof(*cs), GFP_KERNEL);
  675. if (!cs) {
  676. of_node_put(data_np);
  677. return ERR_PTR(-ENOMEM);
  678. }
  679. of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
  680. cs->fb_delay = fb_delay;
  681. of_node_put(data_np);
  682. return cs;
  683. }
  684. /*
  685. * Here we only check the validity of requested configuration
  686. * and save the configuration in a local data-structure.
  687. * The controller is actually configured only just before we
  688. * get a message to transfer.
  689. */
  690. static int s3c64xx_spi_setup(struct spi_device *spi)
  691. {
  692. struct s3c64xx_spi_csinfo *cs = spi->controller_data;
  693. struct s3c64xx_spi_driver_data *sdd;
  694. int err;
  695. sdd = spi_master_get_devdata(spi->master);
  696. if (spi->dev.of_node) {
  697. cs = s3c64xx_get_slave_ctrldata(spi);
  698. spi->controller_data = cs;
  699. } else if (cs) {
  700. /* On non-DT platforms the SPI core will set spi->cs_gpio
  701. * to -ENOENT. The GPIO pin used to drive the chip select
  702. * is defined by using platform data so spi->cs_gpio value
  703. * has to be override to have the proper GPIO pin number.
  704. */
  705. spi->cs_gpio = cs->line;
  706. }
  707. if (IS_ERR_OR_NULL(cs)) {
  708. dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
  709. return -ENODEV;
  710. }
  711. if (!spi_get_ctldata(spi)) {
  712. if (gpio_is_valid(spi->cs_gpio)) {
  713. err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
  714. dev_name(&spi->dev));
  715. if (err) {
  716. dev_err(&spi->dev,
  717. "Failed to get /CS gpio [%d]: %d\n",
  718. spi->cs_gpio, err);
  719. goto err_gpio_req;
  720. }
  721. }
  722. spi_set_ctldata(spi, cs);
  723. }
  724. pm_runtime_get_sync(&sdd->pdev->dev);
  725. /* Check if we can provide the requested rate */
  726. if (!sdd->port_conf->clk_from_cmu) {
  727. u32 psr, speed;
  728. /* Max possible */
  729. speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
  730. if (spi->max_speed_hz > speed)
  731. spi->max_speed_hz = speed;
  732. psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
  733. psr &= S3C64XX_SPI_PSR_MASK;
  734. if (psr == S3C64XX_SPI_PSR_MASK)
  735. psr--;
  736. speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
  737. if (spi->max_speed_hz < speed) {
  738. if (psr+1 < S3C64XX_SPI_PSR_MASK) {
  739. psr++;
  740. } else {
  741. err = -EINVAL;
  742. goto setup_exit;
  743. }
  744. }
  745. speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
  746. if (spi->max_speed_hz >= speed) {
  747. spi->max_speed_hz = speed;
  748. } else {
  749. dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
  750. spi->max_speed_hz);
  751. err = -EINVAL;
  752. goto setup_exit;
  753. }
  754. }
  755. pm_runtime_mark_last_busy(&sdd->pdev->dev);
  756. pm_runtime_put_autosuspend(&sdd->pdev->dev);
  757. s3c64xx_spi_set_cs(spi, false);
  758. return 0;
  759. setup_exit:
  760. pm_runtime_mark_last_busy(&sdd->pdev->dev);
  761. pm_runtime_put_autosuspend(&sdd->pdev->dev);
  762. /* setup() returns with device de-selected */
  763. s3c64xx_spi_set_cs(spi, false);
  764. if (gpio_is_valid(spi->cs_gpio))
  765. gpio_free(spi->cs_gpio);
  766. spi_set_ctldata(spi, NULL);
  767. err_gpio_req:
  768. if (spi->dev.of_node)
  769. kfree(cs);
  770. return err;
  771. }
  772. static void s3c64xx_spi_cleanup(struct spi_device *spi)
  773. {
  774. struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
  775. if (gpio_is_valid(spi->cs_gpio)) {
  776. gpio_free(spi->cs_gpio);
  777. if (spi->dev.of_node)
  778. kfree(cs);
  779. else {
  780. /* On non-DT platforms, the SPI core sets
  781. * spi->cs_gpio to -ENOENT and .setup()
  782. * overrides it with the GPIO pin value
  783. * passed using platform data.
  784. */
  785. spi->cs_gpio = -ENOENT;
  786. }
  787. }
  788. spi_set_ctldata(spi, NULL);
  789. }
  790. static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
  791. {
  792. struct s3c64xx_spi_driver_data *sdd = data;
  793. struct spi_master *spi = sdd->master;
  794. unsigned int val, clr = 0;
  795. val = readl(sdd->regs + S3C64XX_SPI_STATUS);
  796. if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
  797. clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
  798. dev_err(&spi->dev, "RX overrun\n");
  799. }
  800. if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
  801. clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
  802. dev_err(&spi->dev, "RX underrun\n");
  803. }
  804. if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
  805. clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
  806. dev_err(&spi->dev, "TX overrun\n");
  807. }
  808. if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
  809. clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
  810. dev_err(&spi->dev, "TX underrun\n");
  811. }
  812. /* Clear the pending irq by setting and then clearing it */
  813. writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
  814. writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
  815. return IRQ_HANDLED;
  816. }
  817. static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd)
  818. {
  819. struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
  820. void __iomem *regs = sdd->regs;
  821. unsigned int val;
  822. sdd->cur_speed = 0;
  823. if (sci->no_cs)
  824. writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
  825. else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
  826. writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG);
  827. /* Disable Interrupts - we use Polling if not DMA mode */
  828. writel(0, regs + S3C64XX_SPI_INT_EN);
  829. if (!sdd->port_conf->clk_from_cmu)
  830. writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
  831. regs + S3C64XX_SPI_CLK_CFG);
  832. writel(0, regs + S3C64XX_SPI_MODE_CFG);
  833. writel(0, regs + S3C64XX_SPI_PACKET_CNT);
  834. /* Clear any irq pending bits, should set and clear the bits */
  835. val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
  836. S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
  837. S3C64XX_SPI_PND_TX_OVERRUN_CLR |
  838. S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
  839. writel(val, regs + S3C64XX_SPI_PENDING_CLR);
  840. writel(0, regs + S3C64XX_SPI_PENDING_CLR);
  841. writel(0, regs + S3C64XX_SPI_SWAP_CFG);
  842. val = readl(regs + S3C64XX_SPI_MODE_CFG);
  843. val &= ~S3C64XX_SPI_MODE_4BURST;
  844. val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
  845. val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
  846. writel(val, regs + S3C64XX_SPI_MODE_CFG);
  847. s3c64xx_flush_fifo(sdd);
  848. }
  849. #ifdef CONFIG_OF
  850. static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
  851. {
  852. struct s3c64xx_spi_info *sci;
  853. u32 temp;
  854. sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
  855. if (!sci)
  856. return ERR_PTR(-ENOMEM);
  857. if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
  858. dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
  859. sci->src_clk_nr = 0;
  860. } else {
  861. sci->src_clk_nr = temp;
  862. }
  863. if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
  864. dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
  865. sci->num_cs = 1;
  866. } else {
  867. sci->num_cs = temp;
  868. }
  869. sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
  870. return sci;
  871. }
  872. #else
  873. static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
  874. {
  875. return dev_get_platdata(dev);
  876. }
  877. #endif
  878. static const struct of_device_id s3c64xx_spi_dt_match[];
  879. static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
  880. struct platform_device *pdev)
  881. {
  882. #ifdef CONFIG_OF
  883. if (pdev->dev.of_node) {
  884. const struct of_device_id *match;
  885. match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
  886. return (struct s3c64xx_spi_port_config *)match->data;
  887. }
  888. #endif
  889. return (struct s3c64xx_spi_port_config *)
  890. platform_get_device_id(pdev)->driver_data;
  891. }
  892. static int s3c64xx_spi_probe(struct platform_device *pdev)
  893. {
  894. struct resource *mem_res;
  895. struct s3c64xx_spi_driver_data *sdd;
  896. struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
  897. struct spi_master *master;
  898. int ret, irq;
  899. char clk_name[16];
  900. if (!sci && pdev->dev.of_node) {
  901. sci = s3c64xx_spi_parse_dt(&pdev->dev);
  902. if (IS_ERR(sci))
  903. return PTR_ERR(sci);
  904. }
  905. if (!sci) {
  906. dev_err(&pdev->dev, "platform_data missing!\n");
  907. return -ENODEV;
  908. }
  909. mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  910. if (mem_res == NULL) {
  911. dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
  912. return -ENXIO;
  913. }
  914. irq = platform_get_irq(pdev, 0);
  915. if (irq < 0) {
  916. dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
  917. return irq;
  918. }
  919. master = spi_alloc_master(&pdev->dev,
  920. sizeof(struct s3c64xx_spi_driver_data));
  921. if (master == NULL) {
  922. dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
  923. return -ENOMEM;
  924. }
  925. platform_set_drvdata(pdev, master);
  926. sdd = spi_master_get_devdata(master);
  927. sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
  928. sdd->master = master;
  929. sdd->cntrlr_info = sci;
  930. sdd->pdev = pdev;
  931. sdd->sfr_start = mem_res->start;
  932. if (pdev->dev.of_node) {
  933. ret = of_alias_get_id(pdev->dev.of_node, "spi");
  934. if (ret < 0) {
  935. dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
  936. ret);
  937. goto err_deref_master;
  938. }
  939. sdd->port_id = ret;
  940. } else {
  941. sdd->port_id = pdev->id;
  942. }
  943. sdd->cur_bpw = 8;
  944. sdd->tx_dma.direction = DMA_MEM_TO_DEV;
  945. sdd->rx_dma.direction = DMA_DEV_TO_MEM;
  946. master->dev.of_node = pdev->dev.of_node;
  947. master->bus_num = sdd->port_id;
  948. master->setup = s3c64xx_spi_setup;
  949. master->cleanup = s3c64xx_spi_cleanup;
  950. master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
  951. master->prepare_message = s3c64xx_spi_prepare_message;
  952. master->transfer_one = s3c64xx_spi_transfer_one;
  953. master->num_chipselect = sci->num_cs;
  954. master->dma_alignment = 8;
  955. master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
  956. SPI_BPW_MASK(8);
  957. /* the spi->mode bits understood by this driver: */
  958. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
  959. master->auto_runtime_pm = true;
  960. if (!is_polling(sdd))
  961. master->can_dma = s3c64xx_spi_can_dma;
  962. sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
  963. if (IS_ERR(sdd->regs)) {
  964. ret = PTR_ERR(sdd->regs);
  965. goto err_deref_master;
  966. }
  967. if (sci->cfg_gpio && sci->cfg_gpio()) {
  968. dev_err(&pdev->dev, "Unable to config gpio\n");
  969. ret = -EBUSY;
  970. goto err_deref_master;
  971. }
  972. /* Setup clocks */
  973. sdd->clk = devm_clk_get(&pdev->dev, "spi");
  974. if (IS_ERR(sdd->clk)) {
  975. dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
  976. ret = PTR_ERR(sdd->clk);
  977. goto err_deref_master;
  978. }
  979. ret = clk_prepare_enable(sdd->clk);
  980. if (ret) {
  981. dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
  982. goto err_deref_master;
  983. }
  984. sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
  985. sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
  986. if (IS_ERR(sdd->src_clk)) {
  987. dev_err(&pdev->dev,
  988. "Unable to acquire clock '%s'\n", clk_name);
  989. ret = PTR_ERR(sdd->src_clk);
  990. goto err_disable_clk;
  991. }
  992. ret = clk_prepare_enable(sdd->src_clk);
  993. if (ret) {
  994. dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
  995. goto err_disable_clk;
  996. }
  997. if (sdd->port_conf->clk_ioclk) {
  998. sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk");
  999. if (IS_ERR(sdd->ioclk)) {
  1000. dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n");
  1001. ret = PTR_ERR(sdd->ioclk);
  1002. goto err_disable_src_clk;
  1003. }
  1004. ret = clk_prepare_enable(sdd->ioclk);
  1005. if (ret) {
  1006. dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n");
  1007. goto err_disable_src_clk;
  1008. }
  1009. }
  1010. if (!is_polling(sdd)) {
  1011. /* Acquire DMA channels */
  1012. sdd->rx_dma.ch = dma_request_chan(&pdev->dev, "rx");
  1013. if (IS_ERR(sdd->rx_dma.ch)) {
  1014. dev_err(&pdev->dev, "Failed to get RX DMA channel\n");
  1015. ret = PTR_ERR(sdd->rx_dma.ch);
  1016. goto err_disable_io_clk;
  1017. }
  1018. sdd->tx_dma.ch = dma_request_chan(&pdev->dev, "tx");
  1019. if (IS_ERR(sdd->tx_dma.ch)) {
  1020. dev_err(&pdev->dev, "Failed to get TX DMA channel\n");
  1021. ret = PTR_ERR(sdd->tx_dma.ch);
  1022. goto err_release_rx_dma;
  1023. }
  1024. }
  1025. pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
  1026. pm_runtime_use_autosuspend(&pdev->dev);
  1027. pm_runtime_set_active(&pdev->dev);
  1028. pm_runtime_enable(&pdev->dev);
  1029. pm_runtime_get_sync(&pdev->dev);
  1030. /* Setup Deufult Mode */
  1031. s3c64xx_spi_hwinit(sdd);
  1032. spin_lock_init(&sdd->lock);
  1033. init_completion(&sdd->xfer_completion);
  1034. ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
  1035. "spi-s3c64xx", sdd);
  1036. if (ret != 0) {
  1037. dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
  1038. irq, ret);
  1039. goto err_pm_put;
  1040. }
  1041. writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
  1042. S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
  1043. sdd->regs + S3C64XX_SPI_INT_EN);
  1044. ret = devm_spi_register_master(&pdev->dev, master);
  1045. if (ret != 0) {
  1046. dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
  1047. goto err_pm_put;
  1048. }
  1049. dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
  1050. sdd->port_id, master->num_chipselect);
  1051. dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
  1052. mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1);
  1053. pm_runtime_mark_last_busy(&pdev->dev);
  1054. pm_runtime_put_autosuspend(&pdev->dev);
  1055. return 0;
  1056. err_pm_put:
  1057. pm_runtime_put_noidle(&pdev->dev);
  1058. pm_runtime_disable(&pdev->dev);
  1059. pm_runtime_set_suspended(&pdev->dev);
  1060. if (!is_polling(sdd))
  1061. dma_release_channel(sdd->tx_dma.ch);
  1062. err_release_rx_dma:
  1063. if (!is_polling(sdd))
  1064. dma_release_channel(sdd->rx_dma.ch);
  1065. err_disable_io_clk:
  1066. clk_disable_unprepare(sdd->ioclk);
  1067. err_disable_src_clk:
  1068. clk_disable_unprepare(sdd->src_clk);
  1069. err_disable_clk:
  1070. clk_disable_unprepare(sdd->clk);
  1071. err_deref_master:
  1072. spi_master_put(master);
  1073. return ret;
  1074. }
  1075. static int s3c64xx_spi_remove(struct platform_device *pdev)
  1076. {
  1077. struct spi_master *master = platform_get_drvdata(pdev);
  1078. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  1079. pm_runtime_get_sync(&pdev->dev);
  1080. writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
  1081. if (!is_polling(sdd)) {
  1082. dma_release_channel(sdd->rx_dma.ch);
  1083. dma_release_channel(sdd->tx_dma.ch);
  1084. }
  1085. clk_disable_unprepare(sdd->ioclk);
  1086. clk_disable_unprepare(sdd->src_clk);
  1087. clk_disable_unprepare(sdd->clk);
  1088. pm_runtime_put_noidle(&pdev->dev);
  1089. pm_runtime_disable(&pdev->dev);
  1090. pm_runtime_set_suspended(&pdev->dev);
  1091. return 0;
  1092. }
  1093. #ifdef CONFIG_PM_SLEEP
  1094. static int s3c64xx_spi_suspend(struct device *dev)
  1095. {
  1096. struct spi_master *master = dev_get_drvdata(dev);
  1097. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  1098. int ret = spi_master_suspend(master);
  1099. if (ret)
  1100. return ret;
  1101. ret = pm_runtime_force_suspend(dev);
  1102. if (ret < 0)
  1103. return ret;
  1104. sdd->cur_speed = 0; /* Output Clock is stopped */
  1105. return 0;
  1106. }
  1107. static int s3c64xx_spi_resume(struct device *dev)
  1108. {
  1109. struct spi_master *master = dev_get_drvdata(dev);
  1110. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  1111. struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
  1112. int ret;
  1113. if (sci->cfg_gpio)
  1114. sci->cfg_gpio();
  1115. ret = pm_runtime_force_resume(dev);
  1116. if (ret < 0)
  1117. return ret;
  1118. return spi_master_resume(master);
  1119. }
  1120. #endif /* CONFIG_PM_SLEEP */
  1121. #ifdef CONFIG_PM
  1122. static int s3c64xx_spi_runtime_suspend(struct device *dev)
  1123. {
  1124. struct spi_master *master = dev_get_drvdata(dev);
  1125. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  1126. clk_disable_unprepare(sdd->clk);
  1127. clk_disable_unprepare(sdd->src_clk);
  1128. clk_disable_unprepare(sdd->ioclk);
  1129. return 0;
  1130. }
  1131. static int s3c64xx_spi_runtime_resume(struct device *dev)
  1132. {
  1133. struct spi_master *master = dev_get_drvdata(dev);
  1134. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  1135. int ret;
  1136. if (sdd->port_conf->clk_ioclk) {
  1137. ret = clk_prepare_enable(sdd->ioclk);
  1138. if (ret != 0)
  1139. return ret;
  1140. }
  1141. ret = clk_prepare_enable(sdd->src_clk);
  1142. if (ret != 0)
  1143. goto err_disable_ioclk;
  1144. ret = clk_prepare_enable(sdd->clk);
  1145. if (ret != 0)
  1146. goto err_disable_src_clk;
  1147. s3c64xx_spi_hwinit(sdd);
  1148. writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
  1149. S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
  1150. sdd->regs + S3C64XX_SPI_INT_EN);
  1151. return 0;
  1152. err_disable_src_clk:
  1153. clk_disable_unprepare(sdd->src_clk);
  1154. err_disable_ioclk:
  1155. clk_disable_unprepare(sdd->ioclk);
  1156. return ret;
  1157. }
  1158. #endif /* CONFIG_PM */
  1159. static const struct dev_pm_ops s3c64xx_spi_pm = {
  1160. SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
  1161. SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
  1162. s3c64xx_spi_runtime_resume, NULL)
  1163. };
  1164. static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
  1165. .fifo_lvl_mask = { 0x7f },
  1166. .rx_lvl_offset = 13,
  1167. .tx_st_done = 21,
  1168. .high_speed = true,
  1169. };
  1170. static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
  1171. .fifo_lvl_mask = { 0x7f, 0x7F },
  1172. .rx_lvl_offset = 13,
  1173. .tx_st_done = 21,
  1174. };
  1175. static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
  1176. .fifo_lvl_mask = { 0x1ff, 0x7F },
  1177. .rx_lvl_offset = 15,
  1178. .tx_st_done = 25,
  1179. .high_speed = true,
  1180. };
  1181. static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
  1182. .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
  1183. .rx_lvl_offset = 15,
  1184. .tx_st_done = 25,
  1185. .high_speed = true,
  1186. .clk_from_cmu = true,
  1187. .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
  1188. };
  1189. static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
  1190. .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
  1191. .rx_lvl_offset = 15,
  1192. .tx_st_done = 25,
  1193. .high_speed = true,
  1194. .clk_from_cmu = true,
  1195. .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
  1196. };
  1197. static struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
  1198. .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
  1199. .rx_lvl_offset = 15,
  1200. .tx_st_done = 25,
  1201. .high_speed = true,
  1202. .clk_from_cmu = true,
  1203. .clk_ioclk = true,
  1204. .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
  1205. };
  1206. static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
  1207. {
  1208. .name = "s3c2443-spi",
  1209. .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
  1210. }, {
  1211. .name = "s3c6410-spi",
  1212. .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
  1213. },
  1214. { },
  1215. };
  1216. static const struct of_device_id s3c64xx_spi_dt_match[] = {
  1217. { .compatible = "samsung,s3c2443-spi",
  1218. .data = (void *)&s3c2443_spi_port_config,
  1219. },
  1220. { .compatible = "samsung,s3c6410-spi",
  1221. .data = (void *)&s3c6410_spi_port_config,
  1222. },
  1223. { .compatible = "samsung,s5pv210-spi",
  1224. .data = (void *)&s5pv210_spi_port_config,
  1225. },
  1226. { .compatible = "samsung,exynos4210-spi",
  1227. .data = (void *)&exynos4_spi_port_config,
  1228. },
  1229. { .compatible = "samsung,exynos7-spi",
  1230. .data = (void *)&exynos7_spi_port_config,
  1231. },
  1232. { .compatible = "samsung,exynos5433-spi",
  1233. .data = (void *)&exynos5433_spi_port_config,
  1234. },
  1235. { },
  1236. };
  1237. MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
  1238. static struct platform_driver s3c64xx_spi_driver = {
  1239. .driver = {
  1240. .name = "s3c64xx-spi",
  1241. .pm = &s3c64xx_spi_pm,
  1242. .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
  1243. },
  1244. .probe = s3c64xx_spi_probe,
  1245. .remove = s3c64xx_spi_remove,
  1246. .id_table = s3c64xx_spi_driver_ids,
  1247. };
  1248. MODULE_ALIAS("platform:s3c64xx-spi");
  1249. module_platform_driver(s3c64xx_spi_driver);
  1250. MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
  1251. MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
  1252. MODULE_LICENSE("GPL");