spi-rspi.c 37 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SH RSPI driver
  4. *
  5. * Copyright (C) 2012, 2013 Renesas Solutions Corp.
  6. * Copyright (C) 2014 Glider bvba
  7. *
  8. * Based on spi-sh.c:
  9. * Copyright (C) 2011 Renesas Solutions Corp.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/sched.h>
  14. #include <linux/errno.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/io.h>
  18. #include <linux/clk.h>
  19. #include <linux/dmaengine.h>
  20. #include <linux/dma-mapping.h>
  21. #include <linux/of_device.h>
  22. #include <linux/pm_runtime.h>
  23. #include <linux/sh_dma.h>
  24. #include <linux/spi/spi.h>
  25. #include <linux/spi/rspi.h>
  26. #include <linux/spinlock.h>
  27. #define RSPI_SPCR 0x00 /* Control Register */
  28. #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
  29. #define RSPI_SPPCR 0x02 /* Pin Control Register */
  30. #define RSPI_SPSR 0x03 /* Status Register */
  31. #define RSPI_SPDR 0x04 /* Data Register */
  32. #define RSPI_SPSCR 0x08 /* Sequence Control Register */
  33. #define RSPI_SPSSR 0x09 /* Sequence Status Register */
  34. #define RSPI_SPBR 0x0a /* Bit Rate Register */
  35. #define RSPI_SPDCR 0x0b /* Data Control Register */
  36. #define RSPI_SPCKD 0x0c /* Clock Delay Register */
  37. #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
  38. #define RSPI_SPND 0x0e /* Next-Access Delay Register */
  39. #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */
  40. #define RSPI_SPCMD0 0x10 /* Command Register 0 */
  41. #define RSPI_SPCMD1 0x12 /* Command Register 1 */
  42. #define RSPI_SPCMD2 0x14 /* Command Register 2 */
  43. #define RSPI_SPCMD3 0x16 /* Command Register 3 */
  44. #define RSPI_SPCMD4 0x18 /* Command Register 4 */
  45. #define RSPI_SPCMD5 0x1a /* Command Register 5 */
  46. #define RSPI_SPCMD6 0x1c /* Command Register 6 */
  47. #define RSPI_SPCMD7 0x1e /* Command Register 7 */
  48. #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2)
  49. #define RSPI_NUM_SPCMD 8
  50. #define RSPI_RZ_NUM_SPCMD 4
  51. #define QSPI_NUM_SPCMD 4
  52. /* RSPI on RZ only */
  53. #define RSPI_SPBFCR 0x20 /* Buffer Control Register */
  54. #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
  55. /* QSPI only */
  56. #define QSPI_SPBFCR 0x18 /* Buffer Control Register */
  57. #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
  58. #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
  59. #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
  60. #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
  61. #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
  62. #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4)
  63. /* SPCR - Control Register */
  64. #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
  65. #define SPCR_SPE 0x40 /* Function Enable */
  66. #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */
  67. #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */
  68. #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
  69. #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
  70. /* RSPI on SH only */
  71. #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
  72. #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
  73. /* QSPI on R-Car Gen2 only */
  74. #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
  75. #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
  76. /* SSLP - Slave Select Polarity Register */
  77. #define SSLP_SSLP(i) BIT(i) /* SSLi Signal Polarity Setting */
  78. /* SPPCR - Pin Control Register */
  79. #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
  80. #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */
  81. #define SPPCR_SPOM 0x04
  82. #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
  83. #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
  84. #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
  85. #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
  86. /* SPSR - Status Register */
  87. #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */
  88. #define SPSR_TEND 0x40 /* Transmit End */
  89. #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */
  90. #define SPSR_PERF 0x08 /* Parity Error Flag */
  91. #define SPSR_MODF 0x04 /* Mode Fault Error Flag */
  92. #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
  93. #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */
  94. /* SPSCR - Sequence Control Register */
  95. #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
  96. /* SPSSR - Sequence Status Register */
  97. #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */
  98. #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */
  99. /* SPDCR - Data Control Register */
  100. #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */
  101. #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */
  102. #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */
  103. #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
  104. #define SPDCR_SPLWORD SPDCR_SPLW1
  105. #define SPDCR_SPLBYTE SPDCR_SPLW0
  106. #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
  107. #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */
  108. #define SPDCR_SLSEL1 0x08
  109. #define SPDCR_SLSEL0 0x04
  110. #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */
  111. #define SPDCR_SPFC1 0x02
  112. #define SPDCR_SPFC0 0x01
  113. #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
  114. /* SPCKD - Clock Delay Register */
  115. #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
  116. /* SSLND - Slave Select Negation Delay Register */
  117. #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
  118. /* SPND - Next-Access Delay Register */
  119. #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
  120. /* SPCR2 - Control Register 2 */
  121. #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
  122. #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */
  123. #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */
  124. #define SPCR2_SPPE 0x01 /* Parity Enable */
  125. /* SPCMDn - Command Registers */
  126. #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */
  127. #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */
  128. #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
  129. #define SPCMD_LSBF 0x1000 /* LSB First */
  130. #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
  131. #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
  132. #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */
  133. #define SPCMD_SPB_16BIT 0x0100
  134. #define SPCMD_SPB_20BIT 0x0000
  135. #define SPCMD_SPB_24BIT 0x0100
  136. #define SPCMD_SPB_32BIT 0x0200
  137. #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */
  138. #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */
  139. #define SPCMD_SPIMOD1 0x0040
  140. #define SPCMD_SPIMOD0 0x0020
  141. #define SPCMD_SPIMOD_SINGLE 0
  142. #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0
  143. #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1
  144. #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */
  145. #define SPCMD_SSLA(i) ((i) << 4) /* SSL Assert Signal Setting */
  146. #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
  147. #define SPCMD_BRDV(brdv) ((brdv) << 2)
  148. #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
  149. #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
  150. /* SPBFCR - Buffer Control Register */
  151. #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */
  152. #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */
  153. #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
  154. #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
  155. /* QSPI on R-Car Gen2 */
  156. #define SPBFCR_TXTRG_1B 0x00 /* 31 bytes (1 byte available) */
  157. #define SPBFCR_TXTRG_32B 0x30 /* 0 byte (32 bytes available) */
  158. #define SPBFCR_RXTRG_1B 0x00 /* 1 byte (31 bytes available) */
  159. #define SPBFCR_RXTRG_32B 0x07 /* 32 bytes (0 byte available) */
  160. #define QSPI_BUFFER_SIZE 32u
  161. struct rspi_data {
  162. void __iomem *addr;
  163. u32 speed_hz;
  164. struct spi_controller *ctlr;
  165. struct platform_device *pdev;
  166. wait_queue_head_t wait;
  167. spinlock_t lock; /* Protects RMW-access to RSPI_SSLP */
  168. struct clk *clk;
  169. u16 spcmd;
  170. u8 spsr;
  171. u8 sppcr;
  172. int rx_irq, tx_irq;
  173. const struct spi_ops *ops;
  174. unsigned dma_callbacked:1;
  175. unsigned byte_access:1;
  176. };
  177. static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
  178. {
  179. iowrite8(data, rspi->addr + offset);
  180. }
  181. static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
  182. {
  183. iowrite16(data, rspi->addr + offset);
  184. }
  185. static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
  186. {
  187. iowrite32(data, rspi->addr + offset);
  188. }
  189. static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
  190. {
  191. return ioread8(rspi->addr + offset);
  192. }
  193. static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
  194. {
  195. return ioread16(rspi->addr + offset);
  196. }
  197. static void rspi_write_data(const struct rspi_data *rspi, u16 data)
  198. {
  199. if (rspi->byte_access)
  200. rspi_write8(rspi, data, RSPI_SPDR);
  201. else /* 16 bit */
  202. rspi_write16(rspi, data, RSPI_SPDR);
  203. }
  204. static u16 rspi_read_data(const struct rspi_data *rspi)
  205. {
  206. if (rspi->byte_access)
  207. return rspi_read8(rspi, RSPI_SPDR);
  208. else /* 16 bit */
  209. return rspi_read16(rspi, RSPI_SPDR);
  210. }
  211. /* optional functions */
  212. struct spi_ops {
  213. int (*set_config_register)(struct rspi_data *rspi, int access_size);
  214. int (*transfer_one)(struct spi_controller *ctlr,
  215. struct spi_device *spi, struct spi_transfer *xfer);
  216. u16 extra_mode_bits;
  217. u16 min_div;
  218. u16 max_div;
  219. u16 flags;
  220. u16 fifo_size;
  221. u8 num_hw_ss;
  222. };
  223. static void rspi_set_rate(struct rspi_data *rspi)
  224. {
  225. unsigned long clksrc;
  226. int brdv = 0, spbr;
  227. clksrc = clk_get_rate(rspi->clk);
  228. spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1;
  229. while (spbr > 255 && brdv < 3) {
  230. brdv++;
  231. spbr = DIV_ROUND_UP(spbr + 1, 2) - 1;
  232. }
  233. rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
  234. rspi->spcmd |= SPCMD_BRDV(brdv);
  235. rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * (spbr + 1));
  236. }
  237. /*
  238. * functions for RSPI on legacy SH
  239. */
  240. static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
  241. {
  242. /* Sets output mode, MOSI signal, and (optionally) loopback */
  243. rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
  244. /* Sets transfer bit rate */
  245. rspi_set_rate(rspi);
  246. /* Disable dummy transmission, set 16-bit word access, 1 frame */
  247. rspi_write8(rspi, 0, RSPI_SPDCR);
  248. rspi->byte_access = 0;
  249. /* Sets RSPCK, SSL, next-access delay value */
  250. rspi_write8(rspi, 0x00, RSPI_SPCKD);
  251. rspi_write8(rspi, 0x00, RSPI_SSLND);
  252. rspi_write8(rspi, 0x00, RSPI_SPND);
  253. /* Sets parity, interrupt mask */
  254. rspi_write8(rspi, 0x00, RSPI_SPCR2);
  255. /* Resets sequencer */
  256. rspi_write8(rspi, 0, RSPI_SPSCR);
  257. rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
  258. rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
  259. /* Sets RSPI mode */
  260. rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
  261. return 0;
  262. }
  263. /*
  264. * functions for RSPI on RZ
  265. */
  266. static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
  267. {
  268. /* Sets output mode, MOSI signal, and (optionally) loopback */
  269. rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
  270. /* Sets transfer bit rate */
  271. rspi_set_rate(rspi);
  272. /* Disable dummy transmission, set byte access */
  273. rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
  274. rspi->byte_access = 1;
  275. /* Sets RSPCK, SSL, next-access delay value */
  276. rspi_write8(rspi, 0x00, RSPI_SPCKD);
  277. rspi_write8(rspi, 0x00, RSPI_SSLND);
  278. rspi_write8(rspi, 0x00, RSPI_SPND);
  279. /* Resets sequencer */
  280. rspi_write8(rspi, 0, RSPI_SPSCR);
  281. rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
  282. rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
  283. /* Sets RSPI mode */
  284. rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
  285. return 0;
  286. }
  287. /*
  288. * functions for QSPI
  289. */
  290. static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
  291. {
  292. unsigned long clksrc;
  293. int brdv = 0, spbr;
  294. /* Sets output mode, MOSI signal, and (optionally) loopback */
  295. rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
  296. /* Sets transfer bit rate */
  297. clksrc = clk_get_rate(rspi->clk);
  298. if (rspi->speed_hz >= clksrc) {
  299. spbr = 0;
  300. rspi->speed_hz = clksrc;
  301. } else {
  302. spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz);
  303. while (spbr > 255 && brdv < 3) {
  304. brdv++;
  305. spbr = DIV_ROUND_UP(spbr, 2);
  306. }
  307. spbr = clamp(spbr, 0, 255);
  308. rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * spbr);
  309. }
  310. rspi_write8(rspi, spbr, RSPI_SPBR);
  311. rspi->spcmd |= SPCMD_BRDV(brdv);
  312. /* Disable dummy transmission, set byte access */
  313. rspi_write8(rspi, 0, RSPI_SPDCR);
  314. rspi->byte_access = 1;
  315. /* Sets RSPCK, SSL, next-access delay value */
  316. rspi_write8(rspi, 0x00, RSPI_SPCKD);
  317. rspi_write8(rspi, 0x00, RSPI_SSLND);
  318. rspi_write8(rspi, 0x00, RSPI_SPND);
  319. /* Data Length Setting */
  320. if (access_size == 8)
  321. rspi->spcmd |= SPCMD_SPB_8BIT;
  322. else if (access_size == 16)
  323. rspi->spcmd |= SPCMD_SPB_16BIT;
  324. else
  325. rspi->spcmd |= SPCMD_SPB_32BIT;
  326. rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
  327. /* Resets transfer data length */
  328. rspi_write32(rspi, 0, QSPI_SPBMUL0);
  329. /* Resets transmit and receive buffer */
  330. rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
  331. /* Sets buffer to allow normal operation */
  332. rspi_write8(rspi, 0x00, QSPI_SPBFCR);
  333. /* Resets sequencer */
  334. rspi_write8(rspi, 0, RSPI_SPSCR);
  335. rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
  336. /* Sets RSPI mode */
  337. rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
  338. return 0;
  339. }
  340. static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg)
  341. {
  342. u8 data;
  343. data = rspi_read8(rspi, reg);
  344. data &= ~mask;
  345. data |= (val & mask);
  346. rspi_write8(rspi, data, reg);
  347. }
  348. static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
  349. unsigned int len)
  350. {
  351. unsigned int n;
  352. n = min(len, QSPI_BUFFER_SIZE);
  353. if (len >= QSPI_BUFFER_SIZE) {
  354. /* sets triggering number to 32 bytes */
  355. qspi_update(rspi, SPBFCR_TXTRG_MASK,
  356. SPBFCR_TXTRG_32B, QSPI_SPBFCR);
  357. } else {
  358. /* sets triggering number to 1 byte */
  359. qspi_update(rspi, SPBFCR_TXTRG_MASK,
  360. SPBFCR_TXTRG_1B, QSPI_SPBFCR);
  361. }
  362. return n;
  363. }
  364. static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
  365. {
  366. unsigned int n;
  367. n = min(len, QSPI_BUFFER_SIZE);
  368. if (len >= QSPI_BUFFER_SIZE) {
  369. /* sets triggering number to 32 bytes */
  370. qspi_update(rspi, SPBFCR_RXTRG_MASK,
  371. SPBFCR_RXTRG_32B, QSPI_SPBFCR);
  372. } else {
  373. /* sets triggering number to 1 byte */
  374. qspi_update(rspi, SPBFCR_RXTRG_MASK,
  375. SPBFCR_RXTRG_1B, QSPI_SPBFCR);
  376. }
  377. return n;
  378. }
  379. static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
  380. {
  381. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
  382. }
  383. static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
  384. {
  385. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
  386. }
  387. static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
  388. u8 enable_bit)
  389. {
  390. int ret;
  391. rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
  392. if (rspi->spsr & wait_mask)
  393. return 0;
  394. rspi_enable_irq(rspi, enable_bit);
  395. ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
  396. if (ret == 0 && !(rspi->spsr & wait_mask))
  397. return -ETIMEDOUT;
  398. return 0;
  399. }
  400. static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
  401. {
  402. return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
  403. }
  404. static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
  405. {
  406. return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
  407. }
  408. static int rspi_data_out(struct rspi_data *rspi, u8 data)
  409. {
  410. int error = rspi_wait_for_tx_empty(rspi);
  411. if (error < 0) {
  412. dev_err(&rspi->ctlr->dev, "transmit timeout\n");
  413. return error;
  414. }
  415. rspi_write_data(rspi, data);
  416. return 0;
  417. }
  418. static int rspi_data_in(struct rspi_data *rspi)
  419. {
  420. int error;
  421. u8 data;
  422. error = rspi_wait_for_rx_full(rspi);
  423. if (error < 0) {
  424. dev_err(&rspi->ctlr->dev, "receive timeout\n");
  425. return error;
  426. }
  427. data = rspi_read_data(rspi);
  428. return data;
  429. }
  430. static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
  431. unsigned int n)
  432. {
  433. while (n-- > 0) {
  434. if (tx) {
  435. int ret = rspi_data_out(rspi, *tx++);
  436. if (ret < 0)
  437. return ret;
  438. }
  439. if (rx) {
  440. int ret = rspi_data_in(rspi);
  441. if (ret < 0)
  442. return ret;
  443. *rx++ = ret;
  444. }
  445. }
  446. return 0;
  447. }
  448. static void rspi_dma_complete(void *arg)
  449. {
  450. struct rspi_data *rspi = arg;
  451. rspi->dma_callbacked = 1;
  452. wake_up_interruptible(&rspi->wait);
  453. }
  454. static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
  455. struct sg_table *rx)
  456. {
  457. struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
  458. u8 irq_mask = 0;
  459. unsigned int other_irq = 0;
  460. dma_cookie_t cookie;
  461. int ret;
  462. /* First prepare and submit the DMA request(s), as this may fail */
  463. if (rx) {
  464. desc_rx = dmaengine_prep_slave_sg(rspi->ctlr->dma_rx, rx->sgl,
  465. rx->nents, DMA_DEV_TO_MEM,
  466. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  467. if (!desc_rx) {
  468. ret = -EAGAIN;
  469. goto no_dma_rx;
  470. }
  471. desc_rx->callback = rspi_dma_complete;
  472. desc_rx->callback_param = rspi;
  473. cookie = dmaengine_submit(desc_rx);
  474. if (dma_submit_error(cookie)) {
  475. ret = cookie;
  476. goto no_dma_rx;
  477. }
  478. irq_mask |= SPCR_SPRIE;
  479. }
  480. if (tx) {
  481. desc_tx = dmaengine_prep_slave_sg(rspi->ctlr->dma_tx, tx->sgl,
  482. tx->nents, DMA_MEM_TO_DEV,
  483. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  484. if (!desc_tx) {
  485. ret = -EAGAIN;
  486. goto no_dma_tx;
  487. }
  488. if (rx) {
  489. /* No callback */
  490. desc_tx->callback = NULL;
  491. } else {
  492. desc_tx->callback = rspi_dma_complete;
  493. desc_tx->callback_param = rspi;
  494. }
  495. cookie = dmaengine_submit(desc_tx);
  496. if (dma_submit_error(cookie)) {
  497. ret = cookie;
  498. goto no_dma_tx;
  499. }
  500. irq_mask |= SPCR_SPTIE;
  501. }
  502. /*
  503. * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be
  504. * called. So, this driver disables the IRQ while DMA transfer.
  505. */
  506. if (tx)
  507. disable_irq(other_irq = rspi->tx_irq);
  508. if (rx && rspi->rx_irq != other_irq)
  509. disable_irq(rspi->rx_irq);
  510. rspi_enable_irq(rspi, irq_mask);
  511. rspi->dma_callbacked = 0;
  512. /* Now start DMA */
  513. if (rx)
  514. dma_async_issue_pending(rspi->ctlr->dma_rx);
  515. if (tx)
  516. dma_async_issue_pending(rspi->ctlr->dma_tx);
  517. ret = wait_event_interruptible_timeout(rspi->wait,
  518. rspi->dma_callbacked, HZ);
  519. if (ret > 0 && rspi->dma_callbacked) {
  520. ret = 0;
  521. } else {
  522. if (!ret) {
  523. dev_err(&rspi->ctlr->dev, "DMA timeout\n");
  524. ret = -ETIMEDOUT;
  525. }
  526. if (tx)
  527. dmaengine_terminate_all(rspi->ctlr->dma_tx);
  528. if (rx)
  529. dmaengine_terminate_all(rspi->ctlr->dma_rx);
  530. }
  531. rspi_disable_irq(rspi, irq_mask);
  532. if (tx)
  533. enable_irq(rspi->tx_irq);
  534. if (rx && rspi->rx_irq != other_irq)
  535. enable_irq(rspi->rx_irq);
  536. return ret;
  537. no_dma_tx:
  538. if (rx)
  539. dmaengine_terminate_all(rspi->ctlr->dma_rx);
  540. no_dma_rx:
  541. if (ret == -EAGAIN) {
  542. dev_warn_once(&rspi->ctlr->dev,
  543. "DMA not available, falling back to PIO\n");
  544. }
  545. return ret;
  546. }
  547. static void rspi_receive_init(const struct rspi_data *rspi)
  548. {
  549. u8 spsr;
  550. spsr = rspi_read8(rspi, RSPI_SPSR);
  551. if (spsr & SPSR_SPRF)
  552. rspi_read_data(rspi); /* dummy read */
  553. if (spsr & SPSR_OVRF)
  554. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
  555. RSPI_SPSR);
  556. }
  557. static void rspi_rz_receive_init(const struct rspi_data *rspi)
  558. {
  559. rspi_receive_init(rspi);
  560. rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
  561. rspi_write8(rspi, 0, RSPI_SPBFCR);
  562. }
  563. static void qspi_receive_init(const struct rspi_data *rspi)
  564. {
  565. u8 spsr;
  566. spsr = rspi_read8(rspi, RSPI_SPSR);
  567. if (spsr & SPSR_SPRF)
  568. rspi_read_data(rspi); /* dummy read */
  569. rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
  570. rspi_write8(rspi, 0, QSPI_SPBFCR);
  571. }
  572. static bool __rspi_can_dma(const struct rspi_data *rspi,
  573. const struct spi_transfer *xfer)
  574. {
  575. return xfer->len > rspi->ops->fifo_size;
  576. }
  577. static bool rspi_can_dma(struct spi_controller *ctlr, struct spi_device *spi,
  578. struct spi_transfer *xfer)
  579. {
  580. struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
  581. return __rspi_can_dma(rspi, xfer);
  582. }
  583. static int rspi_dma_check_then_transfer(struct rspi_data *rspi,
  584. struct spi_transfer *xfer)
  585. {
  586. if (!rspi->ctlr->can_dma || !__rspi_can_dma(rspi, xfer))
  587. return -EAGAIN;
  588. /* rx_buf can be NULL on RSPI on SH in TX-only Mode */
  589. return rspi_dma_transfer(rspi, &xfer->tx_sg,
  590. xfer->rx_buf ? &xfer->rx_sg : NULL);
  591. }
  592. static int rspi_common_transfer(struct rspi_data *rspi,
  593. struct spi_transfer *xfer)
  594. {
  595. int ret;
  596. xfer->effective_speed_hz = rspi->speed_hz;
  597. ret = rspi_dma_check_then_transfer(rspi, xfer);
  598. if (ret != -EAGAIN)
  599. return ret;
  600. ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
  601. if (ret < 0)
  602. return ret;
  603. /* Wait for the last transmission */
  604. rspi_wait_for_tx_empty(rspi);
  605. return 0;
  606. }
  607. static int rspi_transfer_one(struct spi_controller *ctlr,
  608. struct spi_device *spi, struct spi_transfer *xfer)
  609. {
  610. struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
  611. u8 spcr;
  612. spcr = rspi_read8(rspi, RSPI_SPCR);
  613. if (xfer->rx_buf) {
  614. rspi_receive_init(rspi);
  615. spcr &= ~SPCR_TXMD;
  616. } else {
  617. spcr |= SPCR_TXMD;
  618. }
  619. rspi_write8(rspi, spcr, RSPI_SPCR);
  620. return rspi_common_transfer(rspi, xfer);
  621. }
  622. static int rspi_rz_transfer_one(struct spi_controller *ctlr,
  623. struct spi_device *spi,
  624. struct spi_transfer *xfer)
  625. {
  626. struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
  627. rspi_rz_receive_init(rspi);
  628. return rspi_common_transfer(rspi, xfer);
  629. }
  630. static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx,
  631. u8 *rx, unsigned int len)
  632. {
  633. unsigned int i, n;
  634. int ret;
  635. while (len > 0) {
  636. n = qspi_set_send_trigger(rspi, len);
  637. qspi_set_receive_trigger(rspi, len);
  638. ret = rspi_wait_for_tx_empty(rspi);
  639. if (ret < 0) {
  640. dev_err(&rspi->ctlr->dev, "transmit timeout\n");
  641. return ret;
  642. }
  643. for (i = 0; i < n; i++)
  644. rspi_write_data(rspi, *tx++);
  645. ret = rspi_wait_for_rx_full(rspi);
  646. if (ret < 0) {
  647. dev_err(&rspi->ctlr->dev, "receive timeout\n");
  648. return ret;
  649. }
  650. for (i = 0; i < n; i++)
  651. *rx++ = rspi_read_data(rspi);
  652. len -= n;
  653. }
  654. return 0;
  655. }
  656. static int qspi_transfer_out_in(struct rspi_data *rspi,
  657. struct spi_transfer *xfer)
  658. {
  659. int ret;
  660. qspi_receive_init(rspi);
  661. ret = rspi_dma_check_then_transfer(rspi, xfer);
  662. if (ret != -EAGAIN)
  663. return ret;
  664. return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf,
  665. xfer->rx_buf, xfer->len);
  666. }
  667. static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
  668. {
  669. const u8 *tx = xfer->tx_buf;
  670. unsigned int n = xfer->len;
  671. unsigned int i, len;
  672. int ret;
  673. if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
  674. ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
  675. if (ret != -EAGAIN)
  676. return ret;
  677. }
  678. while (n > 0) {
  679. len = qspi_set_send_trigger(rspi, n);
  680. ret = rspi_wait_for_tx_empty(rspi);
  681. if (ret < 0) {
  682. dev_err(&rspi->ctlr->dev, "transmit timeout\n");
  683. return ret;
  684. }
  685. for (i = 0; i < len; i++)
  686. rspi_write_data(rspi, *tx++);
  687. n -= len;
  688. }
  689. /* Wait for the last transmission */
  690. rspi_wait_for_tx_empty(rspi);
  691. return 0;
  692. }
  693. static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
  694. {
  695. u8 *rx = xfer->rx_buf;
  696. unsigned int n = xfer->len;
  697. unsigned int i, len;
  698. int ret;
  699. if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
  700. int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
  701. if (ret != -EAGAIN)
  702. return ret;
  703. }
  704. while (n > 0) {
  705. len = qspi_set_receive_trigger(rspi, n);
  706. ret = rspi_wait_for_rx_full(rspi);
  707. if (ret < 0) {
  708. dev_err(&rspi->ctlr->dev, "receive timeout\n");
  709. return ret;
  710. }
  711. for (i = 0; i < len; i++)
  712. *rx++ = rspi_read_data(rspi);
  713. n -= len;
  714. }
  715. return 0;
  716. }
  717. static int qspi_transfer_one(struct spi_controller *ctlr,
  718. struct spi_device *spi, struct spi_transfer *xfer)
  719. {
  720. struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
  721. xfer->effective_speed_hz = rspi->speed_hz;
  722. if (spi->mode & SPI_LOOP) {
  723. return qspi_transfer_out_in(rspi, xfer);
  724. } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
  725. /* Quad or Dual SPI Write */
  726. return qspi_transfer_out(rspi, xfer);
  727. } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
  728. /* Quad or Dual SPI Read */
  729. return qspi_transfer_in(rspi, xfer);
  730. } else {
  731. /* Single SPI Transfer */
  732. return qspi_transfer_out_in(rspi, xfer);
  733. }
  734. }
  735. static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
  736. {
  737. if (xfer->tx_buf)
  738. switch (xfer->tx_nbits) {
  739. case SPI_NBITS_QUAD:
  740. return SPCMD_SPIMOD_QUAD;
  741. case SPI_NBITS_DUAL:
  742. return SPCMD_SPIMOD_DUAL;
  743. default:
  744. return 0;
  745. }
  746. if (xfer->rx_buf)
  747. switch (xfer->rx_nbits) {
  748. case SPI_NBITS_QUAD:
  749. return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
  750. case SPI_NBITS_DUAL:
  751. return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
  752. default:
  753. return 0;
  754. }
  755. return 0;
  756. }
  757. static int qspi_setup_sequencer(struct rspi_data *rspi,
  758. const struct spi_message *msg)
  759. {
  760. const struct spi_transfer *xfer;
  761. unsigned int i = 0, len = 0;
  762. u16 current_mode = 0xffff, mode;
  763. list_for_each_entry(xfer, &msg->transfers, transfer_list) {
  764. mode = qspi_transfer_mode(xfer);
  765. if (mode == current_mode) {
  766. len += xfer->len;
  767. continue;
  768. }
  769. /* Transfer mode change */
  770. if (i) {
  771. /* Set transfer data length of previous transfer */
  772. rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
  773. }
  774. if (i >= QSPI_NUM_SPCMD) {
  775. dev_err(&msg->spi->dev,
  776. "Too many different transfer modes");
  777. return -EINVAL;
  778. }
  779. /* Program transfer mode for this transfer */
  780. rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
  781. current_mode = mode;
  782. len = xfer->len;
  783. i++;
  784. }
  785. if (i) {
  786. /* Set final transfer data length and sequence length */
  787. rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
  788. rspi_write8(rspi, i - 1, RSPI_SPSCR);
  789. }
  790. return 0;
  791. }
  792. static int rspi_setup(struct spi_device *spi)
  793. {
  794. struct rspi_data *rspi = spi_controller_get_devdata(spi->controller);
  795. u8 sslp;
  796. if (spi->cs_gpiod)
  797. return 0;
  798. pm_runtime_get_sync(&rspi->pdev->dev);
  799. spin_lock_irq(&rspi->lock);
  800. sslp = rspi_read8(rspi, RSPI_SSLP);
  801. if (spi->mode & SPI_CS_HIGH)
  802. sslp |= SSLP_SSLP(spi->chip_select);
  803. else
  804. sslp &= ~SSLP_SSLP(spi->chip_select);
  805. rspi_write8(rspi, sslp, RSPI_SSLP);
  806. spin_unlock_irq(&rspi->lock);
  807. pm_runtime_put(&rspi->pdev->dev);
  808. return 0;
  809. }
  810. static int rspi_prepare_message(struct spi_controller *ctlr,
  811. struct spi_message *msg)
  812. {
  813. struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
  814. struct spi_device *spi = msg->spi;
  815. const struct spi_transfer *xfer;
  816. int ret;
  817. /*
  818. * As the Bit Rate Register must not be changed while the device is
  819. * active, all transfers in a message must use the same bit rate.
  820. * In theory, the sequencer could be enabled, and each Command Register
  821. * could divide the base bit rate by a different value.
  822. * However, most RSPI variants do not have Transfer Data Length
  823. * Multiplier Setting Registers, so each sequence step would be limited
  824. * to a single word, making this feature unsuitable for large
  825. * transfers, which would gain most from it.
  826. */
  827. rspi->speed_hz = spi->max_speed_hz;
  828. list_for_each_entry(xfer, &msg->transfers, transfer_list) {
  829. if (xfer->speed_hz < rspi->speed_hz)
  830. rspi->speed_hz = xfer->speed_hz;
  831. }
  832. rspi->spcmd = SPCMD_SSLKP;
  833. if (spi->mode & SPI_CPOL)
  834. rspi->spcmd |= SPCMD_CPOL;
  835. if (spi->mode & SPI_CPHA)
  836. rspi->spcmd |= SPCMD_CPHA;
  837. if (spi->mode & SPI_LSB_FIRST)
  838. rspi->spcmd |= SPCMD_LSBF;
  839. /* Configure slave signal to assert */
  840. rspi->spcmd |= SPCMD_SSLA(spi->cs_gpiod ? rspi->ctlr->unused_native_cs
  841. : spi->chip_select);
  842. /* CMOS output mode and MOSI signal from previous transfer */
  843. rspi->sppcr = 0;
  844. if (spi->mode & SPI_LOOP)
  845. rspi->sppcr |= SPPCR_SPLP;
  846. rspi->ops->set_config_register(rspi, 8);
  847. if (msg->spi->mode &
  848. (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
  849. /* Setup sequencer for messages with multiple transfer modes */
  850. ret = qspi_setup_sequencer(rspi, msg);
  851. if (ret < 0)
  852. return ret;
  853. }
  854. /* Enable SPI function in master mode */
  855. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
  856. return 0;
  857. }
  858. static int rspi_unprepare_message(struct spi_controller *ctlr,
  859. struct spi_message *msg)
  860. {
  861. struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
  862. /* Disable SPI function */
  863. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
  864. /* Reset sequencer for Single SPI Transfers */
  865. rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
  866. rspi_write8(rspi, 0, RSPI_SPSCR);
  867. return 0;
  868. }
  869. static irqreturn_t rspi_irq_mux(int irq, void *_sr)
  870. {
  871. struct rspi_data *rspi = _sr;
  872. u8 spsr;
  873. irqreturn_t ret = IRQ_NONE;
  874. u8 disable_irq = 0;
  875. rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
  876. if (spsr & SPSR_SPRF)
  877. disable_irq |= SPCR_SPRIE;
  878. if (spsr & SPSR_SPTEF)
  879. disable_irq |= SPCR_SPTIE;
  880. if (disable_irq) {
  881. ret = IRQ_HANDLED;
  882. rspi_disable_irq(rspi, disable_irq);
  883. wake_up(&rspi->wait);
  884. }
  885. return ret;
  886. }
  887. static irqreturn_t rspi_irq_rx(int irq, void *_sr)
  888. {
  889. struct rspi_data *rspi = _sr;
  890. u8 spsr;
  891. rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
  892. if (spsr & SPSR_SPRF) {
  893. rspi_disable_irq(rspi, SPCR_SPRIE);
  894. wake_up(&rspi->wait);
  895. return IRQ_HANDLED;
  896. }
  897. return 0;
  898. }
  899. static irqreturn_t rspi_irq_tx(int irq, void *_sr)
  900. {
  901. struct rspi_data *rspi = _sr;
  902. u8 spsr;
  903. rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
  904. if (spsr & SPSR_SPTEF) {
  905. rspi_disable_irq(rspi, SPCR_SPTIE);
  906. wake_up(&rspi->wait);
  907. return IRQ_HANDLED;
  908. }
  909. return 0;
  910. }
  911. static struct dma_chan *rspi_request_dma_chan(struct device *dev,
  912. enum dma_transfer_direction dir,
  913. unsigned int id,
  914. dma_addr_t port_addr)
  915. {
  916. dma_cap_mask_t mask;
  917. struct dma_chan *chan;
  918. struct dma_slave_config cfg;
  919. int ret;
  920. dma_cap_zero(mask);
  921. dma_cap_set(DMA_SLAVE, mask);
  922. chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
  923. (void *)(unsigned long)id, dev,
  924. dir == DMA_MEM_TO_DEV ? "tx" : "rx");
  925. if (!chan) {
  926. dev_warn(dev, "dma_request_slave_channel_compat failed\n");
  927. return NULL;
  928. }
  929. memset(&cfg, 0, sizeof(cfg));
  930. cfg.direction = dir;
  931. if (dir == DMA_MEM_TO_DEV) {
  932. cfg.dst_addr = port_addr;
  933. cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  934. } else {
  935. cfg.src_addr = port_addr;
  936. cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  937. }
  938. ret = dmaengine_slave_config(chan, &cfg);
  939. if (ret) {
  940. dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
  941. dma_release_channel(chan);
  942. return NULL;
  943. }
  944. return chan;
  945. }
  946. static int rspi_request_dma(struct device *dev, struct spi_controller *ctlr,
  947. const struct resource *res)
  948. {
  949. const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev);
  950. unsigned int dma_tx_id, dma_rx_id;
  951. if (dev->of_node) {
  952. /* In the OF case we will get the slave IDs from the DT */
  953. dma_tx_id = 0;
  954. dma_rx_id = 0;
  955. } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) {
  956. dma_tx_id = rspi_pd->dma_tx_id;
  957. dma_rx_id = rspi_pd->dma_rx_id;
  958. } else {
  959. /* The driver assumes no error. */
  960. return 0;
  961. }
  962. ctlr->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id,
  963. res->start + RSPI_SPDR);
  964. if (!ctlr->dma_tx)
  965. return -ENODEV;
  966. ctlr->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id,
  967. res->start + RSPI_SPDR);
  968. if (!ctlr->dma_rx) {
  969. dma_release_channel(ctlr->dma_tx);
  970. ctlr->dma_tx = NULL;
  971. return -ENODEV;
  972. }
  973. ctlr->can_dma = rspi_can_dma;
  974. dev_info(dev, "DMA available");
  975. return 0;
  976. }
  977. static void rspi_release_dma(struct spi_controller *ctlr)
  978. {
  979. if (ctlr->dma_tx)
  980. dma_release_channel(ctlr->dma_tx);
  981. if (ctlr->dma_rx)
  982. dma_release_channel(ctlr->dma_rx);
  983. }
  984. static int rspi_remove(struct platform_device *pdev)
  985. {
  986. struct rspi_data *rspi = platform_get_drvdata(pdev);
  987. rspi_release_dma(rspi->ctlr);
  988. pm_runtime_disable(&pdev->dev);
  989. return 0;
  990. }
  991. static const struct spi_ops rspi_ops = {
  992. .set_config_register = rspi_set_config_register,
  993. .transfer_one = rspi_transfer_one,
  994. .min_div = 2,
  995. .max_div = 4096,
  996. .flags = SPI_CONTROLLER_MUST_TX,
  997. .fifo_size = 8,
  998. .num_hw_ss = 2,
  999. };
  1000. static const struct spi_ops rspi_rz_ops = {
  1001. .set_config_register = rspi_rz_set_config_register,
  1002. .transfer_one = rspi_rz_transfer_one,
  1003. .min_div = 2,
  1004. .max_div = 4096,
  1005. .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX,
  1006. .fifo_size = 8, /* 8 for TX, 32 for RX */
  1007. .num_hw_ss = 1,
  1008. };
  1009. static const struct spi_ops qspi_ops = {
  1010. .set_config_register = qspi_set_config_register,
  1011. .transfer_one = qspi_transfer_one,
  1012. .extra_mode_bits = SPI_TX_DUAL | SPI_TX_QUAD |
  1013. SPI_RX_DUAL | SPI_RX_QUAD,
  1014. .min_div = 1,
  1015. .max_div = 4080,
  1016. .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX,
  1017. .fifo_size = 32,
  1018. .num_hw_ss = 1,
  1019. };
  1020. #ifdef CONFIG_OF
  1021. static const struct of_device_id rspi_of_match[] = {
  1022. /* RSPI on legacy SH */
  1023. { .compatible = "renesas,rspi", .data = &rspi_ops },
  1024. /* RSPI on RZ/A1H */
  1025. { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
  1026. /* QSPI on R-Car Gen2 */
  1027. { .compatible = "renesas,qspi", .data = &qspi_ops },
  1028. { /* sentinel */ }
  1029. };
  1030. MODULE_DEVICE_TABLE(of, rspi_of_match);
  1031. static int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr)
  1032. {
  1033. u32 num_cs;
  1034. int error;
  1035. /* Parse DT properties */
  1036. error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
  1037. if (error) {
  1038. dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
  1039. return error;
  1040. }
  1041. ctlr->num_chipselect = num_cs;
  1042. return 0;
  1043. }
  1044. #else
  1045. #define rspi_of_match NULL
  1046. static inline int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr)
  1047. {
  1048. return -EINVAL;
  1049. }
  1050. #endif /* CONFIG_OF */
  1051. static int rspi_request_irq(struct device *dev, unsigned int irq,
  1052. irq_handler_t handler, const char *suffix,
  1053. void *dev_id)
  1054. {
  1055. const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
  1056. dev_name(dev), suffix);
  1057. if (!name)
  1058. return -ENOMEM;
  1059. return devm_request_irq(dev, irq, handler, 0, name, dev_id);
  1060. }
  1061. static int rspi_probe(struct platform_device *pdev)
  1062. {
  1063. struct resource *res;
  1064. struct spi_controller *ctlr;
  1065. struct rspi_data *rspi;
  1066. int ret;
  1067. const struct rspi_plat_data *rspi_pd;
  1068. const struct spi_ops *ops;
  1069. unsigned long clksrc;
  1070. ctlr = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
  1071. if (ctlr == NULL)
  1072. return -ENOMEM;
  1073. ops = of_device_get_match_data(&pdev->dev);
  1074. if (ops) {
  1075. ret = rspi_parse_dt(&pdev->dev, ctlr);
  1076. if (ret)
  1077. goto error1;
  1078. } else {
  1079. ops = (struct spi_ops *)pdev->id_entry->driver_data;
  1080. rspi_pd = dev_get_platdata(&pdev->dev);
  1081. if (rspi_pd && rspi_pd->num_chipselect)
  1082. ctlr->num_chipselect = rspi_pd->num_chipselect;
  1083. else
  1084. ctlr->num_chipselect = 2; /* default */
  1085. }
  1086. rspi = spi_controller_get_devdata(ctlr);
  1087. platform_set_drvdata(pdev, rspi);
  1088. rspi->ops = ops;
  1089. rspi->ctlr = ctlr;
  1090. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1091. rspi->addr = devm_ioremap_resource(&pdev->dev, res);
  1092. if (IS_ERR(rspi->addr)) {
  1093. ret = PTR_ERR(rspi->addr);
  1094. goto error1;
  1095. }
  1096. rspi->clk = devm_clk_get(&pdev->dev, NULL);
  1097. if (IS_ERR(rspi->clk)) {
  1098. dev_err(&pdev->dev, "cannot get clock\n");
  1099. ret = PTR_ERR(rspi->clk);
  1100. goto error1;
  1101. }
  1102. rspi->pdev = pdev;
  1103. pm_runtime_enable(&pdev->dev);
  1104. init_waitqueue_head(&rspi->wait);
  1105. spin_lock_init(&rspi->lock);
  1106. ctlr->bus_num = pdev->id;
  1107. ctlr->setup = rspi_setup;
  1108. ctlr->auto_runtime_pm = true;
  1109. ctlr->transfer_one = ops->transfer_one;
  1110. ctlr->prepare_message = rspi_prepare_message;
  1111. ctlr->unprepare_message = rspi_unprepare_message;
  1112. ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
  1113. SPI_LOOP | ops->extra_mode_bits;
  1114. clksrc = clk_get_rate(rspi->clk);
  1115. ctlr->min_speed_hz = DIV_ROUND_UP(clksrc, ops->max_div);
  1116. ctlr->max_speed_hz = DIV_ROUND_UP(clksrc, ops->min_div);
  1117. ctlr->flags = ops->flags;
  1118. ctlr->dev.of_node = pdev->dev.of_node;
  1119. ctlr->use_gpio_descriptors = true;
  1120. ctlr->max_native_cs = rspi->ops->num_hw_ss;
  1121. ret = platform_get_irq_byname_optional(pdev, "rx");
  1122. if (ret < 0) {
  1123. ret = platform_get_irq_byname_optional(pdev, "mux");
  1124. if (ret < 0)
  1125. ret = platform_get_irq(pdev, 0);
  1126. if (ret >= 0)
  1127. rspi->rx_irq = rspi->tx_irq = ret;
  1128. } else {
  1129. rspi->rx_irq = ret;
  1130. ret = platform_get_irq_byname(pdev, "tx");
  1131. if (ret >= 0)
  1132. rspi->tx_irq = ret;
  1133. }
  1134. if (rspi->rx_irq == rspi->tx_irq) {
  1135. /* Single multiplexed interrupt */
  1136. ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
  1137. "mux", rspi);
  1138. } else {
  1139. /* Multi-interrupt mode, only SPRI and SPTI are used */
  1140. ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
  1141. "rx", rspi);
  1142. if (!ret)
  1143. ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
  1144. rspi_irq_tx, "tx", rspi);
  1145. }
  1146. if (ret < 0) {
  1147. dev_err(&pdev->dev, "request_irq error\n");
  1148. goto error2;
  1149. }
  1150. ret = rspi_request_dma(&pdev->dev, ctlr, res);
  1151. if (ret < 0)
  1152. dev_warn(&pdev->dev, "DMA not available, using PIO\n");
  1153. ret = devm_spi_register_controller(&pdev->dev, ctlr);
  1154. if (ret < 0) {
  1155. dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
  1156. goto error3;
  1157. }
  1158. dev_info(&pdev->dev, "probed\n");
  1159. return 0;
  1160. error3:
  1161. rspi_release_dma(ctlr);
  1162. error2:
  1163. pm_runtime_disable(&pdev->dev);
  1164. error1:
  1165. spi_controller_put(ctlr);
  1166. return ret;
  1167. }
  1168. static const struct platform_device_id spi_driver_ids[] = {
  1169. { "rspi", (kernel_ulong_t)&rspi_ops },
  1170. {},
  1171. };
  1172. MODULE_DEVICE_TABLE(platform, spi_driver_ids);
  1173. #ifdef CONFIG_PM_SLEEP
  1174. static int rspi_suspend(struct device *dev)
  1175. {
  1176. struct rspi_data *rspi = dev_get_drvdata(dev);
  1177. return spi_controller_suspend(rspi->ctlr);
  1178. }
  1179. static int rspi_resume(struct device *dev)
  1180. {
  1181. struct rspi_data *rspi = dev_get_drvdata(dev);
  1182. return spi_controller_resume(rspi->ctlr);
  1183. }
  1184. static SIMPLE_DEV_PM_OPS(rspi_pm_ops, rspi_suspend, rspi_resume);
  1185. #define DEV_PM_OPS &rspi_pm_ops
  1186. #else
  1187. #define DEV_PM_OPS NULL
  1188. #endif /* CONFIG_PM_SLEEP */
  1189. static struct platform_driver rspi_driver = {
  1190. .probe = rspi_probe,
  1191. .remove = rspi_remove,
  1192. .id_table = spi_driver_ids,
  1193. .driver = {
  1194. .name = "renesas_spi",
  1195. .pm = DEV_PM_OPS,
  1196. .of_match_table = of_match_ptr(rspi_of_match),
  1197. },
  1198. };
  1199. module_platform_driver(rspi_driver);
  1200. MODULE_DESCRIPTION("Renesas RSPI bus driver");
  1201. MODULE_LICENSE("GPL v2");
  1202. MODULE_AUTHOR("Yoshihiro Shimoda");
  1203. MODULE_ALIAS("platform:rspi");