spi-rockchip.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
  4. * Author: Addy Ke <addy.ke@rock-chips.com>
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/dmaengine.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/pinctrl/consumer.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/spi/spi.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/scatterlist.h>
  16. #define DRIVER_NAME "rockchip-spi"
  17. #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
  18. writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
  19. #define ROCKCHIP_SPI_SET_BITS(reg, bits) \
  20. writel_relaxed(readl_relaxed(reg) | (bits), reg)
  21. /* SPI register offsets */
  22. #define ROCKCHIP_SPI_CTRLR0 0x0000
  23. #define ROCKCHIP_SPI_CTRLR1 0x0004
  24. #define ROCKCHIP_SPI_SSIENR 0x0008
  25. #define ROCKCHIP_SPI_SER 0x000c
  26. #define ROCKCHIP_SPI_BAUDR 0x0010
  27. #define ROCKCHIP_SPI_TXFTLR 0x0014
  28. #define ROCKCHIP_SPI_RXFTLR 0x0018
  29. #define ROCKCHIP_SPI_TXFLR 0x001c
  30. #define ROCKCHIP_SPI_RXFLR 0x0020
  31. #define ROCKCHIP_SPI_SR 0x0024
  32. #define ROCKCHIP_SPI_IPR 0x0028
  33. #define ROCKCHIP_SPI_IMR 0x002c
  34. #define ROCKCHIP_SPI_ISR 0x0030
  35. #define ROCKCHIP_SPI_RISR 0x0034
  36. #define ROCKCHIP_SPI_ICR 0x0038
  37. #define ROCKCHIP_SPI_DMACR 0x003c
  38. #define ROCKCHIP_SPI_DMATDLR 0x0040
  39. #define ROCKCHIP_SPI_DMARDLR 0x0044
  40. #define ROCKCHIP_SPI_VERSION 0x0048
  41. #define ROCKCHIP_SPI_TXDR 0x0400
  42. #define ROCKCHIP_SPI_RXDR 0x0800
  43. /* Bit fields in CTRLR0 */
  44. #define CR0_DFS_OFFSET 0
  45. #define CR0_DFS_4BIT 0x0
  46. #define CR0_DFS_8BIT 0x1
  47. #define CR0_DFS_16BIT 0x2
  48. #define CR0_CFS_OFFSET 2
  49. #define CR0_SCPH_OFFSET 6
  50. #define CR0_SCPOL_OFFSET 7
  51. #define CR0_CSM_OFFSET 8
  52. #define CR0_CSM_KEEP 0x0
  53. /* ss_n be high for half sclk_out cycles */
  54. #define CR0_CSM_HALF 0X1
  55. /* ss_n be high for one sclk_out cycle */
  56. #define CR0_CSM_ONE 0x2
  57. /* ss_n to sclk_out delay */
  58. #define CR0_SSD_OFFSET 10
  59. /*
  60. * The period between ss_n active and
  61. * sclk_out active is half sclk_out cycles
  62. */
  63. #define CR0_SSD_HALF 0x0
  64. /*
  65. * The period between ss_n active and
  66. * sclk_out active is one sclk_out cycle
  67. */
  68. #define CR0_SSD_ONE 0x1
  69. #define CR0_EM_OFFSET 11
  70. #define CR0_EM_LITTLE 0x0
  71. #define CR0_EM_BIG 0x1
  72. #define CR0_FBM_OFFSET 12
  73. #define CR0_FBM_MSB 0x0
  74. #define CR0_FBM_LSB 0x1
  75. #define CR0_BHT_OFFSET 13
  76. #define CR0_BHT_16BIT 0x0
  77. #define CR0_BHT_8BIT 0x1
  78. #define CR0_RSD_OFFSET 14
  79. #define CR0_RSD_MAX 0x3
  80. #define CR0_FRF_OFFSET 16
  81. #define CR0_FRF_SPI 0x0
  82. #define CR0_FRF_SSP 0x1
  83. #define CR0_FRF_MICROWIRE 0x2
  84. #define CR0_XFM_OFFSET 18
  85. #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
  86. #define CR0_XFM_TR 0x0
  87. #define CR0_XFM_TO 0x1
  88. #define CR0_XFM_RO 0x2
  89. #define CR0_OPM_OFFSET 20
  90. #define CR0_OPM_MASTER 0x0
  91. #define CR0_OPM_SLAVE 0x1
  92. #define CR0_MTM_OFFSET 0x21
  93. /* Bit fields in SER, 2bit */
  94. #define SER_MASK 0x3
  95. /* Bit fields in BAUDR */
  96. #define BAUDR_SCKDV_MIN 2
  97. #define BAUDR_SCKDV_MAX 65534
  98. /* Bit fields in SR, 5bit */
  99. #define SR_MASK 0x1f
  100. #define SR_BUSY (1 << 0)
  101. #define SR_TF_FULL (1 << 1)
  102. #define SR_TF_EMPTY (1 << 2)
  103. #define SR_RF_EMPTY (1 << 3)
  104. #define SR_RF_FULL (1 << 4)
  105. /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
  106. #define INT_MASK 0x1f
  107. #define INT_TF_EMPTY (1 << 0)
  108. #define INT_TF_OVERFLOW (1 << 1)
  109. #define INT_RF_UNDERFLOW (1 << 2)
  110. #define INT_RF_OVERFLOW (1 << 3)
  111. #define INT_RF_FULL (1 << 4)
  112. /* Bit fields in ICR, 4bit */
  113. #define ICR_MASK 0x0f
  114. #define ICR_ALL (1 << 0)
  115. #define ICR_RF_UNDERFLOW (1 << 1)
  116. #define ICR_RF_OVERFLOW (1 << 2)
  117. #define ICR_TF_OVERFLOW (1 << 3)
  118. /* Bit fields in DMACR */
  119. #define RF_DMA_EN (1 << 0)
  120. #define TF_DMA_EN (1 << 1)
  121. /* Driver state flags */
  122. #define RXDMA (1 << 0)
  123. #define TXDMA (1 << 1)
  124. /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
  125. #define MAX_SCLK_OUT 50000000U
  126. /*
  127. * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
  128. * the controller seems to hang when given 0x10000, so stick with this for now.
  129. */
  130. #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
  131. #define ROCKCHIP_SPI_MAX_CS_NUM 2
  132. #define ROCKCHIP_SPI_VER2_TYPE1 0x05EC0002
  133. #define ROCKCHIP_SPI_VER2_TYPE2 0x00110002
  134. struct rockchip_spi {
  135. struct device *dev;
  136. struct clk *spiclk;
  137. struct clk *apb_pclk;
  138. void __iomem *regs;
  139. dma_addr_t dma_addr_rx;
  140. dma_addr_t dma_addr_tx;
  141. const void *tx;
  142. void *rx;
  143. unsigned int tx_left;
  144. unsigned int rx_left;
  145. atomic_t state;
  146. /*depth of the FIFO buffer */
  147. u32 fifo_len;
  148. /* frequency of spiclk */
  149. u32 freq;
  150. u8 n_bytes;
  151. u8 rsd;
  152. bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
  153. bool slave_abort;
  154. };
  155. static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
  156. {
  157. writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
  158. }
  159. static inline void wait_for_idle(struct rockchip_spi *rs)
  160. {
  161. unsigned long timeout = jiffies + msecs_to_jiffies(5);
  162. do {
  163. if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
  164. return;
  165. } while (!time_after(jiffies, timeout));
  166. dev_warn(rs->dev, "spi controller is in busy state!\n");
  167. }
  168. static u32 get_fifo_len(struct rockchip_spi *rs)
  169. {
  170. u32 ver;
  171. ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
  172. switch (ver) {
  173. case ROCKCHIP_SPI_VER2_TYPE1:
  174. case ROCKCHIP_SPI_VER2_TYPE2:
  175. return 64;
  176. default:
  177. return 32;
  178. }
  179. }
  180. static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
  181. {
  182. struct spi_controller *ctlr = spi->controller;
  183. struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
  184. bool cs_asserted = !enable;
  185. /* Return immediately for no-op */
  186. if (cs_asserted == rs->cs_asserted[spi->chip_select])
  187. return;
  188. if (cs_asserted) {
  189. /* Keep things powered as long as CS is asserted */
  190. pm_runtime_get_sync(rs->dev);
  191. ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER,
  192. BIT(spi->chip_select));
  193. } else {
  194. ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER,
  195. BIT(spi->chip_select));
  196. /* Drop reference from when we first asserted CS */
  197. pm_runtime_put(rs->dev);
  198. }
  199. rs->cs_asserted[spi->chip_select] = cs_asserted;
  200. }
  201. static void rockchip_spi_handle_err(struct spi_controller *ctlr,
  202. struct spi_message *msg)
  203. {
  204. struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
  205. /* stop running spi transfer
  206. * this also flushes both rx and tx fifos
  207. */
  208. spi_enable_chip(rs, false);
  209. /* make sure all interrupts are masked */
  210. writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
  211. if (atomic_read(&rs->state) & TXDMA)
  212. dmaengine_terminate_async(ctlr->dma_tx);
  213. if (atomic_read(&rs->state) & RXDMA)
  214. dmaengine_terminate_async(ctlr->dma_rx);
  215. }
  216. static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
  217. {
  218. u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
  219. u32 words = min(rs->tx_left, tx_free);
  220. rs->tx_left -= words;
  221. for (; words; words--) {
  222. u32 txw;
  223. if (rs->n_bytes == 1)
  224. txw = *(u8 *)rs->tx;
  225. else
  226. txw = *(u16 *)rs->tx;
  227. writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
  228. rs->tx += rs->n_bytes;
  229. }
  230. }
  231. static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
  232. {
  233. u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
  234. u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0;
  235. /* the hardware doesn't allow us to change fifo threshold
  236. * level while spi is enabled, so instead make sure to leave
  237. * enough words in the rx fifo to get the last interrupt
  238. * exactly when all words have been received
  239. */
  240. if (rx_left) {
  241. u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1;
  242. if (rx_left < ftl) {
  243. rx_left = ftl;
  244. words = rs->rx_left - rx_left;
  245. }
  246. }
  247. rs->rx_left = rx_left;
  248. for (; words; words--) {
  249. u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
  250. if (!rs->rx)
  251. continue;
  252. if (rs->n_bytes == 1)
  253. *(u8 *)rs->rx = (u8)rxw;
  254. else
  255. *(u16 *)rs->rx = (u16)rxw;
  256. rs->rx += rs->n_bytes;
  257. }
  258. }
  259. static irqreturn_t rockchip_spi_isr(int irq, void *dev_id)
  260. {
  261. struct spi_controller *ctlr = dev_id;
  262. struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
  263. if (rs->tx_left)
  264. rockchip_spi_pio_writer(rs);
  265. rockchip_spi_pio_reader(rs);
  266. if (!rs->rx_left) {
  267. spi_enable_chip(rs, false);
  268. writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
  269. spi_finalize_current_transfer(ctlr);
  270. }
  271. return IRQ_HANDLED;
  272. }
  273. static int rockchip_spi_prepare_irq(struct rockchip_spi *rs,
  274. struct spi_transfer *xfer)
  275. {
  276. rs->tx = xfer->tx_buf;
  277. rs->rx = xfer->rx_buf;
  278. rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
  279. rs->rx_left = xfer->len / rs->n_bytes;
  280. writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
  281. spi_enable_chip(rs, true);
  282. if (rs->tx_left)
  283. rockchip_spi_pio_writer(rs);
  284. /* 1 means the transfer is in progress */
  285. return 1;
  286. }
  287. static void rockchip_spi_dma_rxcb(void *data)
  288. {
  289. struct spi_controller *ctlr = data;
  290. struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
  291. int state = atomic_fetch_andnot(RXDMA, &rs->state);
  292. if (state & TXDMA && !rs->slave_abort)
  293. return;
  294. spi_enable_chip(rs, false);
  295. spi_finalize_current_transfer(ctlr);
  296. }
  297. static void rockchip_spi_dma_txcb(void *data)
  298. {
  299. struct spi_controller *ctlr = data;
  300. struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
  301. int state = atomic_fetch_andnot(TXDMA, &rs->state);
  302. if (state & RXDMA && !rs->slave_abort)
  303. return;
  304. /* Wait until the FIFO data completely. */
  305. wait_for_idle(rs);
  306. spi_enable_chip(rs, false);
  307. spi_finalize_current_transfer(ctlr);
  308. }
  309. static u32 rockchip_spi_calc_burst_size(u32 data_len)
  310. {
  311. u32 i;
  312. /* burst size: 1, 2, 4, 8 */
  313. for (i = 1; i < 8; i <<= 1) {
  314. if (data_len & i)
  315. break;
  316. }
  317. return i;
  318. }
  319. static int rockchip_spi_prepare_dma(struct rockchip_spi *rs,
  320. struct spi_controller *ctlr, struct spi_transfer *xfer)
  321. {
  322. struct dma_async_tx_descriptor *rxdesc, *txdesc;
  323. atomic_set(&rs->state, 0);
  324. rxdesc = NULL;
  325. if (xfer->rx_buf) {
  326. struct dma_slave_config rxconf = {
  327. .direction = DMA_DEV_TO_MEM,
  328. .src_addr = rs->dma_addr_rx,
  329. .src_addr_width = rs->n_bytes,
  330. .src_maxburst = rockchip_spi_calc_burst_size(xfer->len /
  331. rs->n_bytes),
  332. };
  333. dmaengine_slave_config(ctlr->dma_rx, &rxconf);
  334. rxdesc = dmaengine_prep_slave_sg(
  335. ctlr->dma_rx,
  336. xfer->rx_sg.sgl, xfer->rx_sg.nents,
  337. DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
  338. if (!rxdesc)
  339. return -EINVAL;
  340. rxdesc->callback = rockchip_spi_dma_rxcb;
  341. rxdesc->callback_param = ctlr;
  342. }
  343. txdesc = NULL;
  344. if (xfer->tx_buf) {
  345. struct dma_slave_config txconf = {
  346. .direction = DMA_MEM_TO_DEV,
  347. .dst_addr = rs->dma_addr_tx,
  348. .dst_addr_width = rs->n_bytes,
  349. .dst_maxburst = rs->fifo_len / 4,
  350. };
  351. dmaengine_slave_config(ctlr->dma_tx, &txconf);
  352. txdesc = dmaengine_prep_slave_sg(
  353. ctlr->dma_tx,
  354. xfer->tx_sg.sgl, xfer->tx_sg.nents,
  355. DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
  356. if (!txdesc) {
  357. if (rxdesc)
  358. dmaengine_terminate_sync(ctlr->dma_rx);
  359. return -EINVAL;
  360. }
  361. txdesc->callback = rockchip_spi_dma_txcb;
  362. txdesc->callback_param = ctlr;
  363. }
  364. /* rx must be started before tx due to spi instinct */
  365. if (rxdesc) {
  366. atomic_or(RXDMA, &rs->state);
  367. dmaengine_submit(rxdesc);
  368. dma_async_issue_pending(ctlr->dma_rx);
  369. }
  370. spi_enable_chip(rs, true);
  371. if (txdesc) {
  372. atomic_or(TXDMA, &rs->state);
  373. dmaengine_submit(txdesc);
  374. dma_async_issue_pending(ctlr->dma_tx);
  375. }
  376. /* 1 means the transfer is in progress */
  377. return 1;
  378. }
  379. static int rockchip_spi_config(struct rockchip_spi *rs,
  380. struct spi_device *spi, struct spi_transfer *xfer,
  381. bool use_dma, bool slave_mode)
  382. {
  383. u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET
  384. | CR0_BHT_8BIT << CR0_BHT_OFFSET
  385. | CR0_SSD_ONE << CR0_SSD_OFFSET
  386. | CR0_EM_BIG << CR0_EM_OFFSET;
  387. u32 cr1;
  388. u32 dmacr = 0;
  389. if (slave_mode)
  390. cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET;
  391. rs->slave_abort = false;
  392. cr0 |= rs->rsd << CR0_RSD_OFFSET;
  393. cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
  394. if (spi->mode & SPI_LSB_FIRST)
  395. cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
  396. if (xfer->rx_buf && xfer->tx_buf)
  397. cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
  398. else if (xfer->rx_buf)
  399. cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;
  400. else if (use_dma)
  401. cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
  402. switch (xfer->bits_per_word) {
  403. case 4:
  404. cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET;
  405. cr1 = xfer->len - 1;
  406. break;
  407. case 8:
  408. cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET;
  409. cr1 = xfer->len - 1;
  410. break;
  411. case 16:
  412. cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET;
  413. cr1 = xfer->len / 2 - 1;
  414. break;
  415. default:
  416. /* we only whitelist 4, 8 and 16 bit words in
  417. * ctlr->bits_per_word_mask, so this shouldn't
  418. * happen
  419. */
  420. dev_err(rs->dev, "unknown bits per word: %d\n",
  421. xfer->bits_per_word);
  422. return -EINVAL;
  423. }
  424. if (use_dma) {
  425. if (xfer->tx_buf)
  426. dmacr |= TF_DMA_EN;
  427. if (xfer->rx_buf)
  428. dmacr |= RF_DMA_EN;
  429. }
  430. writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
  431. writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1);
  432. /* unfortunately setting the fifo threshold level to generate an
  433. * interrupt exactly when the fifo is full doesn't seem to work,
  434. * so we need the strict inequality here
  435. */
  436. if (xfer->len < rs->fifo_len)
  437. writel_relaxed(xfer->len - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
  438. else
  439. writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
  440. writel_relaxed(rs->fifo_len / 2, rs->regs + ROCKCHIP_SPI_DMATDLR);
  441. writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1,
  442. rs->regs + ROCKCHIP_SPI_DMARDLR);
  443. writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
  444. /* the hardware only supports an even clock divisor, so
  445. * round divisor = spiclk / speed up to nearest even number
  446. * so that the resulting speed is <= the requested speed
  447. */
  448. writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz),
  449. rs->regs + ROCKCHIP_SPI_BAUDR);
  450. return 0;
  451. }
  452. static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
  453. {
  454. return ROCKCHIP_SPI_MAX_TRANLEN;
  455. }
  456. static int rockchip_spi_slave_abort(struct spi_controller *ctlr)
  457. {
  458. struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
  459. if (atomic_read(&rs->state) & RXDMA)
  460. dmaengine_terminate_sync(ctlr->dma_rx);
  461. if (atomic_read(&rs->state) & TXDMA)
  462. dmaengine_terminate_sync(ctlr->dma_tx);
  463. atomic_set(&rs->state, 0);
  464. spi_enable_chip(rs, false);
  465. rs->slave_abort = true;
  466. complete(&ctlr->xfer_completion);
  467. return 0;
  468. }
  469. static int rockchip_spi_transfer_one(
  470. struct spi_controller *ctlr,
  471. struct spi_device *spi,
  472. struct spi_transfer *xfer)
  473. {
  474. struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
  475. int ret;
  476. bool use_dma;
  477. /* Zero length transfers won't trigger an interrupt on completion */
  478. if (!xfer->len) {
  479. spi_finalize_current_transfer(ctlr);
  480. return 1;
  481. }
  482. WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
  483. (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
  484. if (!xfer->tx_buf && !xfer->rx_buf) {
  485. dev_err(rs->dev, "No buffer for transfer\n");
  486. return -EINVAL;
  487. }
  488. if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
  489. dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
  490. return -EINVAL;
  491. }
  492. rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
  493. use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
  494. ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave);
  495. if (ret)
  496. return ret;
  497. if (use_dma)
  498. return rockchip_spi_prepare_dma(rs, ctlr, xfer);
  499. return rockchip_spi_prepare_irq(rs, xfer);
  500. }
  501. static bool rockchip_spi_can_dma(struct spi_controller *ctlr,
  502. struct spi_device *spi,
  503. struct spi_transfer *xfer)
  504. {
  505. struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
  506. unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2;
  507. /* if the numbor of spi words to transfer is less than the fifo
  508. * length we can just fill the fifo and wait for a single irq,
  509. * so don't bother setting up dma
  510. */
  511. return xfer->len / bytes_per_word >= rs->fifo_len;
  512. }
  513. static int rockchip_spi_probe(struct platform_device *pdev)
  514. {
  515. int ret;
  516. struct rockchip_spi *rs;
  517. struct spi_controller *ctlr;
  518. struct resource *mem;
  519. struct device_node *np = pdev->dev.of_node;
  520. u32 rsd_nsecs, num_cs;
  521. bool slave_mode;
  522. slave_mode = of_property_read_bool(np, "spi-slave");
  523. if (slave_mode)
  524. ctlr = spi_alloc_slave(&pdev->dev,
  525. sizeof(struct rockchip_spi));
  526. else
  527. ctlr = spi_alloc_master(&pdev->dev,
  528. sizeof(struct rockchip_spi));
  529. if (!ctlr)
  530. return -ENOMEM;
  531. platform_set_drvdata(pdev, ctlr);
  532. rs = spi_controller_get_devdata(ctlr);
  533. ctlr->slave = slave_mode;
  534. /* Get basic io resource and map it */
  535. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  536. rs->regs = devm_ioremap_resource(&pdev->dev, mem);
  537. if (IS_ERR(rs->regs)) {
  538. ret = PTR_ERR(rs->regs);
  539. goto err_put_ctlr;
  540. }
  541. rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
  542. if (IS_ERR(rs->apb_pclk)) {
  543. dev_err(&pdev->dev, "Failed to get apb_pclk\n");
  544. ret = PTR_ERR(rs->apb_pclk);
  545. goto err_put_ctlr;
  546. }
  547. rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
  548. if (IS_ERR(rs->spiclk)) {
  549. dev_err(&pdev->dev, "Failed to get spi_pclk\n");
  550. ret = PTR_ERR(rs->spiclk);
  551. goto err_put_ctlr;
  552. }
  553. ret = clk_prepare_enable(rs->apb_pclk);
  554. if (ret < 0) {
  555. dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
  556. goto err_put_ctlr;
  557. }
  558. ret = clk_prepare_enable(rs->spiclk);
  559. if (ret < 0) {
  560. dev_err(&pdev->dev, "Failed to enable spi_clk\n");
  561. goto err_disable_apbclk;
  562. }
  563. spi_enable_chip(rs, false);
  564. ret = platform_get_irq(pdev, 0);
  565. if (ret < 0)
  566. goto err_disable_spiclk;
  567. ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
  568. IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
  569. if (ret)
  570. goto err_disable_spiclk;
  571. rs->dev = &pdev->dev;
  572. rs->freq = clk_get_rate(rs->spiclk);
  573. if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
  574. &rsd_nsecs)) {
  575. /* rx sample delay is expressed in parent clock cycles (max 3) */
  576. u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8),
  577. 1000000000 >> 8);
  578. if (!rsd) {
  579. dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n",
  580. rs->freq, rsd_nsecs);
  581. } else if (rsd > CR0_RSD_MAX) {
  582. rsd = CR0_RSD_MAX;
  583. dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n",
  584. rs->freq, rsd_nsecs,
  585. CR0_RSD_MAX * 1000000000U / rs->freq);
  586. }
  587. rs->rsd = rsd;
  588. }
  589. rs->fifo_len = get_fifo_len(rs);
  590. if (!rs->fifo_len) {
  591. dev_err(&pdev->dev, "Failed to get fifo length\n");
  592. ret = -EINVAL;
  593. goto err_disable_spiclk;
  594. }
  595. pm_runtime_set_active(&pdev->dev);
  596. pm_runtime_enable(&pdev->dev);
  597. ctlr->auto_runtime_pm = true;
  598. ctlr->bus_num = pdev->id;
  599. ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
  600. if (slave_mode) {
  601. ctlr->mode_bits |= SPI_NO_CS;
  602. ctlr->slave_abort = rockchip_spi_slave_abort;
  603. } else {
  604. ctlr->flags = SPI_MASTER_GPIO_SS;
  605. ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM;
  606. /*
  607. * rk spi0 has two native cs, spi1..5 one cs only
  608. * if num-cs is missing in the dts, default to 1
  609. */
  610. if (of_property_read_u32(np, "num-cs", &num_cs))
  611. num_cs = 1;
  612. ctlr->num_chipselect = num_cs;
  613. ctlr->use_gpio_descriptors = true;
  614. }
  615. ctlr->dev.of_node = pdev->dev.of_node;
  616. ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
  617. ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
  618. ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
  619. ctlr->set_cs = rockchip_spi_set_cs;
  620. ctlr->transfer_one = rockchip_spi_transfer_one;
  621. ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
  622. ctlr->handle_err = rockchip_spi_handle_err;
  623. ctlr->dma_tx = dma_request_chan(rs->dev, "tx");
  624. if (IS_ERR(ctlr->dma_tx)) {
  625. /* Check tx to see if we need defer probing driver */
  626. if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) {
  627. ret = -EPROBE_DEFER;
  628. goto err_disable_pm_runtime;
  629. }
  630. dev_warn(rs->dev, "Failed to request TX DMA channel\n");
  631. ctlr->dma_tx = NULL;
  632. }
  633. ctlr->dma_rx = dma_request_chan(rs->dev, "rx");
  634. if (IS_ERR(ctlr->dma_rx)) {
  635. if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) {
  636. ret = -EPROBE_DEFER;
  637. goto err_free_dma_tx;
  638. }
  639. dev_warn(rs->dev, "Failed to request RX DMA channel\n");
  640. ctlr->dma_rx = NULL;
  641. }
  642. if (ctlr->dma_tx && ctlr->dma_rx) {
  643. rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR;
  644. rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR;
  645. ctlr->can_dma = rockchip_spi_can_dma;
  646. }
  647. ret = devm_spi_register_controller(&pdev->dev, ctlr);
  648. if (ret < 0) {
  649. dev_err(&pdev->dev, "Failed to register controller\n");
  650. goto err_free_dma_rx;
  651. }
  652. return 0;
  653. err_free_dma_rx:
  654. if (ctlr->dma_rx)
  655. dma_release_channel(ctlr->dma_rx);
  656. err_free_dma_tx:
  657. if (ctlr->dma_tx)
  658. dma_release_channel(ctlr->dma_tx);
  659. err_disable_pm_runtime:
  660. pm_runtime_disable(&pdev->dev);
  661. err_disable_spiclk:
  662. clk_disable_unprepare(rs->spiclk);
  663. err_disable_apbclk:
  664. clk_disable_unprepare(rs->apb_pclk);
  665. err_put_ctlr:
  666. spi_controller_put(ctlr);
  667. return ret;
  668. }
  669. static int rockchip_spi_remove(struct platform_device *pdev)
  670. {
  671. struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev));
  672. struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
  673. pm_runtime_get_sync(&pdev->dev);
  674. clk_disable_unprepare(rs->spiclk);
  675. clk_disable_unprepare(rs->apb_pclk);
  676. pm_runtime_put_noidle(&pdev->dev);
  677. pm_runtime_disable(&pdev->dev);
  678. pm_runtime_set_suspended(&pdev->dev);
  679. if (ctlr->dma_tx)
  680. dma_release_channel(ctlr->dma_tx);
  681. if (ctlr->dma_rx)
  682. dma_release_channel(ctlr->dma_rx);
  683. spi_controller_put(ctlr);
  684. return 0;
  685. }
  686. #ifdef CONFIG_PM_SLEEP
  687. static int rockchip_spi_suspend(struct device *dev)
  688. {
  689. int ret;
  690. struct spi_controller *ctlr = dev_get_drvdata(dev);
  691. ret = spi_controller_suspend(ctlr);
  692. if (ret < 0)
  693. return ret;
  694. ret = pm_runtime_force_suspend(dev);
  695. if (ret < 0)
  696. return ret;
  697. pinctrl_pm_select_sleep_state(dev);
  698. return 0;
  699. }
  700. static int rockchip_spi_resume(struct device *dev)
  701. {
  702. int ret;
  703. struct spi_controller *ctlr = dev_get_drvdata(dev);
  704. struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
  705. pinctrl_pm_select_default_state(dev);
  706. ret = pm_runtime_force_resume(dev);
  707. if (ret < 0)
  708. return ret;
  709. ret = spi_controller_resume(ctlr);
  710. if (ret < 0) {
  711. clk_disable_unprepare(rs->spiclk);
  712. clk_disable_unprepare(rs->apb_pclk);
  713. }
  714. return 0;
  715. }
  716. #endif /* CONFIG_PM_SLEEP */
  717. #ifdef CONFIG_PM
  718. static int rockchip_spi_runtime_suspend(struct device *dev)
  719. {
  720. struct spi_controller *ctlr = dev_get_drvdata(dev);
  721. struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
  722. clk_disable_unprepare(rs->spiclk);
  723. clk_disable_unprepare(rs->apb_pclk);
  724. return 0;
  725. }
  726. static int rockchip_spi_runtime_resume(struct device *dev)
  727. {
  728. int ret;
  729. struct spi_controller *ctlr = dev_get_drvdata(dev);
  730. struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
  731. ret = clk_prepare_enable(rs->apb_pclk);
  732. if (ret < 0)
  733. return ret;
  734. ret = clk_prepare_enable(rs->spiclk);
  735. if (ret < 0)
  736. clk_disable_unprepare(rs->apb_pclk);
  737. return 0;
  738. }
  739. #endif /* CONFIG_PM */
  740. static const struct dev_pm_ops rockchip_spi_pm = {
  741. SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
  742. SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
  743. rockchip_spi_runtime_resume, NULL)
  744. };
  745. static const struct of_device_id rockchip_spi_dt_match[] = {
  746. { .compatible = "rockchip,px30-spi", },
  747. { .compatible = "rockchip,rk3036-spi", },
  748. { .compatible = "rockchip,rk3066-spi", },
  749. { .compatible = "rockchip,rk3188-spi", },
  750. { .compatible = "rockchip,rk3228-spi", },
  751. { .compatible = "rockchip,rk3288-spi", },
  752. { .compatible = "rockchip,rk3308-spi", },
  753. { .compatible = "rockchip,rk3328-spi", },
  754. { .compatible = "rockchip,rk3368-spi", },
  755. { .compatible = "rockchip,rk3399-spi", },
  756. { .compatible = "rockchip,rv1108-spi", },
  757. { },
  758. };
  759. MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
  760. static struct platform_driver rockchip_spi_driver = {
  761. .driver = {
  762. .name = DRIVER_NAME,
  763. .pm = &rockchip_spi_pm,
  764. .of_match_table = of_match_ptr(rockchip_spi_dt_match),
  765. },
  766. .probe = rockchip_spi_probe,
  767. .remove = rockchip_spi_remove,
  768. };
  769. module_platform_driver(rockchip_spi_driver);
  770. MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
  771. MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
  772. MODULE_LICENSE("GPL v2");