spi-qup.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2008-2014, The Linux foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/err.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/io.h>
  10. #include <linux/list.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/of_device.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/spi/spi.h>
  17. #include <linux/dmaengine.h>
  18. #include <linux/dma-mapping.h>
  19. #define QUP_CONFIG 0x0000
  20. #define QUP_STATE 0x0004
  21. #define QUP_IO_M_MODES 0x0008
  22. #define QUP_SW_RESET 0x000c
  23. #define QUP_OPERATIONAL 0x0018
  24. #define QUP_ERROR_FLAGS 0x001c
  25. #define QUP_ERROR_FLAGS_EN 0x0020
  26. #define QUP_OPERATIONAL_MASK 0x0028
  27. #define QUP_HW_VERSION 0x0030
  28. #define QUP_MX_OUTPUT_CNT 0x0100
  29. #define QUP_OUTPUT_FIFO 0x0110
  30. #define QUP_MX_WRITE_CNT 0x0150
  31. #define QUP_MX_INPUT_CNT 0x0200
  32. #define QUP_MX_READ_CNT 0x0208
  33. #define QUP_INPUT_FIFO 0x0218
  34. #define SPI_CONFIG 0x0300
  35. #define SPI_IO_CONTROL 0x0304
  36. #define SPI_ERROR_FLAGS 0x0308
  37. #define SPI_ERROR_FLAGS_EN 0x030c
  38. /* QUP_CONFIG fields */
  39. #define QUP_CONFIG_SPI_MODE (1 << 8)
  40. #define QUP_CONFIG_CLOCK_AUTO_GATE BIT(13)
  41. #define QUP_CONFIG_NO_INPUT BIT(7)
  42. #define QUP_CONFIG_NO_OUTPUT BIT(6)
  43. #define QUP_CONFIG_N 0x001f
  44. /* QUP_STATE fields */
  45. #define QUP_STATE_VALID BIT(2)
  46. #define QUP_STATE_RESET 0
  47. #define QUP_STATE_RUN 1
  48. #define QUP_STATE_PAUSE 3
  49. #define QUP_STATE_MASK 3
  50. #define QUP_STATE_CLEAR 2
  51. #define QUP_HW_VERSION_2_1_1 0x20010001
  52. /* QUP_IO_M_MODES fields */
  53. #define QUP_IO_M_PACK_EN BIT(15)
  54. #define QUP_IO_M_UNPACK_EN BIT(14)
  55. #define QUP_IO_M_INPUT_MODE_MASK_SHIFT 12
  56. #define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT 10
  57. #define QUP_IO_M_INPUT_MODE_MASK (3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT)
  58. #define QUP_IO_M_OUTPUT_MODE_MASK (3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT)
  59. #define QUP_IO_M_OUTPUT_BLOCK_SIZE(x) (((x) & (0x03 << 0)) >> 0)
  60. #define QUP_IO_M_OUTPUT_FIFO_SIZE(x) (((x) & (0x07 << 2)) >> 2)
  61. #define QUP_IO_M_INPUT_BLOCK_SIZE(x) (((x) & (0x03 << 5)) >> 5)
  62. #define QUP_IO_M_INPUT_FIFO_SIZE(x) (((x) & (0x07 << 7)) >> 7)
  63. #define QUP_IO_M_MODE_FIFO 0
  64. #define QUP_IO_M_MODE_BLOCK 1
  65. #define QUP_IO_M_MODE_DMOV 2
  66. #define QUP_IO_M_MODE_BAM 3
  67. /* QUP_OPERATIONAL fields */
  68. #define QUP_OP_IN_BLOCK_READ_REQ BIT(13)
  69. #define QUP_OP_OUT_BLOCK_WRITE_REQ BIT(12)
  70. #define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11)
  71. #define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10)
  72. #define QUP_OP_IN_SERVICE_FLAG BIT(9)
  73. #define QUP_OP_OUT_SERVICE_FLAG BIT(8)
  74. #define QUP_OP_IN_FIFO_FULL BIT(7)
  75. #define QUP_OP_OUT_FIFO_FULL BIT(6)
  76. #define QUP_OP_IN_FIFO_NOT_EMPTY BIT(5)
  77. #define QUP_OP_OUT_FIFO_NOT_EMPTY BIT(4)
  78. /* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */
  79. #define QUP_ERROR_OUTPUT_OVER_RUN BIT(5)
  80. #define QUP_ERROR_INPUT_UNDER_RUN BIT(4)
  81. #define QUP_ERROR_OUTPUT_UNDER_RUN BIT(3)
  82. #define QUP_ERROR_INPUT_OVER_RUN BIT(2)
  83. /* SPI_CONFIG fields */
  84. #define SPI_CONFIG_HS_MODE BIT(10)
  85. #define SPI_CONFIG_INPUT_FIRST BIT(9)
  86. #define SPI_CONFIG_LOOPBACK BIT(8)
  87. /* SPI_IO_CONTROL fields */
  88. #define SPI_IO_C_FORCE_CS BIT(11)
  89. #define SPI_IO_C_CLK_IDLE_HIGH BIT(10)
  90. #define SPI_IO_C_MX_CS_MODE BIT(8)
  91. #define SPI_IO_C_CS_N_POLARITY_0 BIT(4)
  92. #define SPI_IO_C_CS_SELECT(x) (((x) & 3) << 2)
  93. #define SPI_IO_C_CS_SELECT_MASK 0x000c
  94. #define SPI_IO_C_TRISTATE_CS BIT(1)
  95. #define SPI_IO_C_NO_TRI_STATE BIT(0)
  96. /* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */
  97. #define SPI_ERROR_CLK_OVER_RUN BIT(1)
  98. #define SPI_ERROR_CLK_UNDER_RUN BIT(0)
  99. #define SPI_NUM_CHIPSELECTS 4
  100. #define SPI_MAX_XFER (SZ_64K - 64)
  101. /* high speed mode is when bus rate is greater then 26MHz */
  102. #define SPI_HS_MIN_RATE 26000000
  103. #define SPI_MAX_RATE 50000000
  104. #define SPI_DELAY_THRESHOLD 1
  105. #define SPI_DELAY_RETRY 10
  106. struct spi_qup {
  107. void __iomem *base;
  108. struct device *dev;
  109. struct clk *cclk; /* core clock */
  110. struct clk *iclk; /* interface clock */
  111. int irq;
  112. spinlock_t lock;
  113. int in_fifo_sz;
  114. int out_fifo_sz;
  115. int in_blk_sz;
  116. int out_blk_sz;
  117. struct spi_transfer *xfer;
  118. struct completion done;
  119. int error;
  120. int w_size; /* bytes per SPI word */
  121. int n_words;
  122. int tx_bytes;
  123. int rx_bytes;
  124. const u8 *tx_buf;
  125. u8 *rx_buf;
  126. int qup_v1;
  127. int mode;
  128. struct dma_slave_config rx_conf;
  129. struct dma_slave_config tx_conf;
  130. };
  131. static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer);
  132. static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag)
  133. {
  134. u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL);
  135. return (opflag & flag) != 0;
  136. }
  137. static inline bool spi_qup_is_dma_xfer(int mode)
  138. {
  139. if (mode == QUP_IO_M_MODE_DMOV || mode == QUP_IO_M_MODE_BAM)
  140. return true;
  141. return false;
  142. }
  143. /* get's the transaction size length */
  144. static inline unsigned int spi_qup_len(struct spi_qup *controller)
  145. {
  146. return controller->n_words * controller->w_size;
  147. }
  148. static inline bool spi_qup_is_valid_state(struct spi_qup *controller)
  149. {
  150. u32 opstate = readl_relaxed(controller->base + QUP_STATE);
  151. return opstate & QUP_STATE_VALID;
  152. }
  153. static int spi_qup_set_state(struct spi_qup *controller, u32 state)
  154. {
  155. unsigned long loop;
  156. u32 cur_state;
  157. loop = 0;
  158. while (!spi_qup_is_valid_state(controller)) {
  159. usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2);
  160. if (++loop > SPI_DELAY_RETRY)
  161. return -EIO;
  162. }
  163. if (loop)
  164. dev_dbg(controller->dev, "invalid state for %ld,us %d\n",
  165. loop, state);
  166. cur_state = readl_relaxed(controller->base + QUP_STATE);
  167. /*
  168. * Per spec: for PAUSE_STATE to RESET_STATE, two writes
  169. * of (b10) are required
  170. */
  171. if (((cur_state & QUP_STATE_MASK) == QUP_STATE_PAUSE) &&
  172. (state == QUP_STATE_RESET)) {
  173. writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
  174. writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
  175. } else {
  176. cur_state &= ~QUP_STATE_MASK;
  177. cur_state |= state;
  178. writel_relaxed(cur_state, controller->base + QUP_STATE);
  179. }
  180. loop = 0;
  181. while (!spi_qup_is_valid_state(controller)) {
  182. usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2);
  183. if (++loop > SPI_DELAY_RETRY)
  184. return -EIO;
  185. }
  186. return 0;
  187. }
  188. static void spi_qup_read_from_fifo(struct spi_qup *controller, u32 num_words)
  189. {
  190. u8 *rx_buf = controller->rx_buf;
  191. int i, shift, num_bytes;
  192. u32 word;
  193. for (; num_words; num_words--) {
  194. word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
  195. num_bytes = min_t(int, spi_qup_len(controller) -
  196. controller->rx_bytes,
  197. controller->w_size);
  198. if (!rx_buf) {
  199. controller->rx_bytes += num_bytes;
  200. continue;
  201. }
  202. for (i = 0; i < num_bytes; i++, controller->rx_bytes++) {
  203. /*
  204. * The data format depends on bytes per SPI word:
  205. * 4 bytes: 0x12345678
  206. * 2 bytes: 0x00001234
  207. * 1 byte : 0x00000012
  208. */
  209. shift = BITS_PER_BYTE;
  210. shift *= (controller->w_size - i - 1);
  211. rx_buf[controller->rx_bytes] = word >> shift;
  212. }
  213. }
  214. }
  215. static void spi_qup_read(struct spi_qup *controller, u32 *opflags)
  216. {
  217. u32 remainder, words_per_block, num_words;
  218. bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
  219. remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->rx_bytes,
  220. controller->w_size);
  221. words_per_block = controller->in_blk_sz >> 2;
  222. do {
  223. /* ACK by clearing service flag */
  224. writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
  225. controller->base + QUP_OPERATIONAL);
  226. if (!remainder)
  227. goto exit;
  228. if (is_block_mode) {
  229. num_words = (remainder > words_per_block) ?
  230. words_per_block : remainder;
  231. } else {
  232. if (!spi_qup_is_flag_set(controller,
  233. QUP_OP_IN_FIFO_NOT_EMPTY))
  234. break;
  235. num_words = 1;
  236. }
  237. /* read up to the maximum transfer size available */
  238. spi_qup_read_from_fifo(controller, num_words);
  239. remainder -= num_words;
  240. /* if block mode, check to see if next block is available */
  241. if (is_block_mode && !spi_qup_is_flag_set(controller,
  242. QUP_OP_IN_BLOCK_READ_REQ))
  243. break;
  244. } while (remainder);
  245. /*
  246. * Due to extra stickiness of the QUP_OP_IN_SERVICE_FLAG during block
  247. * reads, it has to be cleared again at the very end. However, be sure
  248. * to refresh opflags value because MAX_INPUT_DONE_FLAG may now be
  249. * present and this is used to determine if transaction is complete
  250. */
  251. exit:
  252. if (!remainder) {
  253. *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
  254. if (is_block_mode && *opflags & QUP_OP_MAX_INPUT_DONE_FLAG)
  255. writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
  256. controller->base + QUP_OPERATIONAL);
  257. }
  258. }
  259. static void spi_qup_write_to_fifo(struct spi_qup *controller, u32 num_words)
  260. {
  261. const u8 *tx_buf = controller->tx_buf;
  262. int i, num_bytes;
  263. u32 word, data;
  264. for (; num_words; num_words--) {
  265. word = 0;
  266. num_bytes = min_t(int, spi_qup_len(controller) -
  267. controller->tx_bytes,
  268. controller->w_size);
  269. if (tx_buf)
  270. for (i = 0; i < num_bytes; i++) {
  271. data = tx_buf[controller->tx_bytes + i];
  272. word |= data << (BITS_PER_BYTE * (3 - i));
  273. }
  274. controller->tx_bytes += num_bytes;
  275. writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
  276. }
  277. }
  278. static void spi_qup_dma_done(void *data)
  279. {
  280. struct spi_qup *qup = data;
  281. complete(&qup->done);
  282. }
  283. static void spi_qup_write(struct spi_qup *controller)
  284. {
  285. bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
  286. u32 remainder, words_per_block, num_words;
  287. remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->tx_bytes,
  288. controller->w_size);
  289. words_per_block = controller->out_blk_sz >> 2;
  290. do {
  291. /* ACK by clearing service flag */
  292. writel_relaxed(QUP_OP_OUT_SERVICE_FLAG,
  293. controller->base + QUP_OPERATIONAL);
  294. /* make sure the interrupt is valid */
  295. if (!remainder)
  296. return;
  297. if (is_block_mode) {
  298. num_words = (remainder > words_per_block) ?
  299. words_per_block : remainder;
  300. } else {
  301. if (spi_qup_is_flag_set(controller,
  302. QUP_OP_OUT_FIFO_FULL))
  303. break;
  304. num_words = 1;
  305. }
  306. spi_qup_write_to_fifo(controller, num_words);
  307. remainder -= num_words;
  308. /* if block mode, check to see if next block is available */
  309. if (is_block_mode && !spi_qup_is_flag_set(controller,
  310. QUP_OP_OUT_BLOCK_WRITE_REQ))
  311. break;
  312. } while (remainder);
  313. }
  314. static int spi_qup_prep_sg(struct spi_master *master, struct scatterlist *sgl,
  315. unsigned int nents, enum dma_transfer_direction dir,
  316. dma_async_tx_callback callback)
  317. {
  318. struct spi_qup *qup = spi_master_get_devdata(master);
  319. unsigned long flags = DMA_PREP_INTERRUPT | DMA_PREP_FENCE;
  320. struct dma_async_tx_descriptor *desc;
  321. struct dma_chan *chan;
  322. dma_cookie_t cookie;
  323. if (dir == DMA_MEM_TO_DEV)
  324. chan = master->dma_tx;
  325. else
  326. chan = master->dma_rx;
  327. desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
  328. if (IS_ERR_OR_NULL(desc))
  329. return desc ? PTR_ERR(desc) : -EINVAL;
  330. desc->callback = callback;
  331. desc->callback_param = qup;
  332. cookie = dmaengine_submit(desc);
  333. return dma_submit_error(cookie);
  334. }
  335. static void spi_qup_dma_terminate(struct spi_master *master,
  336. struct spi_transfer *xfer)
  337. {
  338. if (xfer->tx_buf)
  339. dmaengine_terminate_all(master->dma_tx);
  340. if (xfer->rx_buf)
  341. dmaengine_terminate_all(master->dma_rx);
  342. }
  343. static u32 spi_qup_sgl_get_nents_len(struct scatterlist *sgl, u32 max,
  344. u32 *nents)
  345. {
  346. struct scatterlist *sg;
  347. u32 total = 0;
  348. for (sg = sgl; sg; sg = sg_next(sg)) {
  349. unsigned int len = sg_dma_len(sg);
  350. /* check for overflow as well as limit */
  351. if (((total + len) < total) || ((total + len) > max))
  352. break;
  353. total += len;
  354. (*nents)++;
  355. }
  356. return total;
  357. }
  358. static int spi_qup_do_dma(struct spi_device *spi, struct spi_transfer *xfer,
  359. unsigned long timeout)
  360. {
  361. dma_async_tx_callback rx_done = NULL, tx_done = NULL;
  362. struct spi_master *master = spi->master;
  363. struct spi_qup *qup = spi_master_get_devdata(master);
  364. struct scatterlist *tx_sgl, *rx_sgl;
  365. int ret;
  366. if (xfer->rx_buf)
  367. rx_done = spi_qup_dma_done;
  368. else if (xfer->tx_buf)
  369. tx_done = spi_qup_dma_done;
  370. rx_sgl = xfer->rx_sg.sgl;
  371. tx_sgl = xfer->tx_sg.sgl;
  372. do {
  373. u32 rx_nents = 0, tx_nents = 0;
  374. if (rx_sgl)
  375. qup->n_words = spi_qup_sgl_get_nents_len(rx_sgl,
  376. SPI_MAX_XFER, &rx_nents) / qup->w_size;
  377. if (tx_sgl)
  378. qup->n_words = spi_qup_sgl_get_nents_len(tx_sgl,
  379. SPI_MAX_XFER, &tx_nents) / qup->w_size;
  380. if (!qup->n_words)
  381. return -EIO;
  382. ret = spi_qup_io_config(spi, xfer);
  383. if (ret)
  384. return ret;
  385. /* before issuing the descriptors, set the QUP to run */
  386. ret = spi_qup_set_state(qup, QUP_STATE_RUN);
  387. if (ret) {
  388. dev_warn(qup->dev, "cannot set RUN state\n");
  389. return ret;
  390. }
  391. if (rx_sgl) {
  392. ret = spi_qup_prep_sg(master, rx_sgl, rx_nents,
  393. DMA_DEV_TO_MEM, rx_done);
  394. if (ret)
  395. return ret;
  396. dma_async_issue_pending(master->dma_rx);
  397. }
  398. if (tx_sgl) {
  399. ret = spi_qup_prep_sg(master, tx_sgl, tx_nents,
  400. DMA_MEM_TO_DEV, tx_done);
  401. if (ret)
  402. return ret;
  403. dma_async_issue_pending(master->dma_tx);
  404. }
  405. if (!wait_for_completion_timeout(&qup->done, timeout))
  406. return -ETIMEDOUT;
  407. for (; rx_sgl && rx_nents--; rx_sgl = sg_next(rx_sgl))
  408. ;
  409. for (; tx_sgl && tx_nents--; tx_sgl = sg_next(tx_sgl))
  410. ;
  411. } while (rx_sgl || tx_sgl);
  412. return 0;
  413. }
  414. static int spi_qup_do_pio(struct spi_device *spi, struct spi_transfer *xfer,
  415. unsigned long timeout)
  416. {
  417. struct spi_master *master = spi->master;
  418. struct spi_qup *qup = spi_master_get_devdata(master);
  419. int ret, n_words, iterations, offset = 0;
  420. n_words = qup->n_words;
  421. iterations = n_words / SPI_MAX_XFER; /* round down */
  422. qup->rx_buf = xfer->rx_buf;
  423. qup->tx_buf = xfer->tx_buf;
  424. do {
  425. if (iterations)
  426. qup->n_words = SPI_MAX_XFER;
  427. else
  428. qup->n_words = n_words % SPI_MAX_XFER;
  429. if (qup->tx_buf && offset)
  430. qup->tx_buf = xfer->tx_buf + offset * SPI_MAX_XFER;
  431. if (qup->rx_buf && offset)
  432. qup->rx_buf = xfer->rx_buf + offset * SPI_MAX_XFER;
  433. /*
  434. * if the transaction is small enough, we need
  435. * to fallback to FIFO mode
  436. */
  437. if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32)))
  438. qup->mode = QUP_IO_M_MODE_FIFO;
  439. ret = spi_qup_io_config(spi, xfer);
  440. if (ret)
  441. return ret;
  442. ret = spi_qup_set_state(qup, QUP_STATE_RUN);
  443. if (ret) {
  444. dev_warn(qup->dev, "cannot set RUN state\n");
  445. return ret;
  446. }
  447. ret = spi_qup_set_state(qup, QUP_STATE_PAUSE);
  448. if (ret) {
  449. dev_warn(qup->dev, "cannot set PAUSE state\n");
  450. return ret;
  451. }
  452. if (qup->mode == QUP_IO_M_MODE_FIFO)
  453. spi_qup_write(qup);
  454. ret = spi_qup_set_state(qup, QUP_STATE_RUN);
  455. if (ret) {
  456. dev_warn(qup->dev, "cannot set RUN state\n");
  457. return ret;
  458. }
  459. if (!wait_for_completion_timeout(&qup->done, timeout))
  460. return -ETIMEDOUT;
  461. offset++;
  462. } while (iterations--);
  463. return 0;
  464. }
  465. static bool spi_qup_data_pending(struct spi_qup *controller)
  466. {
  467. unsigned int remainder_tx, remainder_rx;
  468. remainder_tx = DIV_ROUND_UP(spi_qup_len(controller) -
  469. controller->tx_bytes, controller->w_size);
  470. remainder_rx = DIV_ROUND_UP(spi_qup_len(controller) -
  471. controller->rx_bytes, controller->w_size);
  472. return remainder_tx || remainder_rx;
  473. }
  474. static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
  475. {
  476. struct spi_qup *controller = dev_id;
  477. u32 opflags, qup_err, spi_err;
  478. unsigned long flags;
  479. int error = 0;
  480. qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
  481. spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
  482. opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
  483. writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
  484. writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
  485. if (qup_err) {
  486. if (qup_err & QUP_ERROR_OUTPUT_OVER_RUN)
  487. dev_warn(controller->dev, "OUTPUT_OVER_RUN\n");
  488. if (qup_err & QUP_ERROR_INPUT_UNDER_RUN)
  489. dev_warn(controller->dev, "INPUT_UNDER_RUN\n");
  490. if (qup_err & QUP_ERROR_OUTPUT_UNDER_RUN)
  491. dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n");
  492. if (qup_err & QUP_ERROR_INPUT_OVER_RUN)
  493. dev_warn(controller->dev, "INPUT_OVER_RUN\n");
  494. error = -EIO;
  495. }
  496. if (spi_err) {
  497. if (spi_err & SPI_ERROR_CLK_OVER_RUN)
  498. dev_warn(controller->dev, "CLK_OVER_RUN\n");
  499. if (spi_err & SPI_ERROR_CLK_UNDER_RUN)
  500. dev_warn(controller->dev, "CLK_UNDER_RUN\n");
  501. error = -EIO;
  502. }
  503. spin_lock_irqsave(&controller->lock, flags);
  504. if (!controller->error)
  505. controller->error = error;
  506. spin_unlock_irqrestore(&controller->lock, flags);
  507. if (spi_qup_is_dma_xfer(controller->mode)) {
  508. writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
  509. } else {
  510. if (opflags & QUP_OP_IN_SERVICE_FLAG)
  511. spi_qup_read(controller, &opflags);
  512. if (opflags & QUP_OP_OUT_SERVICE_FLAG)
  513. spi_qup_write(controller);
  514. if (!spi_qup_data_pending(controller))
  515. complete(&controller->done);
  516. }
  517. if (error)
  518. complete(&controller->done);
  519. if (opflags & QUP_OP_MAX_INPUT_DONE_FLAG) {
  520. if (!spi_qup_is_dma_xfer(controller->mode)) {
  521. if (spi_qup_data_pending(controller))
  522. return IRQ_HANDLED;
  523. }
  524. complete(&controller->done);
  525. }
  526. return IRQ_HANDLED;
  527. }
  528. /* set clock freq ... bits per word, determine mode */
  529. static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer)
  530. {
  531. struct spi_qup *controller = spi_master_get_devdata(spi->master);
  532. int ret;
  533. if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
  534. dev_err(controller->dev, "too big size for loopback %d > %d\n",
  535. xfer->len, controller->in_fifo_sz);
  536. return -EIO;
  537. }
  538. ret = clk_set_rate(controller->cclk, xfer->speed_hz);
  539. if (ret) {
  540. dev_err(controller->dev, "fail to set frequency %d",
  541. xfer->speed_hz);
  542. return -EIO;
  543. }
  544. controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8);
  545. controller->n_words = xfer->len / controller->w_size;
  546. if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32)))
  547. controller->mode = QUP_IO_M_MODE_FIFO;
  548. else if (spi->master->can_dma &&
  549. spi->master->can_dma(spi->master, spi, xfer) &&
  550. spi->master->cur_msg_mapped)
  551. controller->mode = QUP_IO_M_MODE_BAM;
  552. else
  553. controller->mode = QUP_IO_M_MODE_BLOCK;
  554. return 0;
  555. }
  556. /* prep qup for another spi transaction of specific type */
  557. static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
  558. {
  559. struct spi_qup *controller = spi_master_get_devdata(spi->master);
  560. u32 config, iomode, control;
  561. unsigned long flags;
  562. spin_lock_irqsave(&controller->lock, flags);
  563. controller->xfer = xfer;
  564. controller->error = 0;
  565. controller->rx_bytes = 0;
  566. controller->tx_bytes = 0;
  567. spin_unlock_irqrestore(&controller->lock, flags);
  568. if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
  569. dev_err(controller->dev, "cannot set RESET state\n");
  570. return -EIO;
  571. }
  572. switch (controller->mode) {
  573. case QUP_IO_M_MODE_FIFO:
  574. writel_relaxed(controller->n_words,
  575. controller->base + QUP_MX_READ_CNT);
  576. writel_relaxed(controller->n_words,
  577. controller->base + QUP_MX_WRITE_CNT);
  578. /* must be zero for FIFO */
  579. writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
  580. writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
  581. break;
  582. case QUP_IO_M_MODE_BAM:
  583. writel_relaxed(controller->n_words,
  584. controller->base + QUP_MX_INPUT_CNT);
  585. writel_relaxed(controller->n_words,
  586. controller->base + QUP_MX_OUTPUT_CNT);
  587. /* must be zero for BLOCK and BAM */
  588. writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
  589. writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
  590. if (!controller->qup_v1) {
  591. void __iomem *input_cnt;
  592. input_cnt = controller->base + QUP_MX_INPUT_CNT;
  593. /*
  594. * for DMA transfers, both QUP_MX_INPUT_CNT and
  595. * QUP_MX_OUTPUT_CNT must be zero to all cases but one.
  596. * That case is a non-balanced transfer when there is
  597. * only a rx_buf.
  598. */
  599. if (xfer->tx_buf)
  600. writel_relaxed(0, input_cnt);
  601. else
  602. writel_relaxed(controller->n_words, input_cnt);
  603. writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
  604. }
  605. break;
  606. case QUP_IO_M_MODE_BLOCK:
  607. reinit_completion(&controller->done);
  608. writel_relaxed(controller->n_words,
  609. controller->base + QUP_MX_INPUT_CNT);
  610. writel_relaxed(controller->n_words,
  611. controller->base + QUP_MX_OUTPUT_CNT);
  612. /* must be zero for BLOCK and BAM */
  613. writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
  614. writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
  615. break;
  616. default:
  617. dev_err(controller->dev, "unknown mode = %d\n",
  618. controller->mode);
  619. return -EIO;
  620. }
  621. iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
  622. /* Set input and output transfer mode */
  623. iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
  624. if (!spi_qup_is_dma_xfer(controller->mode))
  625. iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
  626. else
  627. iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN;
  628. iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
  629. iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
  630. writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
  631. control = readl_relaxed(controller->base + SPI_IO_CONTROL);
  632. if (spi->mode & SPI_CPOL)
  633. control |= SPI_IO_C_CLK_IDLE_HIGH;
  634. else
  635. control &= ~SPI_IO_C_CLK_IDLE_HIGH;
  636. writel_relaxed(control, controller->base + SPI_IO_CONTROL);
  637. config = readl_relaxed(controller->base + SPI_CONFIG);
  638. if (spi->mode & SPI_LOOP)
  639. config |= SPI_CONFIG_LOOPBACK;
  640. else
  641. config &= ~SPI_CONFIG_LOOPBACK;
  642. if (spi->mode & SPI_CPHA)
  643. config &= ~SPI_CONFIG_INPUT_FIRST;
  644. else
  645. config |= SPI_CONFIG_INPUT_FIRST;
  646. /*
  647. * HS_MODE improves signal stability for spi-clk high rates,
  648. * but is invalid in loop back mode.
  649. */
  650. if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP))
  651. config |= SPI_CONFIG_HS_MODE;
  652. else
  653. config &= ~SPI_CONFIG_HS_MODE;
  654. writel_relaxed(config, controller->base + SPI_CONFIG);
  655. config = readl_relaxed(controller->base + QUP_CONFIG);
  656. config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
  657. config |= xfer->bits_per_word - 1;
  658. config |= QUP_CONFIG_SPI_MODE;
  659. if (spi_qup_is_dma_xfer(controller->mode)) {
  660. if (!xfer->tx_buf)
  661. config |= QUP_CONFIG_NO_OUTPUT;
  662. if (!xfer->rx_buf)
  663. config |= QUP_CONFIG_NO_INPUT;
  664. }
  665. writel_relaxed(config, controller->base + QUP_CONFIG);
  666. /* only write to OPERATIONAL_MASK when register is present */
  667. if (!controller->qup_v1) {
  668. u32 mask = 0;
  669. /*
  670. * mask INPUT and OUTPUT service flags to prevent IRQs on FIFO
  671. * status change in BAM mode
  672. */
  673. if (spi_qup_is_dma_xfer(controller->mode))
  674. mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG;
  675. writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
  676. }
  677. return 0;
  678. }
  679. static int spi_qup_transfer_one(struct spi_master *master,
  680. struct spi_device *spi,
  681. struct spi_transfer *xfer)
  682. {
  683. struct spi_qup *controller = spi_master_get_devdata(master);
  684. unsigned long timeout, flags;
  685. int ret;
  686. ret = spi_qup_io_prep(spi, xfer);
  687. if (ret)
  688. return ret;
  689. timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC);
  690. timeout = DIV_ROUND_UP(min_t(unsigned long, SPI_MAX_XFER,
  691. xfer->len) * 8, timeout);
  692. timeout = 100 * msecs_to_jiffies(timeout);
  693. reinit_completion(&controller->done);
  694. spin_lock_irqsave(&controller->lock, flags);
  695. controller->xfer = xfer;
  696. controller->error = 0;
  697. controller->rx_bytes = 0;
  698. controller->tx_bytes = 0;
  699. spin_unlock_irqrestore(&controller->lock, flags);
  700. if (spi_qup_is_dma_xfer(controller->mode))
  701. ret = spi_qup_do_dma(spi, xfer, timeout);
  702. else
  703. ret = spi_qup_do_pio(spi, xfer, timeout);
  704. spi_qup_set_state(controller, QUP_STATE_RESET);
  705. spin_lock_irqsave(&controller->lock, flags);
  706. if (!ret)
  707. ret = controller->error;
  708. spin_unlock_irqrestore(&controller->lock, flags);
  709. if (ret && spi_qup_is_dma_xfer(controller->mode))
  710. spi_qup_dma_terminate(master, xfer);
  711. return ret;
  712. }
  713. static bool spi_qup_can_dma(struct spi_master *master, struct spi_device *spi,
  714. struct spi_transfer *xfer)
  715. {
  716. struct spi_qup *qup = spi_master_get_devdata(master);
  717. size_t dma_align = dma_get_cache_alignment();
  718. int n_words;
  719. if (xfer->rx_buf) {
  720. if (!IS_ALIGNED((size_t)xfer->rx_buf, dma_align) ||
  721. IS_ERR_OR_NULL(master->dma_rx))
  722. return false;
  723. if (qup->qup_v1 && (xfer->len % qup->in_blk_sz))
  724. return false;
  725. }
  726. if (xfer->tx_buf) {
  727. if (!IS_ALIGNED((size_t)xfer->tx_buf, dma_align) ||
  728. IS_ERR_OR_NULL(master->dma_tx))
  729. return false;
  730. if (qup->qup_v1 && (xfer->len % qup->out_blk_sz))
  731. return false;
  732. }
  733. n_words = xfer->len / DIV_ROUND_UP(xfer->bits_per_word, 8);
  734. if (n_words <= (qup->in_fifo_sz / sizeof(u32)))
  735. return false;
  736. return true;
  737. }
  738. static void spi_qup_release_dma(struct spi_master *master)
  739. {
  740. if (!IS_ERR_OR_NULL(master->dma_rx))
  741. dma_release_channel(master->dma_rx);
  742. if (!IS_ERR_OR_NULL(master->dma_tx))
  743. dma_release_channel(master->dma_tx);
  744. }
  745. static int spi_qup_init_dma(struct spi_master *master, resource_size_t base)
  746. {
  747. struct spi_qup *spi = spi_master_get_devdata(master);
  748. struct dma_slave_config *rx_conf = &spi->rx_conf,
  749. *tx_conf = &spi->tx_conf;
  750. struct device *dev = spi->dev;
  751. int ret;
  752. /* allocate dma resources, if available */
  753. master->dma_rx = dma_request_chan(dev, "rx");
  754. if (IS_ERR(master->dma_rx))
  755. return PTR_ERR(master->dma_rx);
  756. master->dma_tx = dma_request_chan(dev, "tx");
  757. if (IS_ERR(master->dma_tx)) {
  758. ret = PTR_ERR(master->dma_tx);
  759. goto err_tx;
  760. }
  761. /* set DMA parameters */
  762. rx_conf->direction = DMA_DEV_TO_MEM;
  763. rx_conf->device_fc = 1;
  764. rx_conf->src_addr = base + QUP_INPUT_FIFO;
  765. rx_conf->src_maxburst = spi->in_blk_sz;
  766. tx_conf->direction = DMA_MEM_TO_DEV;
  767. tx_conf->device_fc = 1;
  768. tx_conf->dst_addr = base + QUP_OUTPUT_FIFO;
  769. tx_conf->dst_maxburst = spi->out_blk_sz;
  770. ret = dmaengine_slave_config(master->dma_rx, rx_conf);
  771. if (ret) {
  772. dev_err(dev, "failed to configure RX channel\n");
  773. goto err;
  774. }
  775. ret = dmaengine_slave_config(master->dma_tx, tx_conf);
  776. if (ret) {
  777. dev_err(dev, "failed to configure TX channel\n");
  778. goto err;
  779. }
  780. return 0;
  781. err:
  782. dma_release_channel(master->dma_tx);
  783. err_tx:
  784. dma_release_channel(master->dma_rx);
  785. return ret;
  786. }
  787. static void spi_qup_set_cs(struct spi_device *spi, bool val)
  788. {
  789. struct spi_qup *controller;
  790. u32 spi_ioc;
  791. u32 spi_ioc_orig;
  792. controller = spi_master_get_devdata(spi->master);
  793. spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL);
  794. spi_ioc_orig = spi_ioc;
  795. if (!val)
  796. spi_ioc |= SPI_IO_C_FORCE_CS;
  797. else
  798. spi_ioc &= ~SPI_IO_C_FORCE_CS;
  799. if (spi_ioc != spi_ioc_orig)
  800. writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL);
  801. }
  802. static int spi_qup_probe(struct platform_device *pdev)
  803. {
  804. struct spi_master *master;
  805. struct clk *iclk, *cclk;
  806. struct spi_qup *controller;
  807. struct resource *res;
  808. struct device *dev;
  809. void __iomem *base;
  810. u32 max_freq, iomode, num_cs;
  811. int ret, irq, size;
  812. dev = &pdev->dev;
  813. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  814. base = devm_ioremap_resource(dev, res);
  815. if (IS_ERR(base))
  816. return PTR_ERR(base);
  817. irq = platform_get_irq(pdev, 0);
  818. if (irq < 0)
  819. return irq;
  820. cclk = devm_clk_get(dev, "core");
  821. if (IS_ERR(cclk))
  822. return PTR_ERR(cclk);
  823. iclk = devm_clk_get(dev, "iface");
  824. if (IS_ERR(iclk))
  825. return PTR_ERR(iclk);
  826. /* This is optional parameter */
  827. if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq))
  828. max_freq = SPI_MAX_RATE;
  829. if (!max_freq || max_freq > SPI_MAX_RATE) {
  830. dev_err(dev, "invalid clock frequency %d\n", max_freq);
  831. return -ENXIO;
  832. }
  833. ret = clk_prepare_enable(cclk);
  834. if (ret) {
  835. dev_err(dev, "cannot enable core clock\n");
  836. return ret;
  837. }
  838. ret = clk_prepare_enable(iclk);
  839. if (ret) {
  840. clk_disable_unprepare(cclk);
  841. dev_err(dev, "cannot enable iface clock\n");
  842. return ret;
  843. }
  844. master = spi_alloc_master(dev, sizeof(struct spi_qup));
  845. if (!master) {
  846. clk_disable_unprepare(cclk);
  847. clk_disable_unprepare(iclk);
  848. dev_err(dev, "cannot allocate master\n");
  849. return -ENOMEM;
  850. }
  851. /* use num-cs unless not present or out of range */
  852. if (of_property_read_u32(dev->of_node, "num-cs", &num_cs) ||
  853. num_cs > SPI_NUM_CHIPSELECTS)
  854. master->num_chipselect = SPI_NUM_CHIPSELECTS;
  855. else
  856. master->num_chipselect = num_cs;
  857. master->bus_num = pdev->id;
  858. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
  859. master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
  860. master->max_speed_hz = max_freq;
  861. master->transfer_one = spi_qup_transfer_one;
  862. master->dev.of_node = pdev->dev.of_node;
  863. master->auto_runtime_pm = true;
  864. master->dma_alignment = dma_get_cache_alignment();
  865. master->max_dma_len = SPI_MAX_XFER;
  866. platform_set_drvdata(pdev, master);
  867. controller = spi_master_get_devdata(master);
  868. controller->dev = dev;
  869. controller->base = base;
  870. controller->iclk = iclk;
  871. controller->cclk = cclk;
  872. controller->irq = irq;
  873. ret = spi_qup_init_dma(master, res->start);
  874. if (ret == -EPROBE_DEFER)
  875. goto error;
  876. else if (!ret)
  877. master->can_dma = spi_qup_can_dma;
  878. controller->qup_v1 = (uintptr_t)of_device_get_match_data(dev);
  879. if (!controller->qup_v1)
  880. master->set_cs = spi_qup_set_cs;
  881. spin_lock_init(&controller->lock);
  882. init_completion(&controller->done);
  883. iomode = readl_relaxed(base + QUP_IO_M_MODES);
  884. size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode);
  885. if (size)
  886. controller->out_blk_sz = size * 16;
  887. else
  888. controller->out_blk_sz = 4;
  889. size = QUP_IO_M_INPUT_BLOCK_SIZE(iomode);
  890. if (size)
  891. controller->in_blk_sz = size * 16;
  892. else
  893. controller->in_blk_sz = 4;
  894. size = QUP_IO_M_OUTPUT_FIFO_SIZE(iomode);
  895. controller->out_fifo_sz = controller->out_blk_sz * (2 << size);
  896. size = QUP_IO_M_INPUT_FIFO_SIZE(iomode);
  897. controller->in_fifo_sz = controller->in_blk_sz * (2 << size);
  898. dev_info(dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
  899. controller->in_blk_sz, controller->in_fifo_sz,
  900. controller->out_blk_sz, controller->out_fifo_sz);
  901. writel_relaxed(1, base + QUP_SW_RESET);
  902. ret = spi_qup_set_state(controller, QUP_STATE_RESET);
  903. if (ret) {
  904. dev_err(dev, "cannot set RESET state\n");
  905. goto error_dma;
  906. }
  907. writel_relaxed(0, base + QUP_OPERATIONAL);
  908. writel_relaxed(0, base + QUP_IO_M_MODES);
  909. if (!controller->qup_v1)
  910. writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
  911. writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN,
  912. base + SPI_ERROR_FLAGS_EN);
  913. /* if earlier version of the QUP, disable INPUT_OVERRUN */
  914. if (controller->qup_v1)
  915. writel_relaxed(QUP_ERROR_OUTPUT_OVER_RUN |
  916. QUP_ERROR_INPUT_UNDER_RUN | QUP_ERROR_OUTPUT_UNDER_RUN,
  917. base + QUP_ERROR_FLAGS_EN);
  918. writel_relaxed(0, base + SPI_CONFIG);
  919. writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
  920. ret = devm_request_irq(dev, irq, spi_qup_qup_irq,
  921. IRQF_TRIGGER_HIGH, pdev->name, controller);
  922. if (ret)
  923. goto error_dma;
  924. pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
  925. pm_runtime_use_autosuspend(dev);
  926. pm_runtime_set_active(dev);
  927. pm_runtime_enable(dev);
  928. ret = devm_spi_register_master(dev, master);
  929. if (ret)
  930. goto disable_pm;
  931. return 0;
  932. disable_pm:
  933. pm_runtime_disable(&pdev->dev);
  934. error_dma:
  935. spi_qup_release_dma(master);
  936. error:
  937. clk_disable_unprepare(cclk);
  938. clk_disable_unprepare(iclk);
  939. spi_master_put(master);
  940. return ret;
  941. }
  942. #ifdef CONFIG_PM
  943. static int spi_qup_pm_suspend_runtime(struct device *device)
  944. {
  945. struct spi_master *master = dev_get_drvdata(device);
  946. struct spi_qup *controller = spi_master_get_devdata(master);
  947. u32 config;
  948. /* Enable clocks auto gaiting */
  949. config = readl(controller->base + QUP_CONFIG);
  950. config |= QUP_CONFIG_CLOCK_AUTO_GATE;
  951. writel_relaxed(config, controller->base + QUP_CONFIG);
  952. clk_disable_unprepare(controller->cclk);
  953. clk_disable_unprepare(controller->iclk);
  954. return 0;
  955. }
  956. static int spi_qup_pm_resume_runtime(struct device *device)
  957. {
  958. struct spi_master *master = dev_get_drvdata(device);
  959. struct spi_qup *controller = spi_master_get_devdata(master);
  960. u32 config;
  961. int ret;
  962. ret = clk_prepare_enable(controller->iclk);
  963. if (ret)
  964. return ret;
  965. ret = clk_prepare_enable(controller->cclk);
  966. if (ret)
  967. return ret;
  968. /* Disable clocks auto gaiting */
  969. config = readl_relaxed(controller->base + QUP_CONFIG);
  970. config &= ~QUP_CONFIG_CLOCK_AUTO_GATE;
  971. writel_relaxed(config, controller->base + QUP_CONFIG);
  972. return 0;
  973. }
  974. #endif /* CONFIG_PM */
  975. #ifdef CONFIG_PM_SLEEP
  976. static int spi_qup_suspend(struct device *device)
  977. {
  978. struct spi_master *master = dev_get_drvdata(device);
  979. struct spi_qup *controller = spi_master_get_devdata(master);
  980. int ret;
  981. if (pm_runtime_suspended(device)) {
  982. ret = spi_qup_pm_resume_runtime(device);
  983. if (ret)
  984. return ret;
  985. }
  986. ret = spi_master_suspend(master);
  987. if (ret)
  988. return ret;
  989. ret = spi_qup_set_state(controller, QUP_STATE_RESET);
  990. if (ret)
  991. return ret;
  992. clk_disable_unprepare(controller->cclk);
  993. clk_disable_unprepare(controller->iclk);
  994. return 0;
  995. }
  996. static int spi_qup_resume(struct device *device)
  997. {
  998. struct spi_master *master = dev_get_drvdata(device);
  999. struct spi_qup *controller = spi_master_get_devdata(master);
  1000. int ret;
  1001. ret = clk_prepare_enable(controller->iclk);
  1002. if (ret)
  1003. return ret;
  1004. ret = clk_prepare_enable(controller->cclk);
  1005. if (ret)
  1006. return ret;
  1007. ret = spi_qup_set_state(controller, QUP_STATE_RESET);
  1008. if (ret)
  1009. return ret;
  1010. return spi_master_resume(master);
  1011. }
  1012. #endif /* CONFIG_PM_SLEEP */
  1013. static int spi_qup_remove(struct platform_device *pdev)
  1014. {
  1015. struct spi_master *master = dev_get_drvdata(&pdev->dev);
  1016. struct spi_qup *controller = spi_master_get_devdata(master);
  1017. int ret;
  1018. ret = pm_runtime_resume_and_get(&pdev->dev);
  1019. if (ret < 0)
  1020. return ret;
  1021. ret = spi_qup_set_state(controller, QUP_STATE_RESET);
  1022. if (ret)
  1023. return ret;
  1024. spi_qup_release_dma(master);
  1025. clk_disable_unprepare(controller->cclk);
  1026. clk_disable_unprepare(controller->iclk);
  1027. pm_runtime_put_noidle(&pdev->dev);
  1028. pm_runtime_disable(&pdev->dev);
  1029. return 0;
  1030. }
  1031. static const struct of_device_id spi_qup_dt_match[] = {
  1032. { .compatible = "qcom,spi-qup-v1.1.1", .data = (void *)1, },
  1033. { .compatible = "qcom,spi-qup-v2.1.1", },
  1034. { .compatible = "qcom,spi-qup-v2.2.1", },
  1035. { }
  1036. };
  1037. MODULE_DEVICE_TABLE(of, spi_qup_dt_match);
  1038. static const struct dev_pm_ops spi_qup_dev_pm_ops = {
  1039. SET_SYSTEM_SLEEP_PM_OPS(spi_qup_suspend, spi_qup_resume)
  1040. SET_RUNTIME_PM_OPS(spi_qup_pm_suspend_runtime,
  1041. spi_qup_pm_resume_runtime,
  1042. NULL)
  1043. };
  1044. static struct platform_driver spi_qup_driver = {
  1045. .driver = {
  1046. .name = "spi_qup",
  1047. .pm = &spi_qup_dev_pm_ops,
  1048. .of_match_table = spi_qup_dt_match,
  1049. },
  1050. .probe = spi_qup_probe,
  1051. .remove = spi_qup_remove,
  1052. };
  1053. module_platform_driver(spi_qup_driver);
  1054. MODULE_LICENSE("GPL v2");
  1055. MODULE_ALIAS("platform:spi_qup");