spi-qcom-qspi.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
  3. #include <linux/clk.h>
  4. #include <linux/interconnect.h>
  5. #include <linux/interrupt.h>
  6. #include <linux/io.h>
  7. #include <linux/module.h>
  8. #include <linux/of.h>
  9. #include <linux/of_platform.h>
  10. #include <linux/pm_runtime.h>
  11. #include <linux/pm_opp.h>
  12. #include <linux/spi/spi.h>
  13. #include <linux/spi/spi-mem.h>
  14. #define QSPI_NUM_CS 2
  15. #define QSPI_BYTES_PER_WORD 4
  16. #define MSTR_CONFIG 0x0000
  17. #define FULL_CYCLE_MODE BIT(3)
  18. #define FB_CLK_EN BIT(4)
  19. #define PIN_HOLDN BIT(6)
  20. #define PIN_WPN BIT(7)
  21. #define DMA_ENABLE BIT(8)
  22. #define BIG_ENDIAN_MODE BIT(9)
  23. #define SPI_MODE_MSK 0xc00
  24. #define SPI_MODE_SHFT 10
  25. #define CHIP_SELECT_NUM BIT(12)
  26. #define SBL_EN BIT(13)
  27. #define LPA_BASE_MSK 0x3c000
  28. #define LPA_BASE_SHFT 14
  29. #define TX_DATA_DELAY_MSK 0xc0000
  30. #define TX_DATA_DELAY_SHFT 18
  31. #define TX_CLK_DELAY_MSK 0x300000
  32. #define TX_CLK_DELAY_SHFT 20
  33. #define TX_CS_N_DELAY_MSK 0xc00000
  34. #define TX_CS_N_DELAY_SHFT 22
  35. #define TX_DATA_OE_DELAY_MSK 0x3000000
  36. #define TX_DATA_OE_DELAY_SHFT 24
  37. #define AHB_MASTER_CFG 0x0004
  38. #define HMEM_TYPE_START_MID_TRANS_MSK 0x7
  39. #define HMEM_TYPE_START_MID_TRANS_SHFT 0
  40. #define HMEM_TYPE_LAST_TRANS_MSK 0x38
  41. #define HMEM_TYPE_LAST_TRANS_SHFT 3
  42. #define USE_HMEMTYPE_LAST_ON_DESC_OR_CHAIN_MSK 0xc0
  43. #define USE_HMEMTYPE_LAST_ON_DESC_OR_CHAIN_SHFT 6
  44. #define HMEMTYPE_READ_TRANS_MSK 0x700
  45. #define HMEMTYPE_READ_TRANS_SHFT 8
  46. #define HSHARED BIT(11)
  47. #define HINNERSHARED BIT(12)
  48. #define MSTR_INT_EN 0x000C
  49. #define MSTR_INT_STATUS 0x0010
  50. #define RESP_FIFO_UNDERRUN BIT(0)
  51. #define RESP_FIFO_NOT_EMPTY BIT(1)
  52. #define RESP_FIFO_RDY BIT(2)
  53. #define HRESP_FROM_NOC_ERR BIT(3)
  54. #define WR_FIFO_EMPTY BIT(9)
  55. #define WR_FIFO_FULL BIT(10)
  56. #define WR_FIFO_OVERRUN BIT(11)
  57. #define TRANSACTION_DONE BIT(16)
  58. #define QSPI_ERR_IRQS (RESP_FIFO_UNDERRUN | HRESP_FROM_NOC_ERR | \
  59. WR_FIFO_OVERRUN)
  60. #define QSPI_ALL_IRQS (QSPI_ERR_IRQS | RESP_FIFO_RDY | \
  61. WR_FIFO_EMPTY | WR_FIFO_FULL | \
  62. TRANSACTION_DONE)
  63. #define PIO_XFER_CTRL 0x0014
  64. #define REQUEST_COUNT_MSK 0xffff
  65. #define PIO_XFER_CFG 0x0018
  66. #define TRANSFER_DIRECTION BIT(0)
  67. #define MULTI_IO_MODE_MSK 0xe
  68. #define MULTI_IO_MODE_SHFT 1
  69. #define TRANSFER_FRAGMENT BIT(8)
  70. #define SDR_1BIT 1
  71. #define SDR_2BIT 2
  72. #define SDR_4BIT 3
  73. #define DDR_1BIT 5
  74. #define DDR_2BIT 6
  75. #define DDR_4BIT 7
  76. #define DMA_DESC_SINGLE_SPI 1
  77. #define DMA_DESC_DUAL_SPI 2
  78. #define DMA_DESC_QUAD_SPI 3
  79. #define PIO_XFER_STATUS 0x001c
  80. #define WR_FIFO_BYTES_MSK 0xffff0000
  81. #define WR_FIFO_BYTES_SHFT 16
  82. #define PIO_DATAOUT_1B 0x0020
  83. #define PIO_DATAOUT_4B 0x0024
  84. #define RD_FIFO_CFG 0x0028
  85. #define CONTINUOUS_MODE BIT(0)
  86. #define RD_FIFO_STATUS 0x002c
  87. #define FIFO_EMPTY BIT(11)
  88. #define WR_CNTS_MSK 0x7f0
  89. #define WR_CNTS_SHFT 4
  90. #define RDY_64BYTE BIT(3)
  91. #define RDY_32BYTE BIT(2)
  92. #define RDY_16BYTE BIT(1)
  93. #define FIFO_RDY BIT(0)
  94. #define RD_FIFO_RESET 0x0030
  95. #define RESET_FIFO BIT(0)
  96. #define CUR_MEM_ADDR 0x0048
  97. #define HW_VERSION 0x004c
  98. #define RD_FIFO 0x0050
  99. #define SAMPLING_CLK_CFG 0x0090
  100. #define SAMPLING_CLK_STATUS 0x0094
  101. enum qspi_dir {
  102. QSPI_READ,
  103. QSPI_WRITE,
  104. };
  105. struct qspi_xfer {
  106. union {
  107. const void *tx_buf;
  108. void *rx_buf;
  109. };
  110. unsigned int rem_bytes;
  111. unsigned int buswidth;
  112. enum qspi_dir dir;
  113. bool is_last;
  114. };
  115. enum qspi_clocks {
  116. QSPI_CLK_CORE,
  117. QSPI_CLK_IFACE,
  118. QSPI_NUM_CLKS
  119. };
  120. struct qcom_qspi {
  121. void __iomem *base;
  122. struct device *dev;
  123. struct clk_bulk_data *clks;
  124. struct qspi_xfer xfer;
  125. struct icc_path *icc_path_cpu_to_qspi;
  126. struct opp_table *opp_table;
  127. unsigned long last_speed;
  128. /* Lock to protect data accessed by IRQs */
  129. spinlock_t lock;
  130. };
  131. static u32 qspi_buswidth_to_iomode(struct qcom_qspi *ctrl,
  132. unsigned int buswidth)
  133. {
  134. switch (buswidth) {
  135. case 1:
  136. return SDR_1BIT << MULTI_IO_MODE_SHFT;
  137. case 2:
  138. return SDR_2BIT << MULTI_IO_MODE_SHFT;
  139. case 4:
  140. return SDR_4BIT << MULTI_IO_MODE_SHFT;
  141. default:
  142. dev_warn_once(ctrl->dev,
  143. "Unexpected bus width: %u\n", buswidth);
  144. return SDR_1BIT << MULTI_IO_MODE_SHFT;
  145. }
  146. }
  147. static void qcom_qspi_pio_xfer_cfg(struct qcom_qspi *ctrl)
  148. {
  149. u32 pio_xfer_cfg;
  150. const struct qspi_xfer *xfer;
  151. xfer = &ctrl->xfer;
  152. pio_xfer_cfg = readl(ctrl->base + PIO_XFER_CFG);
  153. pio_xfer_cfg &= ~TRANSFER_DIRECTION;
  154. pio_xfer_cfg |= xfer->dir;
  155. if (xfer->is_last)
  156. pio_xfer_cfg &= ~TRANSFER_FRAGMENT;
  157. else
  158. pio_xfer_cfg |= TRANSFER_FRAGMENT;
  159. pio_xfer_cfg &= ~MULTI_IO_MODE_MSK;
  160. pio_xfer_cfg |= qspi_buswidth_to_iomode(ctrl, xfer->buswidth);
  161. writel(pio_xfer_cfg, ctrl->base + PIO_XFER_CFG);
  162. }
  163. static void qcom_qspi_pio_xfer_ctrl(struct qcom_qspi *ctrl)
  164. {
  165. u32 pio_xfer_ctrl;
  166. pio_xfer_ctrl = readl(ctrl->base + PIO_XFER_CTRL);
  167. pio_xfer_ctrl &= ~REQUEST_COUNT_MSK;
  168. pio_xfer_ctrl |= ctrl->xfer.rem_bytes;
  169. writel(pio_xfer_ctrl, ctrl->base + PIO_XFER_CTRL);
  170. }
  171. static void qcom_qspi_pio_xfer(struct qcom_qspi *ctrl)
  172. {
  173. u32 ints;
  174. qcom_qspi_pio_xfer_cfg(ctrl);
  175. /* Ack any previous interrupts that might be hanging around */
  176. writel(QSPI_ALL_IRQS, ctrl->base + MSTR_INT_STATUS);
  177. /* Setup new interrupts */
  178. if (ctrl->xfer.dir == QSPI_WRITE)
  179. ints = QSPI_ERR_IRQS | WR_FIFO_EMPTY;
  180. else
  181. ints = QSPI_ERR_IRQS | RESP_FIFO_RDY;
  182. writel(ints, ctrl->base + MSTR_INT_EN);
  183. /* Kick off the transfer */
  184. qcom_qspi_pio_xfer_ctrl(ctrl);
  185. }
  186. static void qcom_qspi_handle_err(struct spi_master *master,
  187. struct spi_message *msg)
  188. {
  189. struct qcom_qspi *ctrl = spi_master_get_devdata(master);
  190. unsigned long flags;
  191. spin_lock_irqsave(&ctrl->lock, flags);
  192. writel(0, ctrl->base + MSTR_INT_EN);
  193. ctrl->xfer.rem_bytes = 0;
  194. spin_unlock_irqrestore(&ctrl->lock, flags);
  195. }
  196. static int qcom_qspi_set_speed(struct qcom_qspi *ctrl, unsigned long speed_hz)
  197. {
  198. int ret;
  199. unsigned int avg_bw_cpu;
  200. if (speed_hz == ctrl->last_speed)
  201. return 0;
  202. /* In regular operation (SBL_EN=1) core must be 4x transfer clock */
  203. ret = dev_pm_opp_set_rate(ctrl->dev, speed_hz * 4);
  204. if (ret) {
  205. dev_err(ctrl->dev, "Failed to set core clk %d\n", ret);
  206. return ret;
  207. }
  208. /*
  209. * Set BW quota for CPU as driver supports FIFO mode only.
  210. * We don't have explicit peak requirement so keep it equal to avg_bw.
  211. */
  212. avg_bw_cpu = Bps_to_icc(speed_hz);
  213. ret = icc_set_bw(ctrl->icc_path_cpu_to_qspi, avg_bw_cpu, avg_bw_cpu);
  214. if (ret) {
  215. dev_err(ctrl->dev, "%s: ICC BW voting failed for cpu: %d\n",
  216. __func__, ret);
  217. return ret;
  218. }
  219. ctrl->last_speed = speed_hz;
  220. return 0;
  221. }
  222. static int qcom_qspi_transfer_one(struct spi_master *master,
  223. struct spi_device *slv,
  224. struct spi_transfer *xfer)
  225. {
  226. struct qcom_qspi *ctrl = spi_master_get_devdata(master);
  227. int ret;
  228. unsigned long speed_hz;
  229. unsigned long flags;
  230. speed_hz = slv->max_speed_hz;
  231. if (xfer->speed_hz)
  232. speed_hz = xfer->speed_hz;
  233. ret = qcom_qspi_set_speed(ctrl, speed_hz);
  234. if (ret)
  235. return ret;
  236. spin_lock_irqsave(&ctrl->lock, flags);
  237. /* We are half duplex, so either rx or tx will be set */
  238. if (xfer->rx_buf) {
  239. ctrl->xfer.dir = QSPI_READ;
  240. ctrl->xfer.buswidth = xfer->rx_nbits;
  241. ctrl->xfer.rx_buf = xfer->rx_buf;
  242. } else {
  243. ctrl->xfer.dir = QSPI_WRITE;
  244. ctrl->xfer.buswidth = xfer->tx_nbits;
  245. ctrl->xfer.tx_buf = xfer->tx_buf;
  246. }
  247. ctrl->xfer.is_last = list_is_last(&xfer->transfer_list,
  248. &master->cur_msg->transfers);
  249. ctrl->xfer.rem_bytes = xfer->len;
  250. qcom_qspi_pio_xfer(ctrl);
  251. spin_unlock_irqrestore(&ctrl->lock, flags);
  252. /* We'll call spi_finalize_current_transfer() when done */
  253. return 1;
  254. }
  255. static int qcom_qspi_prepare_message(struct spi_master *master,
  256. struct spi_message *message)
  257. {
  258. u32 mstr_cfg;
  259. struct qcom_qspi *ctrl;
  260. int tx_data_oe_delay = 1;
  261. int tx_data_delay = 1;
  262. unsigned long flags;
  263. ctrl = spi_master_get_devdata(master);
  264. spin_lock_irqsave(&ctrl->lock, flags);
  265. mstr_cfg = readl(ctrl->base + MSTR_CONFIG);
  266. mstr_cfg &= ~CHIP_SELECT_NUM;
  267. if (message->spi->chip_select)
  268. mstr_cfg |= CHIP_SELECT_NUM;
  269. mstr_cfg |= FB_CLK_EN | PIN_WPN | PIN_HOLDN | SBL_EN | FULL_CYCLE_MODE;
  270. mstr_cfg &= ~(SPI_MODE_MSK | TX_DATA_OE_DELAY_MSK | TX_DATA_DELAY_MSK);
  271. mstr_cfg |= message->spi->mode << SPI_MODE_SHFT;
  272. mstr_cfg |= tx_data_oe_delay << TX_DATA_OE_DELAY_SHFT;
  273. mstr_cfg |= tx_data_delay << TX_DATA_DELAY_SHFT;
  274. mstr_cfg &= ~DMA_ENABLE;
  275. writel(mstr_cfg, ctrl->base + MSTR_CONFIG);
  276. spin_unlock_irqrestore(&ctrl->lock, flags);
  277. return 0;
  278. }
  279. static irqreturn_t pio_read(struct qcom_qspi *ctrl)
  280. {
  281. u32 rd_fifo_status;
  282. u32 rd_fifo;
  283. unsigned int wr_cnts;
  284. unsigned int bytes_to_read;
  285. unsigned int words_to_read;
  286. u32 *word_buf;
  287. u8 *byte_buf;
  288. int i;
  289. rd_fifo_status = readl(ctrl->base + RD_FIFO_STATUS);
  290. if (!(rd_fifo_status & FIFO_RDY)) {
  291. dev_dbg(ctrl->dev, "Spurious IRQ %#x\n", rd_fifo_status);
  292. return IRQ_NONE;
  293. }
  294. wr_cnts = (rd_fifo_status & WR_CNTS_MSK) >> WR_CNTS_SHFT;
  295. wr_cnts = min(wr_cnts, ctrl->xfer.rem_bytes);
  296. words_to_read = wr_cnts / QSPI_BYTES_PER_WORD;
  297. bytes_to_read = wr_cnts % QSPI_BYTES_PER_WORD;
  298. if (words_to_read) {
  299. word_buf = ctrl->xfer.rx_buf;
  300. ctrl->xfer.rem_bytes -= words_to_read * QSPI_BYTES_PER_WORD;
  301. ioread32_rep(ctrl->base + RD_FIFO, word_buf, words_to_read);
  302. ctrl->xfer.rx_buf = word_buf + words_to_read;
  303. }
  304. if (bytes_to_read) {
  305. byte_buf = ctrl->xfer.rx_buf;
  306. rd_fifo = readl(ctrl->base + RD_FIFO);
  307. ctrl->xfer.rem_bytes -= bytes_to_read;
  308. for (i = 0; i < bytes_to_read; i++)
  309. *byte_buf++ = rd_fifo >> (i * BITS_PER_BYTE);
  310. ctrl->xfer.rx_buf = byte_buf;
  311. }
  312. return IRQ_HANDLED;
  313. }
  314. static irqreturn_t pio_write(struct qcom_qspi *ctrl)
  315. {
  316. const void *xfer_buf = ctrl->xfer.tx_buf;
  317. const int *word_buf;
  318. const char *byte_buf;
  319. unsigned int wr_fifo_bytes;
  320. unsigned int wr_fifo_words;
  321. unsigned int wr_size;
  322. unsigned int rem_words;
  323. wr_fifo_bytes = readl(ctrl->base + PIO_XFER_STATUS);
  324. wr_fifo_bytes >>= WR_FIFO_BYTES_SHFT;
  325. if (ctrl->xfer.rem_bytes < QSPI_BYTES_PER_WORD) {
  326. /* Process the last 1-3 bytes */
  327. wr_size = min(wr_fifo_bytes, ctrl->xfer.rem_bytes);
  328. ctrl->xfer.rem_bytes -= wr_size;
  329. byte_buf = xfer_buf;
  330. while (wr_size--)
  331. writel(*byte_buf++,
  332. ctrl->base + PIO_DATAOUT_1B);
  333. ctrl->xfer.tx_buf = byte_buf;
  334. } else {
  335. /*
  336. * Process all the whole words; to keep things simple we'll
  337. * just wait for the next interrupt to handle the last 1-3
  338. * bytes if we don't have an even number of words.
  339. */
  340. rem_words = ctrl->xfer.rem_bytes / QSPI_BYTES_PER_WORD;
  341. wr_fifo_words = wr_fifo_bytes / QSPI_BYTES_PER_WORD;
  342. wr_size = min(rem_words, wr_fifo_words);
  343. ctrl->xfer.rem_bytes -= wr_size * QSPI_BYTES_PER_WORD;
  344. word_buf = xfer_buf;
  345. iowrite32_rep(ctrl->base + PIO_DATAOUT_4B, word_buf, wr_size);
  346. ctrl->xfer.tx_buf = word_buf + wr_size;
  347. }
  348. return IRQ_HANDLED;
  349. }
  350. static irqreturn_t qcom_qspi_irq(int irq, void *dev_id)
  351. {
  352. u32 int_status;
  353. struct qcom_qspi *ctrl = dev_id;
  354. irqreturn_t ret = IRQ_NONE;
  355. spin_lock(&ctrl->lock);
  356. int_status = readl(ctrl->base + MSTR_INT_STATUS);
  357. writel(int_status, ctrl->base + MSTR_INT_STATUS);
  358. if (ctrl->xfer.dir == QSPI_WRITE) {
  359. if (int_status & WR_FIFO_EMPTY)
  360. ret = pio_write(ctrl);
  361. } else {
  362. if (int_status & RESP_FIFO_RDY)
  363. ret = pio_read(ctrl);
  364. }
  365. if (int_status & QSPI_ERR_IRQS) {
  366. if (int_status & RESP_FIFO_UNDERRUN)
  367. dev_err(ctrl->dev, "IRQ error: FIFO underrun\n");
  368. if (int_status & WR_FIFO_OVERRUN)
  369. dev_err(ctrl->dev, "IRQ error: FIFO overrun\n");
  370. if (int_status & HRESP_FROM_NOC_ERR)
  371. dev_err(ctrl->dev, "IRQ error: NOC response error\n");
  372. ret = IRQ_HANDLED;
  373. }
  374. if (!ctrl->xfer.rem_bytes) {
  375. writel(0, ctrl->base + MSTR_INT_EN);
  376. spi_finalize_current_transfer(dev_get_drvdata(ctrl->dev));
  377. }
  378. spin_unlock(&ctrl->lock);
  379. return ret;
  380. }
  381. static int qcom_qspi_probe(struct platform_device *pdev)
  382. {
  383. int ret;
  384. struct device *dev;
  385. struct spi_master *master;
  386. struct qcom_qspi *ctrl;
  387. dev = &pdev->dev;
  388. master = devm_spi_alloc_master(dev, sizeof(*ctrl));
  389. if (!master)
  390. return -ENOMEM;
  391. platform_set_drvdata(pdev, master);
  392. ctrl = spi_master_get_devdata(master);
  393. spin_lock_init(&ctrl->lock);
  394. ctrl->dev = dev;
  395. ctrl->base = devm_platform_ioremap_resource(pdev, 0);
  396. if (IS_ERR(ctrl->base))
  397. return PTR_ERR(ctrl->base);
  398. ctrl->clks = devm_kcalloc(dev, QSPI_NUM_CLKS,
  399. sizeof(*ctrl->clks), GFP_KERNEL);
  400. if (!ctrl->clks)
  401. return -ENOMEM;
  402. ctrl->clks[QSPI_CLK_CORE].id = "core";
  403. ctrl->clks[QSPI_CLK_IFACE].id = "iface";
  404. ret = devm_clk_bulk_get(dev, QSPI_NUM_CLKS, ctrl->clks);
  405. if (ret)
  406. return ret;
  407. ctrl->icc_path_cpu_to_qspi = devm_of_icc_get(dev, "qspi-config");
  408. if (IS_ERR(ctrl->icc_path_cpu_to_qspi))
  409. return dev_err_probe(dev, PTR_ERR(ctrl->icc_path_cpu_to_qspi),
  410. "Failed to get cpu path\n");
  411. /* Set BW vote for register access */
  412. ret = icc_set_bw(ctrl->icc_path_cpu_to_qspi, Bps_to_icc(1000),
  413. Bps_to_icc(1000));
  414. if (ret) {
  415. dev_err(ctrl->dev, "%s: ICC BW voting failed for cpu: %d\n",
  416. __func__, ret);
  417. return ret;
  418. }
  419. ret = icc_disable(ctrl->icc_path_cpu_to_qspi);
  420. if (ret) {
  421. dev_err(ctrl->dev, "%s: ICC disable failed for cpu: %d\n",
  422. __func__, ret);
  423. return ret;
  424. }
  425. ret = platform_get_irq(pdev, 0);
  426. if (ret < 0)
  427. return ret;
  428. ret = devm_request_irq(dev, ret, qcom_qspi_irq,
  429. IRQF_TRIGGER_HIGH, dev_name(dev), ctrl);
  430. if (ret) {
  431. dev_err(dev, "Failed to request irq %d\n", ret);
  432. return ret;
  433. }
  434. master->max_speed_hz = 300000000;
  435. master->num_chipselect = QSPI_NUM_CS;
  436. master->bus_num = -1;
  437. master->dev.of_node = pdev->dev.of_node;
  438. master->mode_bits = SPI_MODE_0 |
  439. SPI_TX_DUAL | SPI_RX_DUAL |
  440. SPI_TX_QUAD | SPI_RX_QUAD;
  441. master->flags = SPI_MASTER_HALF_DUPLEX;
  442. master->prepare_message = qcom_qspi_prepare_message;
  443. master->transfer_one = qcom_qspi_transfer_one;
  444. master->handle_err = qcom_qspi_handle_err;
  445. master->auto_runtime_pm = true;
  446. ctrl->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "core");
  447. if (IS_ERR(ctrl->opp_table))
  448. return PTR_ERR(ctrl->opp_table);
  449. /* OPP table is optional */
  450. ret = dev_pm_opp_of_add_table(&pdev->dev);
  451. if (ret && ret != -ENODEV) {
  452. dev_err(&pdev->dev, "invalid OPP table in device tree\n");
  453. goto exit_probe_put_clkname;
  454. }
  455. pm_runtime_use_autosuspend(dev);
  456. pm_runtime_set_autosuspend_delay(dev, 250);
  457. pm_runtime_enable(dev);
  458. ret = spi_register_master(master);
  459. if (!ret)
  460. return 0;
  461. pm_runtime_disable(dev);
  462. dev_pm_opp_of_remove_table(&pdev->dev);
  463. exit_probe_put_clkname:
  464. dev_pm_opp_put_clkname(ctrl->opp_table);
  465. return ret;
  466. }
  467. static int qcom_qspi_remove(struct platform_device *pdev)
  468. {
  469. struct spi_master *master = platform_get_drvdata(pdev);
  470. struct qcom_qspi *ctrl = spi_master_get_devdata(master);
  471. /* Unregister _before_ disabling pm_runtime() so we stop transfers */
  472. spi_unregister_master(master);
  473. pm_runtime_disable(&pdev->dev);
  474. dev_pm_opp_of_remove_table(&pdev->dev);
  475. dev_pm_opp_put_clkname(ctrl->opp_table);
  476. return 0;
  477. }
  478. static int __maybe_unused qcom_qspi_runtime_suspend(struct device *dev)
  479. {
  480. struct spi_master *master = dev_get_drvdata(dev);
  481. struct qcom_qspi *ctrl = spi_master_get_devdata(master);
  482. int ret;
  483. /* Drop the performance state vote */
  484. dev_pm_opp_set_rate(dev, 0);
  485. clk_bulk_disable_unprepare(QSPI_NUM_CLKS, ctrl->clks);
  486. ret = icc_disable(ctrl->icc_path_cpu_to_qspi);
  487. if (ret) {
  488. dev_err_ratelimited(ctrl->dev, "%s: ICC disable failed for cpu: %d\n",
  489. __func__, ret);
  490. return ret;
  491. }
  492. return 0;
  493. }
  494. static int __maybe_unused qcom_qspi_runtime_resume(struct device *dev)
  495. {
  496. struct spi_master *master = dev_get_drvdata(dev);
  497. struct qcom_qspi *ctrl = spi_master_get_devdata(master);
  498. int ret;
  499. ret = icc_enable(ctrl->icc_path_cpu_to_qspi);
  500. if (ret) {
  501. dev_err_ratelimited(ctrl->dev, "%s: ICC enable failed for cpu: %d\n",
  502. __func__, ret);
  503. return ret;
  504. }
  505. ret = clk_bulk_prepare_enable(QSPI_NUM_CLKS, ctrl->clks);
  506. if (ret)
  507. return ret;
  508. return dev_pm_opp_set_rate(dev, ctrl->last_speed * 4);
  509. }
  510. static int __maybe_unused qcom_qspi_suspend(struct device *dev)
  511. {
  512. struct spi_master *master = dev_get_drvdata(dev);
  513. int ret;
  514. ret = spi_master_suspend(master);
  515. if (ret)
  516. return ret;
  517. ret = pm_runtime_force_suspend(dev);
  518. if (ret)
  519. spi_master_resume(master);
  520. return ret;
  521. }
  522. static int __maybe_unused qcom_qspi_resume(struct device *dev)
  523. {
  524. struct spi_master *master = dev_get_drvdata(dev);
  525. int ret;
  526. ret = pm_runtime_force_resume(dev);
  527. if (ret)
  528. return ret;
  529. ret = spi_master_resume(master);
  530. if (ret)
  531. pm_runtime_force_suspend(dev);
  532. return ret;
  533. }
  534. static const struct dev_pm_ops qcom_qspi_dev_pm_ops = {
  535. SET_RUNTIME_PM_OPS(qcom_qspi_runtime_suspend,
  536. qcom_qspi_runtime_resume, NULL)
  537. SET_SYSTEM_SLEEP_PM_OPS(qcom_qspi_suspend, qcom_qspi_resume)
  538. };
  539. static const struct of_device_id qcom_qspi_dt_match[] = {
  540. { .compatible = "qcom,qspi-v1", },
  541. { }
  542. };
  543. MODULE_DEVICE_TABLE(of, qcom_qspi_dt_match);
  544. static struct platform_driver qcom_qspi_driver = {
  545. .driver = {
  546. .name = "qcom_qspi",
  547. .pm = &qcom_qspi_dev_pm_ops,
  548. .of_match_table = qcom_qspi_dt_match,
  549. },
  550. .probe = qcom_qspi_probe,
  551. .remove = qcom_qspi_remove,
  552. };
  553. module_platform_driver(qcom_qspi_driver);
  554. MODULE_DESCRIPTION("SPI driver for QSPI cores");
  555. MODULE_LICENSE("GPL v2");