spi-pxa2xx.c 52 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
  4. * Copyright (C) 2013, Intel Corporation
  5. */
  6. #include <linux/acpi.h>
  7. #include <linux/bitops.h>
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/device.h>
  11. #include <linux/err.h>
  12. #include <linux/errno.h>
  13. #include <linux/gpio/consumer.h>
  14. #include <linux/gpio.h>
  15. #include <linux/init.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/ioport.h>
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/mod_devicetable.h>
  21. #include <linux/of.h>
  22. #include <linux/pci.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/pm_runtime.h>
  25. #include <linux/property.h>
  26. #include <linux/slab.h>
  27. #include <linux/spi/pxa2xx_spi.h>
  28. #include <linux/spi/spi.h>
  29. #include "spi-pxa2xx.h"
  30. MODULE_AUTHOR("Stephen Street");
  31. MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
  32. MODULE_LICENSE("GPL");
  33. MODULE_ALIAS("platform:pxa2xx-spi");
  34. #define TIMOUT_DFLT 1000
  35. /*
  36. * for testing SSCR1 changes that require SSP restart, basically
  37. * everything except the service and interrupt enables, the pxa270 developer
  38. * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
  39. * list, but the PXA255 dev man says all bits without really meaning the
  40. * service and interrupt enables
  41. */
  42. #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  43. | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  44. | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  45. | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  46. | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
  47. | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  48. #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
  49. | QUARK_X1000_SSCR1_EFWR \
  50. | QUARK_X1000_SSCR1_RFT \
  51. | QUARK_X1000_SSCR1_TFT \
  52. | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  53. #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  54. | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  55. | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  56. | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  57. | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
  58. | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  59. #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
  60. #define LPSS_CS_CONTROL_SW_MODE BIT(0)
  61. #define LPSS_CS_CONTROL_CS_HIGH BIT(1)
  62. #define LPSS_CAPS_CS_EN_SHIFT 9
  63. #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
  64. #define LPSS_PRIV_CLOCK_GATE 0x38
  65. #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
  66. #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
  67. struct lpss_config {
  68. /* LPSS offset from drv_data->ioaddr */
  69. unsigned offset;
  70. /* Register offsets from drv_data->lpss_base or -1 */
  71. int reg_general;
  72. int reg_ssp;
  73. int reg_cs_ctrl;
  74. int reg_capabilities;
  75. /* FIFO thresholds */
  76. u32 rx_threshold;
  77. u32 tx_threshold_lo;
  78. u32 tx_threshold_hi;
  79. /* Chip select control */
  80. unsigned cs_sel_shift;
  81. unsigned cs_sel_mask;
  82. unsigned cs_num;
  83. /* Quirks */
  84. unsigned cs_clk_stays_gated : 1;
  85. };
  86. /* Keep these sorted with enum pxa_ssp_type */
  87. static const struct lpss_config lpss_platforms[] = {
  88. { /* LPSS_LPT_SSP */
  89. .offset = 0x800,
  90. .reg_general = 0x08,
  91. .reg_ssp = 0x0c,
  92. .reg_cs_ctrl = 0x18,
  93. .reg_capabilities = -1,
  94. .rx_threshold = 64,
  95. .tx_threshold_lo = 160,
  96. .tx_threshold_hi = 224,
  97. },
  98. { /* LPSS_BYT_SSP */
  99. .offset = 0x400,
  100. .reg_general = 0x08,
  101. .reg_ssp = 0x0c,
  102. .reg_cs_ctrl = 0x18,
  103. .reg_capabilities = -1,
  104. .rx_threshold = 64,
  105. .tx_threshold_lo = 160,
  106. .tx_threshold_hi = 224,
  107. },
  108. { /* LPSS_BSW_SSP */
  109. .offset = 0x400,
  110. .reg_general = 0x08,
  111. .reg_ssp = 0x0c,
  112. .reg_cs_ctrl = 0x18,
  113. .reg_capabilities = -1,
  114. .rx_threshold = 64,
  115. .tx_threshold_lo = 160,
  116. .tx_threshold_hi = 224,
  117. .cs_sel_shift = 2,
  118. .cs_sel_mask = 1 << 2,
  119. .cs_num = 2,
  120. },
  121. { /* LPSS_SPT_SSP */
  122. .offset = 0x200,
  123. .reg_general = -1,
  124. .reg_ssp = 0x20,
  125. .reg_cs_ctrl = 0x24,
  126. .reg_capabilities = -1,
  127. .rx_threshold = 1,
  128. .tx_threshold_lo = 32,
  129. .tx_threshold_hi = 56,
  130. },
  131. { /* LPSS_BXT_SSP */
  132. .offset = 0x200,
  133. .reg_general = -1,
  134. .reg_ssp = 0x20,
  135. .reg_cs_ctrl = 0x24,
  136. .reg_capabilities = 0xfc,
  137. .rx_threshold = 1,
  138. .tx_threshold_lo = 16,
  139. .tx_threshold_hi = 48,
  140. .cs_sel_shift = 8,
  141. .cs_sel_mask = 3 << 8,
  142. .cs_clk_stays_gated = true,
  143. },
  144. { /* LPSS_CNL_SSP */
  145. .offset = 0x200,
  146. .reg_general = -1,
  147. .reg_ssp = 0x20,
  148. .reg_cs_ctrl = 0x24,
  149. .reg_capabilities = 0xfc,
  150. .rx_threshold = 1,
  151. .tx_threshold_lo = 32,
  152. .tx_threshold_hi = 56,
  153. .cs_sel_shift = 8,
  154. .cs_sel_mask = 3 << 8,
  155. .cs_clk_stays_gated = true,
  156. },
  157. };
  158. static inline const struct lpss_config
  159. *lpss_get_config(const struct driver_data *drv_data)
  160. {
  161. return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
  162. }
  163. static bool is_lpss_ssp(const struct driver_data *drv_data)
  164. {
  165. switch (drv_data->ssp_type) {
  166. case LPSS_LPT_SSP:
  167. case LPSS_BYT_SSP:
  168. case LPSS_BSW_SSP:
  169. case LPSS_SPT_SSP:
  170. case LPSS_BXT_SSP:
  171. case LPSS_CNL_SSP:
  172. return true;
  173. default:
  174. return false;
  175. }
  176. }
  177. static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
  178. {
  179. return drv_data->ssp_type == QUARK_X1000_SSP;
  180. }
  181. static bool is_mmp2_ssp(const struct driver_data *drv_data)
  182. {
  183. return drv_data->ssp_type == MMP2_SSP;
  184. }
  185. static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
  186. {
  187. switch (drv_data->ssp_type) {
  188. case QUARK_X1000_SSP:
  189. return QUARK_X1000_SSCR1_CHANGE_MASK;
  190. case CE4100_SSP:
  191. return CE4100_SSCR1_CHANGE_MASK;
  192. default:
  193. return SSCR1_CHANGE_MASK;
  194. }
  195. }
  196. static u32
  197. pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
  198. {
  199. switch (drv_data->ssp_type) {
  200. case QUARK_X1000_SSP:
  201. return RX_THRESH_QUARK_X1000_DFLT;
  202. case CE4100_SSP:
  203. return RX_THRESH_CE4100_DFLT;
  204. default:
  205. return RX_THRESH_DFLT;
  206. }
  207. }
  208. static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
  209. {
  210. u32 mask;
  211. switch (drv_data->ssp_type) {
  212. case QUARK_X1000_SSP:
  213. mask = QUARK_X1000_SSSR_TFL_MASK;
  214. break;
  215. case CE4100_SSP:
  216. mask = CE4100_SSSR_TFL_MASK;
  217. break;
  218. default:
  219. mask = SSSR_TFL_MASK;
  220. break;
  221. }
  222. return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
  223. }
  224. static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
  225. u32 *sccr1_reg)
  226. {
  227. u32 mask;
  228. switch (drv_data->ssp_type) {
  229. case QUARK_X1000_SSP:
  230. mask = QUARK_X1000_SSCR1_RFT;
  231. break;
  232. case CE4100_SSP:
  233. mask = CE4100_SSCR1_RFT;
  234. break;
  235. default:
  236. mask = SSCR1_RFT;
  237. break;
  238. }
  239. *sccr1_reg &= ~mask;
  240. }
  241. static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
  242. u32 *sccr1_reg, u32 threshold)
  243. {
  244. switch (drv_data->ssp_type) {
  245. case QUARK_X1000_SSP:
  246. *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
  247. break;
  248. case CE4100_SSP:
  249. *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
  250. break;
  251. default:
  252. *sccr1_reg |= SSCR1_RxTresh(threshold);
  253. break;
  254. }
  255. }
  256. static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
  257. u32 clk_div, u8 bits)
  258. {
  259. switch (drv_data->ssp_type) {
  260. case QUARK_X1000_SSP:
  261. return clk_div
  262. | QUARK_X1000_SSCR0_Motorola
  263. | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
  264. | SSCR0_SSE;
  265. default:
  266. return clk_div
  267. | SSCR0_Motorola
  268. | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
  269. | SSCR0_SSE
  270. | (bits > 16 ? SSCR0_EDSS : 0);
  271. }
  272. }
  273. /*
  274. * Read and write LPSS SSP private registers. Caller must first check that
  275. * is_lpss_ssp() returns true before these can be called.
  276. */
  277. static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
  278. {
  279. WARN_ON(!drv_data->lpss_base);
  280. return readl(drv_data->lpss_base + offset);
  281. }
  282. static void __lpss_ssp_write_priv(struct driver_data *drv_data,
  283. unsigned offset, u32 value)
  284. {
  285. WARN_ON(!drv_data->lpss_base);
  286. writel(value, drv_data->lpss_base + offset);
  287. }
  288. /*
  289. * lpss_ssp_setup - perform LPSS SSP specific setup
  290. * @drv_data: pointer to the driver private data
  291. *
  292. * Perform LPSS SSP specific setup. This function must be called first if
  293. * one is going to use LPSS SSP private registers.
  294. */
  295. static void lpss_ssp_setup(struct driver_data *drv_data)
  296. {
  297. const struct lpss_config *config;
  298. u32 value;
  299. config = lpss_get_config(drv_data);
  300. drv_data->lpss_base = drv_data->ioaddr + config->offset;
  301. /* Enable software chip select control */
  302. value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
  303. value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
  304. value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
  305. __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
  306. /* Enable multiblock DMA transfers */
  307. if (drv_data->controller_info->enable_dma) {
  308. __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
  309. if (config->reg_general >= 0) {
  310. value = __lpss_ssp_read_priv(drv_data,
  311. config->reg_general);
  312. value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
  313. __lpss_ssp_write_priv(drv_data,
  314. config->reg_general, value);
  315. }
  316. }
  317. }
  318. static void lpss_ssp_select_cs(struct spi_device *spi,
  319. const struct lpss_config *config)
  320. {
  321. struct driver_data *drv_data =
  322. spi_controller_get_devdata(spi->controller);
  323. u32 value, cs;
  324. if (!config->cs_sel_mask)
  325. return;
  326. value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
  327. cs = spi->chip_select;
  328. cs <<= config->cs_sel_shift;
  329. if (cs != (value & config->cs_sel_mask)) {
  330. /*
  331. * When switching another chip select output active the
  332. * output must be selected first and wait 2 ssp_clk cycles
  333. * before changing state to active. Otherwise a short
  334. * glitch will occur on the previous chip select since
  335. * output select is latched but state control is not.
  336. */
  337. value &= ~config->cs_sel_mask;
  338. value |= cs;
  339. __lpss_ssp_write_priv(drv_data,
  340. config->reg_cs_ctrl, value);
  341. ndelay(1000000000 /
  342. (drv_data->controller->max_speed_hz / 2));
  343. }
  344. }
  345. static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
  346. {
  347. struct driver_data *drv_data =
  348. spi_controller_get_devdata(spi->controller);
  349. const struct lpss_config *config;
  350. u32 value;
  351. config = lpss_get_config(drv_data);
  352. if (enable)
  353. lpss_ssp_select_cs(spi, config);
  354. value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
  355. if (enable)
  356. value &= ~LPSS_CS_CONTROL_CS_HIGH;
  357. else
  358. value |= LPSS_CS_CONTROL_CS_HIGH;
  359. __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
  360. if (config->cs_clk_stays_gated) {
  361. u32 clkgate;
  362. /*
  363. * Changing CS alone when dynamic clock gating is on won't
  364. * actually flip CS at that time. This ruins SPI transfers
  365. * that specify delays, or have no data. Toggle the clock mode
  366. * to force on briefly to poke the CS pin to move.
  367. */
  368. clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
  369. value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
  370. LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
  371. __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
  372. __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
  373. }
  374. }
  375. static void cs_assert(struct spi_device *spi)
  376. {
  377. struct chip_data *chip = spi_get_ctldata(spi);
  378. struct driver_data *drv_data =
  379. spi_controller_get_devdata(spi->controller);
  380. if (drv_data->ssp_type == CE4100_SSP) {
  381. pxa2xx_spi_write(drv_data, SSSR, chip->frm);
  382. return;
  383. }
  384. if (chip->cs_control) {
  385. chip->cs_control(PXA2XX_CS_ASSERT);
  386. return;
  387. }
  388. if (chip->gpiod_cs) {
  389. gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
  390. return;
  391. }
  392. if (is_lpss_ssp(drv_data))
  393. lpss_ssp_cs_control(spi, true);
  394. }
  395. static void cs_deassert(struct spi_device *spi)
  396. {
  397. struct chip_data *chip = spi_get_ctldata(spi);
  398. struct driver_data *drv_data =
  399. spi_controller_get_devdata(spi->controller);
  400. unsigned long timeout;
  401. if (drv_data->ssp_type == CE4100_SSP)
  402. return;
  403. /* Wait until SSP becomes idle before deasserting the CS */
  404. timeout = jiffies + msecs_to_jiffies(10);
  405. while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
  406. !time_after(jiffies, timeout))
  407. cpu_relax();
  408. if (chip->cs_control) {
  409. chip->cs_control(PXA2XX_CS_DEASSERT);
  410. return;
  411. }
  412. if (chip->gpiod_cs) {
  413. gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
  414. return;
  415. }
  416. if (is_lpss_ssp(drv_data))
  417. lpss_ssp_cs_control(spi, false);
  418. }
  419. static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
  420. {
  421. if (level)
  422. cs_deassert(spi);
  423. else
  424. cs_assert(spi);
  425. }
  426. int pxa2xx_spi_flush(struct driver_data *drv_data)
  427. {
  428. unsigned long limit = loops_per_jiffy << 1;
  429. do {
  430. while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
  431. pxa2xx_spi_read(drv_data, SSDR);
  432. } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
  433. write_SSSR_CS(drv_data, SSSR_ROR);
  434. return limit;
  435. }
  436. static void pxa2xx_spi_off(struct driver_data *drv_data)
  437. {
  438. /* On MMP, disabling SSE seems to corrupt the Rx FIFO */
  439. if (is_mmp2_ssp(drv_data))
  440. return;
  441. pxa2xx_spi_write(drv_data, SSCR0,
  442. pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
  443. }
  444. static int null_writer(struct driver_data *drv_data)
  445. {
  446. u8 n_bytes = drv_data->n_bytes;
  447. if (pxa2xx_spi_txfifo_full(drv_data)
  448. || (drv_data->tx == drv_data->tx_end))
  449. return 0;
  450. pxa2xx_spi_write(drv_data, SSDR, 0);
  451. drv_data->tx += n_bytes;
  452. return 1;
  453. }
  454. static int null_reader(struct driver_data *drv_data)
  455. {
  456. u8 n_bytes = drv_data->n_bytes;
  457. while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
  458. && (drv_data->rx < drv_data->rx_end)) {
  459. pxa2xx_spi_read(drv_data, SSDR);
  460. drv_data->rx += n_bytes;
  461. }
  462. return drv_data->rx == drv_data->rx_end;
  463. }
  464. static int u8_writer(struct driver_data *drv_data)
  465. {
  466. if (pxa2xx_spi_txfifo_full(drv_data)
  467. || (drv_data->tx == drv_data->tx_end))
  468. return 0;
  469. pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
  470. ++drv_data->tx;
  471. return 1;
  472. }
  473. static int u8_reader(struct driver_data *drv_data)
  474. {
  475. while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
  476. && (drv_data->rx < drv_data->rx_end)) {
  477. *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
  478. ++drv_data->rx;
  479. }
  480. return drv_data->rx == drv_data->rx_end;
  481. }
  482. static int u16_writer(struct driver_data *drv_data)
  483. {
  484. if (pxa2xx_spi_txfifo_full(drv_data)
  485. || (drv_data->tx == drv_data->tx_end))
  486. return 0;
  487. pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
  488. drv_data->tx += 2;
  489. return 1;
  490. }
  491. static int u16_reader(struct driver_data *drv_data)
  492. {
  493. while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
  494. && (drv_data->rx < drv_data->rx_end)) {
  495. *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
  496. drv_data->rx += 2;
  497. }
  498. return drv_data->rx == drv_data->rx_end;
  499. }
  500. static int u32_writer(struct driver_data *drv_data)
  501. {
  502. if (pxa2xx_spi_txfifo_full(drv_data)
  503. || (drv_data->tx == drv_data->tx_end))
  504. return 0;
  505. pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
  506. drv_data->tx += 4;
  507. return 1;
  508. }
  509. static int u32_reader(struct driver_data *drv_data)
  510. {
  511. while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
  512. && (drv_data->rx < drv_data->rx_end)) {
  513. *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
  514. drv_data->rx += 4;
  515. }
  516. return drv_data->rx == drv_data->rx_end;
  517. }
  518. static void reset_sccr1(struct driver_data *drv_data)
  519. {
  520. struct chip_data *chip =
  521. spi_get_ctldata(drv_data->controller->cur_msg->spi);
  522. u32 sccr1_reg;
  523. sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
  524. switch (drv_data->ssp_type) {
  525. case QUARK_X1000_SSP:
  526. sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
  527. break;
  528. case CE4100_SSP:
  529. sccr1_reg &= ~CE4100_SSCR1_RFT;
  530. break;
  531. default:
  532. sccr1_reg &= ~SSCR1_RFT;
  533. break;
  534. }
  535. sccr1_reg |= chip->threshold;
  536. pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
  537. }
  538. static void int_error_stop(struct driver_data *drv_data, const char* msg)
  539. {
  540. /* Stop and reset SSP */
  541. write_SSSR_CS(drv_data, drv_data->clear_sr);
  542. reset_sccr1(drv_data);
  543. if (!pxa25x_ssp_comp(drv_data))
  544. pxa2xx_spi_write(drv_data, SSTO, 0);
  545. pxa2xx_spi_flush(drv_data);
  546. pxa2xx_spi_off(drv_data);
  547. dev_err(&drv_data->pdev->dev, "%s\n", msg);
  548. drv_data->controller->cur_msg->status = -EIO;
  549. spi_finalize_current_transfer(drv_data->controller);
  550. }
  551. static void int_transfer_complete(struct driver_data *drv_data)
  552. {
  553. /* Clear and disable interrupts */
  554. write_SSSR_CS(drv_data, drv_data->clear_sr);
  555. reset_sccr1(drv_data);
  556. if (!pxa25x_ssp_comp(drv_data))
  557. pxa2xx_spi_write(drv_data, SSTO, 0);
  558. spi_finalize_current_transfer(drv_data->controller);
  559. }
  560. static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
  561. {
  562. u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
  563. drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
  564. u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
  565. if (irq_status & SSSR_ROR) {
  566. int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
  567. return IRQ_HANDLED;
  568. }
  569. if (irq_status & SSSR_TUR) {
  570. int_error_stop(drv_data, "interrupt_transfer: fifo underrun");
  571. return IRQ_HANDLED;
  572. }
  573. if (irq_status & SSSR_TINT) {
  574. pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
  575. if (drv_data->read(drv_data)) {
  576. int_transfer_complete(drv_data);
  577. return IRQ_HANDLED;
  578. }
  579. }
  580. /* Drain rx fifo, Fill tx fifo and prevent overruns */
  581. do {
  582. if (drv_data->read(drv_data)) {
  583. int_transfer_complete(drv_data);
  584. return IRQ_HANDLED;
  585. }
  586. } while (drv_data->write(drv_data));
  587. if (drv_data->read(drv_data)) {
  588. int_transfer_complete(drv_data);
  589. return IRQ_HANDLED;
  590. }
  591. if (drv_data->tx == drv_data->tx_end) {
  592. u32 bytes_left;
  593. u32 sccr1_reg;
  594. sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
  595. sccr1_reg &= ~SSCR1_TIE;
  596. /*
  597. * PXA25x_SSP has no timeout, set up rx threshould for the
  598. * remaining RX bytes.
  599. */
  600. if (pxa25x_ssp_comp(drv_data)) {
  601. u32 rx_thre;
  602. pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
  603. bytes_left = drv_data->rx_end - drv_data->rx;
  604. switch (drv_data->n_bytes) {
  605. case 4:
  606. bytes_left >>= 2;
  607. break;
  608. case 2:
  609. bytes_left >>= 1;
  610. break;
  611. }
  612. rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
  613. if (rx_thre > bytes_left)
  614. rx_thre = bytes_left;
  615. pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
  616. }
  617. pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
  618. }
  619. /* We did something */
  620. return IRQ_HANDLED;
  621. }
  622. static void handle_bad_msg(struct driver_data *drv_data)
  623. {
  624. pxa2xx_spi_off(drv_data);
  625. pxa2xx_spi_write(drv_data, SSCR1,
  626. pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
  627. if (!pxa25x_ssp_comp(drv_data))
  628. pxa2xx_spi_write(drv_data, SSTO, 0);
  629. write_SSSR_CS(drv_data, drv_data->clear_sr);
  630. dev_err(&drv_data->pdev->dev,
  631. "bad message state in interrupt handler\n");
  632. }
  633. static irqreturn_t ssp_int(int irq, void *dev_id)
  634. {
  635. struct driver_data *drv_data = dev_id;
  636. u32 sccr1_reg;
  637. u32 mask = drv_data->mask_sr;
  638. u32 status;
  639. /*
  640. * The IRQ might be shared with other peripherals so we must first
  641. * check that are we RPM suspended or not. If we are we assume that
  642. * the IRQ was not for us (we shouldn't be RPM suspended when the
  643. * interrupt is enabled).
  644. */
  645. if (pm_runtime_suspended(&drv_data->pdev->dev))
  646. return IRQ_NONE;
  647. /*
  648. * If the device is not yet in RPM suspended state and we get an
  649. * interrupt that is meant for another device, check if status bits
  650. * are all set to one. That means that the device is already
  651. * powered off.
  652. */
  653. status = pxa2xx_spi_read(drv_data, SSSR);
  654. if (status == ~0)
  655. return IRQ_NONE;
  656. sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
  657. /* Ignore possible writes if we don't need to write */
  658. if (!(sccr1_reg & SSCR1_TIE))
  659. mask &= ~SSSR_TFS;
  660. /* Ignore RX timeout interrupt if it is disabled */
  661. if (!(sccr1_reg & SSCR1_TINTE))
  662. mask &= ~SSSR_TINT;
  663. if (!(status & mask))
  664. return IRQ_NONE;
  665. pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
  666. pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
  667. if (!drv_data->controller->cur_msg) {
  668. handle_bad_msg(drv_data);
  669. /* Never fail */
  670. return IRQ_HANDLED;
  671. }
  672. return drv_data->transfer_handler(drv_data);
  673. }
  674. /*
  675. * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
  676. * input frequency by fractions of 2^24. It also has a divider by 5.
  677. *
  678. * There are formulas to get baud rate value for given input frequency and
  679. * divider parameters, such as DDS_CLK_RATE and SCR:
  680. *
  681. * Fsys = 200MHz
  682. *
  683. * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
  684. * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
  685. *
  686. * DDS_CLK_RATE either 2^n or 2^n / 5.
  687. * SCR is in range 0 .. 255
  688. *
  689. * Divisor = 5^i * 2^j * 2 * k
  690. * i = [0, 1] i = 1 iff j = 0 or j > 3
  691. * j = [0, 23] j = 0 iff i = 1
  692. * k = [1, 256]
  693. * Special case: j = 0, i = 1: Divisor = 2 / 5
  694. *
  695. * Accordingly to the specification the recommended values for DDS_CLK_RATE
  696. * are:
  697. * Case 1: 2^n, n = [0, 23]
  698. * Case 2: 2^24 * 2 / 5 (0x666666)
  699. * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
  700. *
  701. * In all cases the lowest possible value is better.
  702. *
  703. * The function calculates parameters for all cases and chooses the one closest
  704. * to the asked baud rate.
  705. */
  706. static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
  707. {
  708. unsigned long xtal = 200000000;
  709. unsigned long fref = xtal / 2; /* mandatory division by 2,
  710. see (2) */
  711. /* case 3 */
  712. unsigned long fref1 = fref / 2; /* case 1 */
  713. unsigned long fref2 = fref * 2 / 5; /* case 2 */
  714. unsigned long scale;
  715. unsigned long q, q1, q2;
  716. long r, r1, r2;
  717. u32 mul;
  718. /* Case 1 */
  719. /* Set initial value for DDS_CLK_RATE */
  720. mul = (1 << 24) >> 1;
  721. /* Calculate initial quot */
  722. q1 = DIV_ROUND_UP(fref1, rate);
  723. /* Scale q1 if it's too big */
  724. if (q1 > 256) {
  725. /* Scale q1 to range [1, 512] */
  726. scale = fls_long(q1 - 1);
  727. if (scale > 9) {
  728. q1 >>= scale - 9;
  729. mul >>= scale - 9;
  730. }
  731. /* Round the result if we have a remainder */
  732. q1 += q1 & 1;
  733. }
  734. /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
  735. scale = __ffs(q1);
  736. q1 >>= scale;
  737. mul >>= scale;
  738. /* Get the remainder */
  739. r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
  740. /* Case 2 */
  741. q2 = DIV_ROUND_UP(fref2, rate);
  742. r2 = abs(fref2 / q2 - rate);
  743. /*
  744. * Choose the best between two: less remainder we have the better. We
  745. * can't go case 2 if q2 is greater than 256 since SCR register can
  746. * hold only values 0 .. 255.
  747. */
  748. if (r2 >= r1 || q2 > 256) {
  749. /* case 1 is better */
  750. r = r1;
  751. q = q1;
  752. } else {
  753. /* case 2 is better */
  754. r = r2;
  755. q = q2;
  756. mul = (1 << 24) * 2 / 5;
  757. }
  758. /* Check case 3 only if the divisor is big enough */
  759. if (fref / rate >= 80) {
  760. u64 fssp;
  761. u32 m;
  762. /* Calculate initial quot */
  763. q1 = DIV_ROUND_UP(fref, rate);
  764. m = (1 << 24) / q1;
  765. /* Get the remainder */
  766. fssp = (u64)fref * m;
  767. do_div(fssp, 1 << 24);
  768. r1 = abs(fssp - rate);
  769. /* Choose this one if it suits better */
  770. if (r1 < r) {
  771. /* case 3 is better */
  772. q = 1;
  773. mul = m;
  774. }
  775. }
  776. *dds = mul;
  777. return q - 1;
  778. }
  779. static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
  780. {
  781. unsigned long ssp_clk = drv_data->controller->max_speed_hz;
  782. const struct ssp_device *ssp = drv_data->ssp;
  783. rate = min_t(int, ssp_clk, rate);
  784. /*
  785. * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
  786. * that the SSP transmission rate can be greater than the device rate
  787. */
  788. if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
  789. return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
  790. else
  791. return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff;
  792. }
  793. static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
  794. int rate)
  795. {
  796. struct chip_data *chip =
  797. spi_get_ctldata(drv_data->controller->cur_msg->spi);
  798. unsigned int clk_div;
  799. switch (drv_data->ssp_type) {
  800. case QUARK_X1000_SSP:
  801. clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
  802. break;
  803. default:
  804. clk_div = ssp_get_clk_div(drv_data, rate);
  805. break;
  806. }
  807. return clk_div << 8;
  808. }
  809. static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
  810. struct spi_device *spi,
  811. struct spi_transfer *xfer)
  812. {
  813. struct chip_data *chip = spi_get_ctldata(spi);
  814. return chip->enable_dma &&
  815. xfer->len <= MAX_DMA_LEN &&
  816. xfer->len >= chip->dma_burst_size;
  817. }
  818. static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
  819. struct spi_device *spi,
  820. struct spi_transfer *transfer)
  821. {
  822. struct driver_data *drv_data = spi_controller_get_devdata(controller);
  823. struct spi_message *message = controller->cur_msg;
  824. struct chip_data *chip = spi_get_ctldata(spi);
  825. u32 dma_thresh = chip->dma_threshold;
  826. u32 dma_burst = chip->dma_burst_size;
  827. u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
  828. u32 clk_div;
  829. u8 bits;
  830. u32 speed;
  831. u32 cr0;
  832. u32 cr1;
  833. int err;
  834. int dma_mapped;
  835. /* Check if we can DMA this transfer */
  836. if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
  837. /* reject already-mapped transfers; PIO won't always work */
  838. if (message->is_dma_mapped
  839. || transfer->rx_dma || transfer->tx_dma) {
  840. dev_err(&spi->dev,
  841. "Mapped transfer length of %u is greater than %d\n",
  842. transfer->len, MAX_DMA_LEN);
  843. return -EINVAL;
  844. }
  845. /* warn ... we force this to PIO mode */
  846. dev_warn_ratelimited(&spi->dev,
  847. "DMA disabled for transfer length %ld greater than %d\n",
  848. (long)transfer->len, MAX_DMA_LEN);
  849. }
  850. /* Setup the transfer state based on the type of transfer */
  851. if (pxa2xx_spi_flush(drv_data) == 0) {
  852. dev_err(&spi->dev, "Flush failed\n");
  853. return -EIO;
  854. }
  855. drv_data->n_bytes = chip->n_bytes;
  856. drv_data->tx = (void *)transfer->tx_buf;
  857. drv_data->tx_end = drv_data->tx + transfer->len;
  858. drv_data->rx = transfer->rx_buf;
  859. drv_data->rx_end = drv_data->rx + transfer->len;
  860. drv_data->write = drv_data->tx ? chip->write : null_writer;
  861. drv_data->read = drv_data->rx ? chip->read : null_reader;
  862. /* Change speed and bit per word on a per transfer */
  863. bits = transfer->bits_per_word;
  864. speed = transfer->speed_hz;
  865. clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
  866. if (bits <= 8) {
  867. drv_data->n_bytes = 1;
  868. drv_data->read = drv_data->read != null_reader ?
  869. u8_reader : null_reader;
  870. drv_data->write = drv_data->write != null_writer ?
  871. u8_writer : null_writer;
  872. } else if (bits <= 16) {
  873. drv_data->n_bytes = 2;
  874. drv_data->read = drv_data->read != null_reader ?
  875. u16_reader : null_reader;
  876. drv_data->write = drv_data->write != null_writer ?
  877. u16_writer : null_writer;
  878. } else if (bits <= 32) {
  879. drv_data->n_bytes = 4;
  880. drv_data->read = drv_data->read != null_reader ?
  881. u32_reader : null_reader;
  882. drv_data->write = drv_data->write != null_writer ?
  883. u32_writer : null_writer;
  884. }
  885. /*
  886. * if bits/word is changed in dma mode, then must check the
  887. * thresholds and burst also
  888. */
  889. if (chip->enable_dma) {
  890. if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
  891. spi,
  892. bits, &dma_burst,
  893. &dma_thresh))
  894. dev_warn_ratelimited(&spi->dev,
  895. "DMA burst size reduced to match bits_per_word\n");
  896. }
  897. dma_mapped = controller->can_dma &&
  898. controller->can_dma(controller, spi, transfer) &&
  899. controller->cur_msg_mapped;
  900. if (dma_mapped) {
  901. /* Ensure we have the correct interrupt handler */
  902. drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
  903. err = pxa2xx_spi_dma_prepare(drv_data, transfer);
  904. if (err)
  905. return err;
  906. /* Clear status and start DMA engine */
  907. cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
  908. pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
  909. pxa2xx_spi_dma_start(drv_data);
  910. } else {
  911. /* Ensure we have the correct interrupt handler */
  912. drv_data->transfer_handler = interrupt_transfer;
  913. /* Clear status */
  914. cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
  915. write_SSSR_CS(drv_data, drv_data->clear_sr);
  916. }
  917. /* NOTE: PXA25x_SSP _could_ use external clocking ... */
  918. cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
  919. if (!pxa25x_ssp_comp(drv_data))
  920. dev_dbg(&spi->dev, "%u Hz actual, %s\n",
  921. controller->max_speed_hz
  922. / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
  923. dma_mapped ? "DMA" : "PIO");
  924. else
  925. dev_dbg(&spi->dev, "%u Hz actual, %s\n",
  926. controller->max_speed_hz / 2
  927. / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
  928. dma_mapped ? "DMA" : "PIO");
  929. if (is_lpss_ssp(drv_data)) {
  930. if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
  931. != chip->lpss_rx_threshold)
  932. pxa2xx_spi_write(drv_data, SSIRF,
  933. chip->lpss_rx_threshold);
  934. if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
  935. != chip->lpss_tx_threshold)
  936. pxa2xx_spi_write(drv_data, SSITF,
  937. chip->lpss_tx_threshold);
  938. }
  939. if (is_quark_x1000_ssp(drv_data) &&
  940. (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
  941. pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
  942. /* see if we need to reload the config registers */
  943. if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
  944. || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
  945. != (cr1 & change_mask)) {
  946. /* stop the SSP, and update the other bits */
  947. if (!is_mmp2_ssp(drv_data))
  948. pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
  949. if (!pxa25x_ssp_comp(drv_data))
  950. pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
  951. /* first set CR1 without interrupt and service enables */
  952. pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
  953. /* restart the SSP */
  954. pxa2xx_spi_write(drv_data, SSCR0, cr0);
  955. } else {
  956. if (!pxa25x_ssp_comp(drv_data))
  957. pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
  958. }
  959. if (is_mmp2_ssp(drv_data)) {
  960. u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR)
  961. & SSSR_TFL_MASK) >> 8;
  962. if (tx_level) {
  963. /* On MMP2, flipping SSE doesn't to empty TXFIFO. */
  964. dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n",
  965. tx_level);
  966. if (tx_level > transfer->len)
  967. tx_level = transfer->len;
  968. drv_data->tx += tx_level;
  969. }
  970. }
  971. if (spi_controller_is_slave(controller)) {
  972. while (drv_data->write(drv_data))
  973. ;
  974. if (drv_data->gpiod_ready) {
  975. gpiod_set_value(drv_data->gpiod_ready, 1);
  976. udelay(1);
  977. gpiod_set_value(drv_data->gpiod_ready, 0);
  978. }
  979. }
  980. /*
  981. * Release the data by enabling service requests and interrupts,
  982. * without changing any mode bits
  983. */
  984. pxa2xx_spi_write(drv_data, SSCR1, cr1);
  985. return 1;
  986. }
  987. static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
  988. {
  989. struct driver_data *drv_data = spi_controller_get_devdata(controller);
  990. /* Stop and reset SSP */
  991. write_SSSR_CS(drv_data, drv_data->clear_sr);
  992. reset_sccr1(drv_data);
  993. if (!pxa25x_ssp_comp(drv_data))
  994. pxa2xx_spi_write(drv_data, SSTO, 0);
  995. pxa2xx_spi_flush(drv_data);
  996. pxa2xx_spi_off(drv_data);
  997. dev_dbg(&drv_data->pdev->dev, "transfer aborted\n");
  998. drv_data->controller->cur_msg->status = -EINTR;
  999. spi_finalize_current_transfer(drv_data->controller);
  1000. return 0;
  1001. }
  1002. static void pxa2xx_spi_handle_err(struct spi_controller *controller,
  1003. struct spi_message *msg)
  1004. {
  1005. struct driver_data *drv_data = spi_controller_get_devdata(controller);
  1006. /* Disable the SSP */
  1007. pxa2xx_spi_off(drv_data);
  1008. /* Clear and disable interrupts and service requests */
  1009. write_SSSR_CS(drv_data, drv_data->clear_sr);
  1010. pxa2xx_spi_write(drv_data, SSCR1,
  1011. pxa2xx_spi_read(drv_data, SSCR1)
  1012. & ~(drv_data->int_cr1 | drv_data->dma_cr1));
  1013. if (!pxa25x_ssp_comp(drv_data))
  1014. pxa2xx_spi_write(drv_data, SSTO, 0);
  1015. /*
  1016. * Stop the DMA if running. Note DMA callback handler may have unset
  1017. * the dma_running already, which is fine as stopping is not needed
  1018. * then but we shouldn't rely this flag for anything else than
  1019. * stopping. For instance to differentiate between PIO and DMA
  1020. * transfers.
  1021. */
  1022. if (atomic_read(&drv_data->dma_running))
  1023. pxa2xx_spi_dma_stop(drv_data);
  1024. }
  1025. static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
  1026. {
  1027. struct driver_data *drv_data = spi_controller_get_devdata(controller);
  1028. /* Disable the SSP now */
  1029. pxa2xx_spi_off(drv_data);
  1030. return 0;
  1031. }
  1032. static int setup_cs(struct spi_device *spi, struct chip_data *chip,
  1033. struct pxa2xx_spi_chip *chip_info)
  1034. {
  1035. struct driver_data *drv_data =
  1036. spi_controller_get_devdata(spi->controller);
  1037. struct gpio_desc *gpiod;
  1038. int err = 0;
  1039. if (chip == NULL)
  1040. return 0;
  1041. if (drv_data->cs_gpiods) {
  1042. gpiod = drv_data->cs_gpiods[spi->chip_select];
  1043. if (gpiod) {
  1044. chip->gpiod_cs = gpiod;
  1045. chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
  1046. gpiod_set_value(gpiod, chip->gpio_cs_inverted);
  1047. }
  1048. return 0;
  1049. }
  1050. if (chip_info == NULL)
  1051. return 0;
  1052. /* NOTE: setup() can be called multiple times, possibly with
  1053. * different chip_info, release previously requested GPIO
  1054. */
  1055. if (chip->gpiod_cs) {
  1056. gpiod_put(chip->gpiod_cs);
  1057. chip->gpiod_cs = NULL;
  1058. }
  1059. /* If (*cs_control) is provided, ignore GPIO chip select */
  1060. if (chip_info->cs_control) {
  1061. chip->cs_control = chip_info->cs_control;
  1062. return 0;
  1063. }
  1064. if (gpio_is_valid(chip_info->gpio_cs)) {
  1065. err = gpio_request(chip_info->gpio_cs, "SPI_CS");
  1066. if (err) {
  1067. dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
  1068. chip_info->gpio_cs);
  1069. return err;
  1070. }
  1071. gpiod = gpio_to_desc(chip_info->gpio_cs);
  1072. chip->gpiod_cs = gpiod;
  1073. chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
  1074. err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
  1075. if (err)
  1076. gpiod_put(chip->gpiod_cs);
  1077. }
  1078. return err;
  1079. }
  1080. static int setup(struct spi_device *spi)
  1081. {
  1082. struct pxa2xx_spi_chip *chip_info;
  1083. struct chip_data *chip;
  1084. const struct lpss_config *config;
  1085. struct driver_data *drv_data =
  1086. spi_controller_get_devdata(spi->controller);
  1087. uint tx_thres, tx_hi_thres, rx_thres;
  1088. int err;
  1089. switch (drv_data->ssp_type) {
  1090. case QUARK_X1000_SSP:
  1091. tx_thres = TX_THRESH_QUARK_X1000_DFLT;
  1092. tx_hi_thres = 0;
  1093. rx_thres = RX_THRESH_QUARK_X1000_DFLT;
  1094. break;
  1095. case CE4100_SSP:
  1096. tx_thres = TX_THRESH_CE4100_DFLT;
  1097. tx_hi_thres = 0;
  1098. rx_thres = RX_THRESH_CE4100_DFLT;
  1099. break;
  1100. case LPSS_LPT_SSP:
  1101. case LPSS_BYT_SSP:
  1102. case LPSS_BSW_SSP:
  1103. case LPSS_SPT_SSP:
  1104. case LPSS_BXT_SSP:
  1105. case LPSS_CNL_SSP:
  1106. config = lpss_get_config(drv_data);
  1107. tx_thres = config->tx_threshold_lo;
  1108. tx_hi_thres = config->tx_threshold_hi;
  1109. rx_thres = config->rx_threshold;
  1110. break;
  1111. default:
  1112. tx_hi_thres = 0;
  1113. if (spi_controller_is_slave(drv_data->controller)) {
  1114. tx_thres = 1;
  1115. rx_thres = 2;
  1116. } else {
  1117. tx_thres = TX_THRESH_DFLT;
  1118. rx_thres = RX_THRESH_DFLT;
  1119. }
  1120. break;
  1121. }
  1122. /* Only alloc on first setup */
  1123. chip = spi_get_ctldata(spi);
  1124. if (!chip) {
  1125. chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
  1126. if (!chip)
  1127. return -ENOMEM;
  1128. if (drv_data->ssp_type == CE4100_SSP) {
  1129. if (spi->chip_select > 4) {
  1130. dev_err(&spi->dev,
  1131. "failed setup: cs number must not be > 4.\n");
  1132. kfree(chip);
  1133. return -EINVAL;
  1134. }
  1135. chip->frm = spi->chip_select;
  1136. }
  1137. chip->enable_dma = drv_data->controller_info->enable_dma;
  1138. chip->timeout = TIMOUT_DFLT;
  1139. }
  1140. /* protocol drivers may change the chip settings, so...
  1141. * if chip_info exists, use it */
  1142. chip_info = spi->controller_data;
  1143. /* chip_info isn't always needed */
  1144. chip->cr1 = 0;
  1145. if (chip_info) {
  1146. if (chip_info->timeout)
  1147. chip->timeout = chip_info->timeout;
  1148. if (chip_info->tx_threshold)
  1149. tx_thres = chip_info->tx_threshold;
  1150. if (chip_info->tx_hi_threshold)
  1151. tx_hi_thres = chip_info->tx_hi_threshold;
  1152. if (chip_info->rx_threshold)
  1153. rx_thres = chip_info->rx_threshold;
  1154. chip->dma_threshold = 0;
  1155. if (chip_info->enable_loopback)
  1156. chip->cr1 = SSCR1_LBM;
  1157. }
  1158. if (spi_controller_is_slave(drv_data->controller)) {
  1159. chip->cr1 |= SSCR1_SCFR;
  1160. chip->cr1 |= SSCR1_SCLKDIR;
  1161. chip->cr1 |= SSCR1_SFRMDIR;
  1162. chip->cr1 |= SSCR1_SPH;
  1163. }
  1164. chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
  1165. chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
  1166. | SSITF_TxHiThresh(tx_hi_thres);
  1167. /* set dma burst and threshold outside of chip_info path so that if
  1168. * chip_info goes away after setting chip->enable_dma, the
  1169. * burst and threshold can still respond to changes in bits_per_word */
  1170. if (chip->enable_dma) {
  1171. /* set up legal burst and threshold for dma */
  1172. if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
  1173. spi->bits_per_word,
  1174. &chip->dma_burst_size,
  1175. &chip->dma_threshold)) {
  1176. dev_warn(&spi->dev,
  1177. "in setup: DMA burst size reduced to match bits_per_word\n");
  1178. }
  1179. dev_dbg(&spi->dev,
  1180. "in setup: DMA burst size set to %u\n",
  1181. chip->dma_burst_size);
  1182. }
  1183. switch (drv_data->ssp_type) {
  1184. case QUARK_X1000_SSP:
  1185. chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
  1186. & QUARK_X1000_SSCR1_RFT)
  1187. | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
  1188. & QUARK_X1000_SSCR1_TFT);
  1189. break;
  1190. case CE4100_SSP:
  1191. chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
  1192. (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
  1193. break;
  1194. default:
  1195. chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
  1196. (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
  1197. break;
  1198. }
  1199. chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
  1200. chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
  1201. | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
  1202. if (spi->mode & SPI_LOOP)
  1203. chip->cr1 |= SSCR1_LBM;
  1204. if (spi->bits_per_word <= 8) {
  1205. chip->n_bytes = 1;
  1206. chip->read = u8_reader;
  1207. chip->write = u8_writer;
  1208. } else if (spi->bits_per_word <= 16) {
  1209. chip->n_bytes = 2;
  1210. chip->read = u16_reader;
  1211. chip->write = u16_writer;
  1212. } else if (spi->bits_per_word <= 32) {
  1213. chip->n_bytes = 4;
  1214. chip->read = u32_reader;
  1215. chip->write = u32_writer;
  1216. }
  1217. spi_set_ctldata(spi, chip);
  1218. if (drv_data->ssp_type == CE4100_SSP)
  1219. return 0;
  1220. err = setup_cs(spi, chip, chip_info);
  1221. if (err)
  1222. kfree(chip);
  1223. return err;
  1224. }
  1225. static void cleanup(struct spi_device *spi)
  1226. {
  1227. struct chip_data *chip = spi_get_ctldata(spi);
  1228. struct driver_data *drv_data =
  1229. spi_controller_get_devdata(spi->controller);
  1230. if (!chip)
  1231. return;
  1232. if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
  1233. chip->gpiod_cs)
  1234. gpiod_put(chip->gpiod_cs);
  1235. kfree(chip);
  1236. }
  1237. #ifdef CONFIG_ACPI
  1238. static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
  1239. { "INT33C0", LPSS_LPT_SSP },
  1240. { "INT33C1", LPSS_LPT_SSP },
  1241. { "INT3430", LPSS_LPT_SSP },
  1242. { "INT3431", LPSS_LPT_SSP },
  1243. { "80860F0E", LPSS_BYT_SSP },
  1244. { "8086228E", LPSS_BSW_SSP },
  1245. { },
  1246. };
  1247. MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
  1248. #endif
  1249. /*
  1250. * PCI IDs of compound devices that integrate both host controller and private
  1251. * integrated DMA engine. Please note these are not used in module
  1252. * autoloading and probing in this module but matching the LPSS SSP type.
  1253. */
  1254. static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
  1255. /* SPT-LP */
  1256. { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
  1257. { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
  1258. /* SPT-H */
  1259. { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
  1260. { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
  1261. /* KBL-H */
  1262. { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
  1263. { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
  1264. /* CML-V */
  1265. { PCI_VDEVICE(INTEL, 0xa3a9), LPSS_SPT_SSP },
  1266. { PCI_VDEVICE(INTEL, 0xa3aa), LPSS_SPT_SSP },
  1267. /* BXT A-Step */
  1268. { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
  1269. { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
  1270. { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
  1271. /* BXT B-Step */
  1272. { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
  1273. { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
  1274. { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
  1275. /* GLK */
  1276. { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
  1277. { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
  1278. { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
  1279. /* ICL-LP */
  1280. { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
  1281. { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
  1282. { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
  1283. /* EHL */
  1284. { PCI_VDEVICE(INTEL, 0x4b2a), LPSS_BXT_SSP },
  1285. { PCI_VDEVICE(INTEL, 0x4b2b), LPSS_BXT_SSP },
  1286. { PCI_VDEVICE(INTEL, 0x4b37), LPSS_BXT_SSP },
  1287. /* JSL */
  1288. { PCI_VDEVICE(INTEL, 0x4daa), LPSS_CNL_SSP },
  1289. { PCI_VDEVICE(INTEL, 0x4dab), LPSS_CNL_SSP },
  1290. { PCI_VDEVICE(INTEL, 0x4dfb), LPSS_CNL_SSP },
  1291. /* TGL-H */
  1292. { PCI_VDEVICE(INTEL, 0x43aa), LPSS_CNL_SSP },
  1293. { PCI_VDEVICE(INTEL, 0x43ab), LPSS_CNL_SSP },
  1294. { PCI_VDEVICE(INTEL, 0x43fb), LPSS_CNL_SSP },
  1295. { PCI_VDEVICE(INTEL, 0x43fd), LPSS_CNL_SSP },
  1296. /* APL */
  1297. { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
  1298. { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
  1299. { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
  1300. /* CNL-LP */
  1301. { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
  1302. { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
  1303. { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
  1304. /* CNL-H */
  1305. { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
  1306. { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
  1307. { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
  1308. /* CML-LP */
  1309. { PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP },
  1310. { PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP },
  1311. { PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP },
  1312. /* CML-H */
  1313. { PCI_VDEVICE(INTEL, 0x06aa), LPSS_CNL_SSP },
  1314. { PCI_VDEVICE(INTEL, 0x06ab), LPSS_CNL_SSP },
  1315. { PCI_VDEVICE(INTEL, 0x06fb), LPSS_CNL_SSP },
  1316. /* TGL-LP */
  1317. { PCI_VDEVICE(INTEL, 0xa0aa), LPSS_CNL_SSP },
  1318. { PCI_VDEVICE(INTEL, 0xa0ab), LPSS_CNL_SSP },
  1319. { PCI_VDEVICE(INTEL, 0xa0de), LPSS_CNL_SSP },
  1320. { PCI_VDEVICE(INTEL, 0xa0df), LPSS_CNL_SSP },
  1321. { PCI_VDEVICE(INTEL, 0xa0fb), LPSS_CNL_SSP },
  1322. { PCI_VDEVICE(INTEL, 0xa0fd), LPSS_CNL_SSP },
  1323. { PCI_VDEVICE(INTEL, 0xa0fe), LPSS_CNL_SSP },
  1324. { },
  1325. };
  1326. static const struct of_device_id pxa2xx_spi_of_match[] = {
  1327. { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
  1328. {},
  1329. };
  1330. MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
  1331. #ifdef CONFIG_ACPI
  1332. static int pxa2xx_spi_get_port_id(struct device *dev)
  1333. {
  1334. struct acpi_device *adev;
  1335. unsigned int devid;
  1336. int port_id = -1;
  1337. adev = ACPI_COMPANION(dev);
  1338. if (adev && adev->pnp.unique_id &&
  1339. !kstrtouint(adev->pnp.unique_id, 0, &devid))
  1340. port_id = devid;
  1341. return port_id;
  1342. }
  1343. #else /* !CONFIG_ACPI */
  1344. static int pxa2xx_spi_get_port_id(struct device *dev)
  1345. {
  1346. return -1;
  1347. }
  1348. #endif /* CONFIG_ACPI */
  1349. #ifdef CONFIG_PCI
  1350. static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
  1351. {
  1352. return param == chan->device->dev;
  1353. }
  1354. #endif /* CONFIG_PCI */
  1355. static struct pxa2xx_spi_controller *
  1356. pxa2xx_spi_init_pdata(struct platform_device *pdev)
  1357. {
  1358. struct pxa2xx_spi_controller *pdata;
  1359. struct ssp_device *ssp;
  1360. struct resource *res;
  1361. struct device *parent = pdev->dev.parent;
  1362. struct pci_dev *pcidev = dev_is_pci(parent) ? to_pci_dev(parent) : NULL;
  1363. const struct pci_device_id *pcidev_id = NULL;
  1364. enum pxa_ssp_type type;
  1365. const void *match;
  1366. if (pcidev)
  1367. pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, pcidev);
  1368. match = device_get_match_data(&pdev->dev);
  1369. if (match)
  1370. type = (enum pxa_ssp_type)match;
  1371. else if (pcidev_id)
  1372. type = (enum pxa_ssp_type)pcidev_id->driver_data;
  1373. else
  1374. return ERR_PTR(-EINVAL);
  1375. pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
  1376. if (!pdata)
  1377. return ERR_PTR(-ENOMEM);
  1378. ssp = &pdata->ssp;
  1379. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1380. ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
  1381. if (IS_ERR(ssp->mmio_base))
  1382. return ERR_CAST(ssp->mmio_base);
  1383. ssp->phys_base = res->start;
  1384. #ifdef CONFIG_PCI
  1385. if (pcidev_id) {
  1386. pdata->tx_param = parent;
  1387. pdata->rx_param = parent;
  1388. pdata->dma_filter = pxa2xx_spi_idma_filter;
  1389. }
  1390. #endif
  1391. ssp->clk = devm_clk_get(&pdev->dev, NULL);
  1392. if (IS_ERR(ssp->clk))
  1393. return ERR_CAST(ssp->clk);
  1394. ssp->irq = platform_get_irq(pdev, 0);
  1395. if (ssp->irq < 0)
  1396. return ERR_PTR(ssp->irq);
  1397. ssp->type = type;
  1398. ssp->dev = &pdev->dev;
  1399. ssp->port_id = pxa2xx_spi_get_port_id(&pdev->dev);
  1400. pdata->is_slave = device_property_read_bool(&pdev->dev, "spi-slave");
  1401. pdata->num_chipselect = 1;
  1402. pdata->enable_dma = true;
  1403. pdata->dma_burst_size = 1;
  1404. return pdata;
  1405. }
  1406. static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
  1407. unsigned int cs)
  1408. {
  1409. struct driver_data *drv_data = spi_controller_get_devdata(controller);
  1410. if (has_acpi_companion(&drv_data->pdev->dev)) {
  1411. switch (drv_data->ssp_type) {
  1412. /*
  1413. * For Atoms the ACPI DeviceSelection used by the Windows
  1414. * driver starts from 1 instead of 0 so translate it here
  1415. * to match what Linux expects.
  1416. */
  1417. case LPSS_BYT_SSP:
  1418. case LPSS_BSW_SSP:
  1419. return cs - 1;
  1420. default:
  1421. break;
  1422. }
  1423. }
  1424. return cs;
  1425. }
  1426. static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
  1427. {
  1428. return MAX_DMA_LEN;
  1429. }
  1430. static int pxa2xx_spi_probe(struct platform_device *pdev)
  1431. {
  1432. struct device *dev = &pdev->dev;
  1433. struct pxa2xx_spi_controller *platform_info;
  1434. struct spi_controller *controller;
  1435. struct driver_data *drv_data;
  1436. struct ssp_device *ssp;
  1437. const struct lpss_config *config;
  1438. int status, count;
  1439. u32 tmp;
  1440. platform_info = dev_get_platdata(dev);
  1441. if (!platform_info) {
  1442. platform_info = pxa2xx_spi_init_pdata(pdev);
  1443. if (IS_ERR(platform_info)) {
  1444. dev_err(&pdev->dev, "missing platform data\n");
  1445. return PTR_ERR(platform_info);
  1446. }
  1447. }
  1448. ssp = pxa_ssp_request(pdev->id, pdev->name);
  1449. if (!ssp)
  1450. ssp = &platform_info->ssp;
  1451. if (!ssp->mmio_base) {
  1452. dev_err(&pdev->dev, "failed to get ssp\n");
  1453. return -ENODEV;
  1454. }
  1455. if (platform_info->is_slave)
  1456. controller = devm_spi_alloc_slave(dev, sizeof(*drv_data));
  1457. else
  1458. controller = devm_spi_alloc_master(dev, sizeof(*drv_data));
  1459. if (!controller) {
  1460. dev_err(&pdev->dev, "cannot alloc spi_controller\n");
  1461. pxa_ssp_free(ssp);
  1462. return -ENOMEM;
  1463. }
  1464. drv_data = spi_controller_get_devdata(controller);
  1465. drv_data->controller = controller;
  1466. drv_data->controller_info = platform_info;
  1467. drv_data->pdev = pdev;
  1468. drv_data->ssp = ssp;
  1469. controller->dev.of_node = pdev->dev.of_node;
  1470. /* the spi->mode bits understood by this driver: */
  1471. controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
  1472. controller->bus_num = ssp->port_id;
  1473. controller->dma_alignment = DMA_ALIGNMENT;
  1474. controller->cleanup = cleanup;
  1475. controller->setup = setup;
  1476. controller->set_cs = pxa2xx_spi_set_cs;
  1477. controller->transfer_one = pxa2xx_spi_transfer_one;
  1478. controller->slave_abort = pxa2xx_spi_slave_abort;
  1479. controller->handle_err = pxa2xx_spi_handle_err;
  1480. controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
  1481. controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
  1482. controller->auto_runtime_pm = true;
  1483. controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
  1484. drv_data->ssp_type = ssp->type;
  1485. drv_data->ioaddr = ssp->mmio_base;
  1486. drv_data->ssdr_physical = ssp->phys_base + SSDR;
  1487. if (pxa25x_ssp_comp(drv_data)) {
  1488. switch (drv_data->ssp_type) {
  1489. case QUARK_X1000_SSP:
  1490. controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
  1491. break;
  1492. default:
  1493. controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
  1494. break;
  1495. }
  1496. drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
  1497. drv_data->dma_cr1 = 0;
  1498. drv_data->clear_sr = SSSR_ROR;
  1499. drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
  1500. } else {
  1501. controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
  1502. drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
  1503. drv_data->dma_cr1 = DEFAULT_DMA_CR1;
  1504. drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
  1505. drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
  1506. | SSSR_ROR | SSSR_TUR;
  1507. }
  1508. status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
  1509. drv_data);
  1510. if (status < 0) {
  1511. dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
  1512. goto out_error_controller_alloc;
  1513. }
  1514. /* Setup DMA if requested */
  1515. if (platform_info->enable_dma) {
  1516. status = pxa2xx_spi_dma_setup(drv_data);
  1517. if (status) {
  1518. dev_warn(dev, "no DMA channels available, using PIO\n");
  1519. platform_info->enable_dma = false;
  1520. } else {
  1521. controller->can_dma = pxa2xx_spi_can_dma;
  1522. controller->max_dma_len = MAX_DMA_LEN;
  1523. controller->max_transfer_size =
  1524. pxa2xx_spi_max_dma_transfer_size;
  1525. }
  1526. }
  1527. /* Enable SOC clock */
  1528. status = clk_prepare_enable(ssp->clk);
  1529. if (status)
  1530. goto out_error_dma_irq_alloc;
  1531. controller->max_speed_hz = clk_get_rate(ssp->clk);
  1532. /*
  1533. * Set minimum speed for all other platforms than Intel Quark which is
  1534. * able do under 1 Hz transfers.
  1535. */
  1536. if (!pxa25x_ssp_comp(drv_data))
  1537. controller->min_speed_hz =
  1538. DIV_ROUND_UP(controller->max_speed_hz, 4096);
  1539. else if (!is_quark_x1000_ssp(drv_data))
  1540. controller->min_speed_hz =
  1541. DIV_ROUND_UP(controller->max_speed_hz, 512);
  1542. /* Load default SSP configuration */
  1543. pxa2xx_spi_write(drv_data, SSCR0, 0);
  1544. switch (drv_data->ssp_type) {
  1545. case QUARK_X1000_SSP:
  1546. tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
  1547. QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
  1548. pxa2xx_spi_write(drv_data, SSCR1, tmp);
  1549. /* using the Motorola SPI protocol and use 8 bit frame */
  1550. tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
  1551. pxa2xx_spi_write(drv_data, SSCR0, tmp);
  1552. break;
  1553. case CE4100_SSP:
  1554. tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
  1555. CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
  1556. pxa2xx_spi_write(drv_data, SSCR1, tmp);
  1557. tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
  1558. pxa2xx_spi_write(drv_data, SSCR0, tmp);
  1559. break;
  1560. default:
  1561. if (spi_controller_is_slave(controller)) {
  1562. tmp = SSCR1_SCFR |
  1563. SSCR1_SCLKDIR |
  1564. SSCR1_SFRMDIR |
  1565. SSCR1_RxTresh(2) |
  1566. SSCR1_TxTresh(1) |
  1567. SSCR1_SPH;
  1568. } else {
  1569. tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
  1570. SSCR1_TxTresh(TX_THRESH_DFLT);
  1571. }
  1572. pxa2xx_spi_write(drv_data, SSCR1, tmp);
  1573. tmp = SSCR0_Motorola | SSCR0_DataSize(8);
  1574. if (!spi_controller_is_slave(controller))
  1575. tmp |= SSCR0_SCR(2);
  1576. pxa2xx_spi_write(drv_data, SSCR0, tmp);
  1577. break;
  1578. }
  1579. if (!pxa25x_ssp_comp(drv_data))
  1580. pxa2xx_spi_write(drv_data, SSTO, 0);
  1581. if (!is_quark_x1000_ssp(drv_data))
  1582. pxa2xx_spi_write(drv_data, SSPSP, 0);
  1583. if (is_lpss_ssp(drv_data)) {
  1584. lpss_ssp_setup(drv_data);
  1585. config = lpss_get_config(drv_data);
  1586. if (config->reg_capabilities >= 0) {
  1587. tmp = __lpss_ssp_read_priv(drv_data,
  1588. config->reg_capabilities);
  1589. tmp &= LPSS_CAPS_CS_EN_MASK;
  1590. tmp >>= LPSS_CAPS_CS_EN_SHIFT;
  1591. platform_info->num_chipselect = ffz(tmp);
  1592. } else if (config->cs_num) {
  1593. platform_info->num_chipselect = config->cs_num;
  1594. }
  1595. }
  1596. controller->num_chipselect = platform_info->num_chipselect;
  1597. count = gpiod_count(&pdev->dev, "cs");
  1598. if (count > 0) {
  1599. int i;
  1600. controller->num_chipselect = max_t(int, count,
  1601. controller->num_chipselect);
  1602. drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
  1603. controller->num_chipselect, sizeof(struct gpio_desc *),
  1604. GFP_KERNEL);
  1605. if (!drv_data->cs_gpiods) {
  1606. status = -ENOMEM;
  1607. goto out_error_clock_enabled;
  1608. }
  1609. for (i = 0; i < controller->num_chipselect; i++) {
  1610. struct gpio_desc *gpiod;
  1611. gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
  1612. if (IS_ERR(gpiod)) {
  1613. /* Means use native chip select */
  1614. if (PTR_ERR(gpiod) == -ENOENT)
  1615. continue;
  1616. status = PTR_ERR(gpiod);
  1617. goto out_error_clock_enabled;
  1618. } else {
  1619. drv_data->cs_gpiods[i] = gpiod;
  1620. }
  1621. }
  1622. }
  1623. if (platform_info->is_slave) {
  1624. drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
  1625. "ready", GPIOD_OUT_LOW);
  1626. if (IS_ERR(drv_data->gpiod_ready)) {
  1627. status = PTR_ERR(drv_data->gpiod_ready);
  1628. goto out_error_clock_enabled;
  1629. }
  1630. }
  1631. pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
  1632. pm_runtime_use_autosuspend(&pdev->dev);
  1633. pm_runtime_set_active(&pdev->dev);
  1634. pm_runtime_enable(&pdev->dev);
  1635. /* Register with the SPI framework */
  1636. platform_set_drvdata(pdev, drv_data);
  1637. status = spi_register_controller(controller);
  1638. if (status != 0) {
  1639. dev_err(&pdev->dev, "problem registering spi controller\n");
  1640. goto out_error_pm_runtime_enabled;
  1641. }
  1642. return status;
  1643. out_error_pm_runtime_enabled:
  1644. pm_runtime_disable(&pdev->dev);
  1645. out_error_clock_enabled:
  1646. clk_disable_unprepare(ssp->clk);
  1647. out_error_dma_irq_alloc:
  1648. pxa2xx_spi_dma_release(drv_data);
  1649. free_irq(ssp->irq, drv_data);
  1650. out_error_controller_alloc:
  1651. pxa_ssp_free(ssp);
  1652. return status;
  1653. }
  1654. static int pxa2xx_spi_remove(struct platform_device *pdev)
  1655. {
  1656. struct driver_data *drv_data = platform_get_drvdata(pdev);
  1657. struct ssp_device *ssp = drv_data->ssp;
  1658. pm_runtime_get_sync(&pdev->dev);
  1659. spi_unregister_controller(drv_data->controller);
  1660. /* Disable the SSP at the peripheral and SOC level */
  1661. pxa2xx_spi_write(drv_data, SSCR0, 0);
  1662. clk_disable_unprepare(ssp->clk);
  1663. /* Release DMA */
  1664. if (drv_data->controller_info->enable_dma)
  1665. pxa2xx_spi_dma_release(drv_data);
  1666. pm_runtime_put_noidle(&pdev->dev);
  1667. pm_runtime_disable(&pdev->dev);
  1668. /* Release IRQ */
  1669. free_irq(ssp->irq, drv_data);
  1670. /* Release SSP */
  1671. pxa_ssp_free(ssp);
  1672. return 0;
  1673. }
  1674. #ifdef CONFIG_PM_SLEEP
  1675. static int pxa2xx_spi_suspend(struct device *dev)
  1676. {
  1677. struct driver_data *drv_data = dev_get_drvdata(dev);
  1678. struct ssp_device *ssp = drv_data->ssp;
  1679. int status;
  1680. status = spi_controller_suspend(drv_data->controller);
  1681. if (status != 0)
  1682. return status;
  1683. pxa2xx_spi_write(drv_data, SSCR0, 0);
  1684. if (!pm_runtime_suspended(dev))
  1685. clk_disable_unprepare(ssp->clk);
  1686. return 0;
  1687. }
  1688. static int pxa2xx_spi_resume(struct device *dev)
  1689. {
  1690. struct driver_data *drv_data = dev_get_drvdata(dev);
  1691. struct ssp_device *ssp = drv_data->ssp;
  1692. int status;
  1693. /* Enable the SSP clock */
  1694. if (!pm_runtime_suspended(dev)) {
  1695. status = clk_prepare_enable(ssp->clk);
  1696. if (status)
  1697. return status;
  1698. }
  1699. /* Start the queue running */
  1700. return spi_controller_resume(drv_data->controller);
  1701. }
  1702. #endif
  1703. #ifdef CONFIG_PM
  1704. static int pxa2xx_spi_runtime_suspend(struct device *dev)
  1705. {
  1706. struct driver_data *drv_data = dev_get_drvdata(dev);
  1707. clk_disable_unprepare(drv_data->ssp->clk);
  1708. return 0;
  1709. }
  1710. static int pxa2xx_spi_runtime_resume(struct device *dev)
  1711. {
  1712. struct driver_data *drv_data = dev_get_drvdata(dev);
  1713. int status;
  1714. status = clk_prepare_enable(drv_data->ssp->clk);
  1715. return status;
  1716. }
  1717. #endif
  1718. static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
  1719. SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
  1720. SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
  1721. pxa2xx_spi_runtime_resume, NULL)
  1722. };
  1723. static struct platform_driver driver = {
  1724. .driver = {
  1725. .name = "pxa2xx-spi",
  1726. .pm = &pxa2xx_spi_pm_ops,
  1727. .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
  1728. .of_match_table = of_match_ptr(pxa2xx_spi_of_match),
  1729. },
  1730. .probe = pxa2xx_spi_probe,
  1731. .remove = pxa2xx_spi_remove,
  1732. };
  1733. static int __init pxa2xx_spi_init(void)
  1734. {
  1735. return platform_driver_register(&driver);
  1736. }
  1737. subsys_initcall(pxa2xx_spi_init);
  1738. static void __exit pxa2xx_spi_exit(void)
  1739. {
  1740. platform_driver_unregister(&driver);
  1741. }
  1742. module_exit(pxa2xx_spi_exit);
  1743. MODULE_SOFTDEP("pre: dw_dmac");