spi-pxa2xx-dma.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * PXA2xx SPI DMA engine support.
  4. *
  5. * Copyright (C) 2013, Intel Corporation
  6. * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
  7. */
  8. #include <linux/device.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/dmaengine.h>
  11. #include <linux/pxa2xx_ssp.h>
  12. #include <linux/scatterlist.h>
  13. #include <linux/sizes.h>
  14. #include <linux/spi/spi.h>
  15. #include <linux/spi/pxa2xx_spi.h>
  16. #include "spi-pxa2xx.h"
  17. static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
  18. bool error)
  19. {
  20. struct spi_message *msg = drv_data->controller->cur_msg;
  21. /*
  22. * It is possible that one CPU is handling ROR interrupt and other
  23. * just gets DMA completion. Calling pump_transfers() twice for the
  24. * same transfer leads to problems thus we prevent concurrent calls
  25. * by using ->dma_running.
  26. */
  27. if (atomic_dec_and_test(&drv_data->dma_running)) {
  28. /*
  29. * If the other CPU is still handling the ROR interrupt we
  30. * might not know about the error yet. So we re-check the
  31. * ROR bit here before we clear the status register.
  32. */
  33. if (!error) {
  34. u32 status = pxa2xx_spi_read(drv_data, SSSR)
  35. & drv_data->mask_sr;
  36. error = status & SSSR_ROR;
  37. }
  38. /* Clear status & disable interrupts */
  39. pxa2xx_spi_write(drv_data, SSCR1,
  40. pxa2xx_spi_read(drv_data, SSCR1)
  41. & ~drv_data->dma_cr1);
  42. write_SSSR_CS(drv_data, drv_data->clear_sr);
  43. if (!pxa25x_ssp_comp(drv_data))
  44. pxa2xx_spi_write(drv_data, SSTO, 0);
  45. if (error) {
  46. /* In case we got an error we disable the SSP now */
  47. pxa2xx_spi_write(drv_data, SSCR0,
  48. pxa2xx_spi_read(drv_data, SSCR0)
  49. & ~SSCR0_SSE);
  50. msg->status = -EIO;
  51. }
  52. spi_finalize_current_transfer(drv_data->controller);
  53. }
  54. }
  55. static void pxa2xx_spi_dma_callback(void *data)
  56. {
  57. pxa2xx_spi_dma_transfer_complete(data, false);
  58. }
  59. static struct dma_async_tx_descriptor *
  60. pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
  61. enum dma_transfer_direction dir,
  62. struct spi_transfer *xfer)
  63. {
  64. struct chip_data *chip =
  65. spi_get_ctldata(drv_data->controller->cur_msg->spi);
  66. enum dma_slave_buswidth width;
  67. struct dma_slave_config cfg;
  68. struct dma_chan *chan;
  69. struct sg_table *sgt;
  70. int ret;
  71. switch (drv_data->n_bytes) {
  72. case 1:
  73. width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  74. break;
  75. case 2:
  76. width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  77. break;
  78. default:
  79. width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  80. break;
  81. }
  82. memset(&cfg, 0, sizeof(cfg));
  83. cfg.direction = dir;
  84. if (dir == DMA_MEM_TO_DEV) {
  85. cfg.dst_addr = drv_data->ssdr_physical;
  86. cfg.dst_addr_width = width;
  87. cfg.dst_maxburst = chip->dma_burst_size;
  88. sgt = &xfer->tx_sg;
  89. chan = drv_data->controller->dma_tx;
  90. } else {
  91. cfg.src_addr = drv_data->ssdr_physical;
  92. cfg.src_addr_width = width;
  93. cfg.src_maxburst = chip->dma_burst_size;
  94. sgt = &xfer->rx_sg;
  95. chan = drv_data->controller->dma_rx;
  96. }
  97. ret = dmaengine_slave_config(chan, &cfg);
  98. if (ret) {
  99. dev_warn(&drv_data->pdev->dev, "DMA slave config failed\n");
  100. return NULL;
  101. }
  102. return dmaengine_prep_slave_sg(chan, sgt->sgl, sgt->nents, dir,
  103. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  104. }
  105. irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
  106. {
  107. u32 status;
  108. status = pxa2xx_spi_read(drv_data, SSSR) & drv_data->mask_sr;
  109. if (status & SSSR_ROR) {
  110. dev_err(&drv_data->pdev->dev, "FIFO overrun\n");
  111. dmaengine_terminate_async(drv_data->controller->dma_rx);
  112. dmaengine_terminate_async(drv_data->controller->dma_tx);
  113. pxa2xx_spi_dma_transfer_complete(drv_data, true);
  114. return IRQ_HANDLED;
  115. }
  116. return IRQ_NONE;
  117. }
  118. int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
  119. struct spi_transfer *xfer)
  120. {
  121. struct dma_async_tx_descriptor *tx_desc, *rx_desc;
  122. int err;
  123. tx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_MEM_TO_DEV, xfer);
  124. if (!tx_desc) {
  125. dev_err(&drv_data->pdev->dev,
  126. "failed to get DMA TX descriptor\n");
  127. err = -EBUSY;
  128. goto err_tx;
  129. }
  130. rx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_DEV_TO_MEM, xfer);
  131. if (!rx_desc) {
  132. dev_err(&drv_data->pdev->dev,
  133. "failed to get DMA RX descriptor\n");
  134. err = -EBUSY;
  135. goto err_rx;
  136. }
  137. /* We are ready when RX completes */
  138. rx_desc->callback = pxa2xx_spi_dma_callback;
  139. rx_desc->callback_param = drv_data;
  140. dmaengine_submit(rx_desc);
  141. dmaengine_submit(tx_desc);
  142. return 0;
  143. err_rx:
  144. dmaengine_terminate_async(drv_data->controller->dma_tx);
  145. err_tx:
  146. return err;
  147. }
  148. void pxa2xx_spi_dma_start(struct driver_data *drv_data)
  149. {
  150. dma_async_issue_pending(drv_data->controller->dma_rx);
  151. dma_async_issue_pending(drv_data->controller->dma_tx);
  152. atomic_set(&drv_data->dma_running, 1);
  153. }
  154. void pxa2xx_spi_dma_stop(struct driver_data *drv_data)
  155. {
  156. atomic_set(&drv_data->dma_running, 0);
  157. dmaengine_terminate_sync(drv_data->controller->dma_rx);
  158. dmaengine_terminate_sync(drv_data->controller->dma_tx);
  159. }
  160. int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
  161. {
  162. struct pxa2xx_spi_controller *pdata = drv_data->controller_info;
  163. struct device *dev = &drv_data->pdev->dev;
  164. struct spi_controller *controller = drv_data->controller;
  165. dma_cap_mask_t mask;
  166. dma_cap_zero(mask);
  167. dma_cap_set(DMA_SLAVE, mask);
  168. controller->dma_tx = dma_request_slave_channel_compat(mask,
  169. pdata->dma_filter, pdata->tx_param, dev, "tx");
  170. if (!controller->dma_tx)
  171. return -ENODEV;
  172. controller->dma_rx = dma_request_slave_channel_compat(mask,
  173. pdata->dma_filter, pdata->rx_param, dev, "rx");
  174. if (!controller->dma_rx) {
  175. dma_release_channel(controller->dma_tx);
  176. controller->dma_tx = NULL;
  177. return -ENODEV;
  178. }
  179. return 0;
  180. }
  181. void pxa2xx_spi_dma_release(struct driver_data *drv_data)
  182. {
  183. struct spi_controller *controller = drv_data->controller;
  184. if (controller->dma_rx) {
  185. dmaengine_terminate_sync(controller->dma_rx);
  186. dma_release_channel(controller->dma_rx);
  187. controller->dma_rx = NULL;
  188. }
  189. if (controller->dma_tx) {
  190. dmaengine_terminate_sync(controller->dma_tx);
  191. dma_release_channel(controller->dma_tx);
  192. controller->dma_tx = NULL;
  193. }
  194. }
  195. int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
  196. struct spi_device *spi,
  197. u8 bits_per_word, u32 *burst_code,
  198. u32 *threshold)
  199. {
  200. struct pxa2xx_spi_chip *chip_info = spi->controller_data;
  201. struct driver_data *drv_data = spi_controller_get_devdata(spi->controller);
  202. u32 dma_burst_size = drv_data->controller_info->dma_burst_size;
  203. /*
  204. * If the DMA burst size is given in chip_info we use that,
  205. * otherwise we use the default. Also we use the default FIFO
  206. * thresholds for now.
  207. */
  208. *burst_code = chip_info ? chip_info->dma_burst_size : dma_burst_size;
  209. *threshold = SSCR1_RxTresh(RX_THRESH_DFLT)
  210. | SSCR1_TxTresh(TX_THRESH_DFLT);
  211. return 0;
  212. }