spi-pl022.c 69 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
  4. *
  5. * Copyright (C) 2008-2012 ST-Ericsson AB
  6. * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
  7. *
  8. * Author: Linus Walleij <linus.walleij@stericsson.com>
  9. *
  10. * Initial version inspired by:
  11. * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
  12. * Initial adoption to PL022 by:
  13. * Sachin Verma <sachin.verma@st.com>
  14. */
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <linux/device.h>
  18. #include <linux/ioport.h>
  19. #include <linux/errno.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/spi/spi.h>
  22. #include <linux/delay.h>
  23. #include <linux/clk.h>
  24. #include <linux/err.h>
  25. #include <linux/amba/bus.h>
  26. #include <linux/amba/pl022.h>
  27. #include <linux/io.h>
  28. #include <linux/slab.h>
  29. #include <linux/dmaengine.h>
  30. #include <linux/dma-mapping.h>
  31. #include <linux/scatterlist.h>
  32. #include <linux/pm_runtime.h>
  33. #include <linux/gpio.h>
  34. #include <linux/of_gpio.h>
  35. #include <linux/pinctrl/consumer.h>
  36. /*
  37. * This macro is used to define some register default values.
  38. * reg is masked with mask, the OR:ed with an (again masked)
  39. * val shifted sb steps to the left.
  40. */
  41. #define SSP_WRITE_BITS(reg, val, mask, sb) \
  42. ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
  43. /*
  44. * This macro is also used to define some default values.
  45. * It will just shift val by sb steps to the left and mask
  46. * the result with mask.
  47. */
  48. #define GEN_MASK_BITS(val, mask, sb) \
  49. (((val)<<(sb)) & (mask))
  50. #define DRIVE_TX 0
  51. #define DO_NOT_DRIVE_TX 1
  52. #define DO_NOT_QUEUE_DMA 0
  53. #define QUEUE_DMA 1
  54. #define RX_TRANSFER 1
  55. #define TX_TRANSFER 2
  56. /*
  57. * Macros to access SSP Registers with their offsets
  58. */
  59. #define SSP_CR0(r) (r + 0x000)
  60. #define SSP_CR1(r) (r + 0x004)
  61. #define SSP_DR(r) (r + 0x008)
  62. #define SSP_SR(r) (r + 0x00C)
  63. #define SSP_CPSR(r) (r + 0x010)
  64. #define SSP_IMSC(r) (r + 0x014)
  65. #define SSP_RIS(r) (r + 0x018)
  66. #define SSP_MIS(r) (r + 0x01C)
  67. #define SSP_ICR(r) (r + 0x020)
  68. #define SSP_DMACR(r) (r + 0x024)
  69. #define SSP_CSR(r) (r + 0x030) /* vendor extension */
  70. #define SSP_ITCR(r) (r + 0x080)
  71. #define SSP_ITIP(r) (r + 0x084)
  72. #define SSP_ITOP(r) (r + 0x088)
  73. #define SSP_TDR(r) (r + 0x08C)
  74. #define SSP_PID0(r) (r + 0xFE0)
  75. #define SSP_PID1(r) (r + 0xFE4)
  76. #define SSP_PID2(r) (r + 0xFE8)
  77. #define SSP_PID3(r) (r + 0xFEC)
  78. #define SSP_CID0(r) (r + 0xFF0)
  79. #define SSP_CID1(r) (r + 0xFF4)
  80. #define SSP_CID2(r) (r + 0xFF8)
  81. #define SSP_CID3(r) (r + 0xFFC)
  82. /*
  83. * SSP Control Register 0 - SSP_CR0
  84. */
  85. #define SSP_CR0_MASK_DSS (0x0FUL << 0)
  86. #define SSP_CR0_MASK_FRF (0x3UL << 4)
  87. #define SSP_CR0_MASK_SPO (0x1UL << 6)
  88. #define SSP_CR0_MASK_SPH (0x1UL << 7)
  89. #define SSP_CR0_MASK_SCR (0xFFUL << 8)
  90. /*
  91. * The ST version of this block moves som bits
  92. * in SSP_CR0 and extends it to 32 bits
  93. */
  94. #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
  95. #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
  96. #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
  97. #define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
  98. /*
  99. * SSP Control Register 0 - SSP_CR1
  100. */
  101. #define SSP_CR1_MASK_LBM (0x1UL << 0)
  102. #define SSP_CR1_MASK_SSE (0x1UL << 1)
  103. #define SSP_CR1_MASK_MS (0x1UL << 2)
  104. #define SSP_CR1_MASK_SOD (0x1UL << 3)
  105. /*
  106. * The ST version of this block adds some bits
  107. * in SSP_CR1
  108. */
  109. #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
  110. #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
  111. #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
  112. #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
  113. #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
  114. /* This one is only in the PL023 variant */
  115. #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
  116. /*
  117. * SSP Status Register - SSP_SR
  118. */
  119. #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
  120. #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
  121. #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
  122. #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
  123. #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
  124. /*
  125. * SSP Clock Prescale Register - SSP_CPSR
  126. */
  127. #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
  128. /*
  129. * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
  130. */
  131. #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
  132. #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
  133. #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
  134. #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
  135. /*
  136. * SSP Raw Interrupt Status Register - SSP_RIS
  137. */
  138. /* Receive Overrun Raw Interrupt status */
  139. #define SSP_RIS_MASK_RORRIS (0x1UL << 0)
  140. /* Receive Timeout Raw Interrupt status */
  141. #define SSP_RIS_MASK_RTRIS (0x1UL << 1)
  142. /* Receive FIFO Raw Interrupt status */
  143. #define SSP_RIS_MASK_RXRIS (0x1UL << 2)
  144. /* Transmit FIFO Raw Interrupt status */
  145. #define SSP_RIS_MASK_TXRIS (0x1UL << 3)
  146. /*
  147. * SSP Masked Interrupt Status Register - SSP_MIS
  148. */
  149. /* Receive Overrun Masked Interrupt status */
  150. #define SSP_MIS_MASK_RORMIS (0x1UL << 0)
  151. /* Receive Timeout Masked Interrupt status */
  152. #define SSP_MIS_MASK_RTMIS (0x1UL << 1)
  153. /* Receive FIFO Masked Interrupt status */
  154. #define SSP_MIS_MASK_RXMIS (0x1UL << 2)
  155. /* Transmit FIFO Masked Interrupt status */
  156. #define SSP_MIS_MASK_TXMIS (0x1UL << 3)
  157. /*
  158. * SSP Interrupt Clear Register - SSP_ICR
  159. */
  160. /* Receive Overrun Raw Clear Interrupt bit */
  161. #define SSP_ICR_MASK_RORIC (0x1UL << 0)
  162. /* Receive Timeout Clear Interrupt bit */
  163. #define SSP_ICR_MASK_RTIC (0x1UL << 1)
  164. /*
  165. * SSP DMA Control Register - SSP_DMACR
  166. */
  167. /* Receive DMA Enable bit */
  168. #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
  169. /* Transmit DMA Enable bit */
  170. #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
  171. /*
  172. * SSP Chip Select Control Register - SSP_CSR
  173. * (vendor extension)
  174. */
  175. #define SSP_CSR_CSVALUE_MASK (0x1FUL << 0)
  176. /*
  177. * SSP Integration Test control Register - SSP_ITCR
  178. */
  179. #define SSP_ITCR_MASK_ITEN (0x1UL << 0)
  180. #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
  181. /*
  182. * SSP Integration Test Input Register - SSP_ITIP
  183. */
  184. #define ITIP_MASK_SSPRXD (0x1UL << 0)
  185. #define ITIP_MASK_SSPFSSIN (0x1UL << 1)
  186. #define ITIP_MASK_SSPCLKIN (0x1UL << 2)
  187. #define ITIP_MASK_RXDMAC (0x1UL << 3)
  188. #define ITIP_MASK_TXDMAC (0x1UL << 4)
  189. #define ITIP_MASK_SSPTXDIN (0x1UL << 5)
  190. /*
  191. * SSP Integration Test output Register - SSP_ITOP
  192. */
  193. #define ITOP_MASK_SSPTXD (0x1UL << 0)
  194. #define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
  195. #define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
  196. #define ITOP_MASK_SSPOEn (0x1UL << 3)
  197. #define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
  198. #define ITOP_MASK_RORINTR (0x1UL << 5)
  199. #define ITOP_MASK_RTINTR (0x1UL << 6)
  200. #define ITOP_MASK_RXINTR (0x1UL << 7)
  201. #define ITOP_MASK_TXINTR (0x1UL << 8)
  202. #define ITOP_MASK_INTR (0x1UL << 9)
  203. #define ITOP_MASK_RXDMABREQ (0x1UL << 10)
  204. #define ITOP_MASK_RXDMASREQ (0x1UL << 11)
  205. #define ITOP_MASK_TXDMABREQ (0x1UL << 12)
  206. #define ITOP_MASK_TXDMASREQ (0x1UL << 13)
  207. /*
  208. * SSP Test Data Register - SSP_TDR
  209. */
  210. #define TDR_MASK_TESTDATA (0xFFFFFFFF)
  211. /*
  212. * Message State
  213. * we use the spi_message.state (void *) pointer to
  214. * hold a single state value, that's why all this
  215. * (void *) casting is done here.
  216. */
  217. #define STATE_START ((void *) 0)
  218. #define STATE_RUNNING ((void *) 1)
  219. #define STATE_DONE ((void *) 2)
  220. #define STATE_ERROR ((void *) -1)
  221. #define STATE_TIMEOUT ((void *) -2)
  222. /*
  223. * SSP State - Whether Enabled or Disabled
  224. */
  225. #define SSP_DISABLED (0)
  226. #define SSP_ENABLED (1)
  227. /*
  228. * SSP DMA State - Whether DMA Enabled or Disabled
  229. */
  230. #define SSP_DMA_DISABLED (0)
  231. #define SSP_DMA_ENABLED (1)
  232. /*
  233. * SSP Clock Defaults
  234. */
  235. #define SSP_DEFAULT_CLKRATE 0x2
  236. #define SSP_DEFAULT_PRESCALE 0x40
  237. /*
  238. * SSP Clock Parameter ranges
  239. */
  240. #define CPSDVR_MIN 0x02
  241. #define CPSDVR_MAX 0xFE
  242. #define SCR_MIN 0x00
  243. #define SCR_MAX 0xFF
  244. /*
  245. * SSP Interrupt related Macros
  246. */
  247. #define DEFAULT_SSP_REG_IMSC 0x0UL
  248. #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
  249. #define ENABLE_ALL_INTERRUPTS ( \
  250. SSP_IMSC_MASK_RORIM | \
  251. SSP_IMSC_MASK_RTIM | \
  252. SSP_IMSC_MASK_RXIM | \
  253. SSP_IMSC_MASK_TXIM \
  254. )
  255. #define CLEAR_ALL_INTERRUPTS 0x3
  256. #define SPI_POLLING_TIMEOUT 1000
  257. /*
  258. * The type of reading going on on this chip
  259. */
  260. enum ssp_reading {
  261. READING_NULL,
  262. READING_U8,
  263. READING_U16,
  264. READING_U32
  265. };
  266. /*
  267. * The type of writing going on on this chip
  268. */
  269. enum ssp_writing {
  270. WRITING_NULL,
  271. WRITING_U8,
  272. WRITING_U16,
  273. WRITING_U32
  274. };
  275. /**
  276. * struct vendor_data - vendor-specific config parameters
  277. * for PL022 derivates
  278. * @fifodepth: depth of FIFOs (both)
  279. * @max_bpw: maximum number of bits per word
  280. * @unidir: supports unidirection transfers
  281. * @extended_cr: 32 bit wide control register 0 with extra
  282. * features and extra features in CR1 as found in the ST variants
  283. * @pl023: supports a subset of the ST extensions called "PL023"
  284. * @loopback: supports loopback mode
  285. * @internal_cs_ctrl: supports chip select control register
  286. */
  287. struct vendor_data {
  288. int fifodepth;
  289. int max_bpw;
  290. bool unidir;
  291. bool extended_cr;
  292. bool pl023;
  293. bool loopback;
  294. bool internal_cs_ctrl;
  295. };
  296. /**
  297. * struct pl022 - This is the private SSP driver data structure
  298. * @adev: AMBA device model hookup
  299. * @vendor: vendor data for the IP block
  300. * @phybase: the physical memory where the SSP device resides
  301. * @virtbase: the virtual memory where the SSP is mapped
  302. * @clk: outgoing clock "SPICLK" for the SPI bus
  303. * @master: SPI framework hookup
  304. * @master_info: controller-specific data from machine setup
  305. * @pump_transfers: Tasklet used in Interrupt Transfer mode
  306. * @cur_msg: Pointer to current spi_message being processed
  307. * @cur_transfer: Pointer to current spi_transfer
  308. * @cur_chip: pointer to current clients chip(assigned from controller_state)
  309. * @next_msg_cs_active: the next message in the queue has been examined
  310. * and it was found that it uses the same chip select as the previous
  311. * message, so we left it active after the previous transfer, and it's
  312. * active already.
  313. * @tx: current position in TX buffer to be read
  314. * @tx_end: end position in TX buffer to be read
  315. * @rx: current position in RX buffer to be written
  316. * @rx_end: end position in RX buffer to be written
  317. * @read: the type of read currently going on
  318. * @write: the type of write currently going on
  319. * @exp_fifo_level: expected FIFO level
  320. * @rx_lev_trig: receive FIFO watermark level which triggers IRQ
  321. * @tx_lev_trig: transmit FIFO watermark level which triggers IRQ
  322. * @dma_rx_channel: optional channel for RX DMA
  323. * @dma_tx_channel: optional channel for TX DMA
  324. * @sgt_rx: scattertable for the RX transfer
  325. * @sgt_tx: scattertable for the TX transfer
  326. * @dummypage: a dummy page used for driving data on the bus with DMA
  327. * @dma_running: indicates whether DMA is in operation
  328. * @cur_cs: current chip select (gpio)
  329. * @chipselects: list of chipselects (gpios)
  330. */
  331. struct pl022 {
  332. struct amba_device *adev;
  333. struct vendor_data *vendor;
  334. resource_size_t phybase;
  335. void __iomem *virtbase;
  336. struct clk *clk;
  337. struct spi_master *master;
  338. struct pl022_ssp_controller *master_info;
  339. /* Message per-transfer pump */
  340. struct tasklet_struct pump_transfers;
  341. struct spi_message *cur_msg;
  342. struct spi_transfer *cur_transfer;
  343. struct chip_data *cur_chip;
  344. bool next_msg_cs_active;
  345. void *tx;
  346. void *tx_end;
  347. void *rx;
  348. void *rx_end;
  349. enum ssp_reading read;
  350. enum ssp_writing write;
  351. u32 exp_fifo_level;
  352. enum ssp_rx_level_trig rx_lev_trig;
  353. enum ssp_tx_level_trig tx_lev_trig;
  354. /* DMA settings */
  355. #ifdef CONFIG_DMA_ENGINE
  356. struct dma_chan *dma_rx_channel;
  357. struct dma_chan *dma_tx_channel;
  358. struct sg_table sgt_rx;
  359. struct sg_table sgt_tx;
  360. char *dummypage;
  361. bool dma_running;
  362. #endif
  363. int cur_cs;
  364. int *chipselects;
  365. };
  366. /**
  367. * struct chip_data - To maintain runtime state of SSP for each client chip
  368. * @cr0: Value of control register CR0 of SSP - on later ST variants this
  369. * register is 32 bits wide rather than just 16
  370. * @cr1: Value of control register CR1 of SSP
  371. * @dmacr: Value of DMA control Register of SSP
  372. * @cpsr: Value of Clock prescale register
  373. * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
  374. * @enable_dma: Whether to enable DMA or not
  375. * @read: function ptr to be used to read when doing xfer for this chip
  376. * @write: function ptr to be used to write when doing xfer for this chip
  377. * @cs_control: chip select callback provided by chip
  378. * @xfer_type: polling/interrupt/DMA
  379. *
  380. * Runtime state of the SSP controller, maintained per chip,
  381. * This would be set according to the current message that would be served
  382. */
  383. struct chip_data {
  384. u32 cr0;
  385. u16 cr1;
  386. u16 dmacr;
  387. u16 cpsr;
  388. u8 n_bytes;
  389. bool enable_dma;
  390. enum ssp_reading read;
  391. enum ssp_writing write;
  392. void (*cs_control) (u32 command);
  393. int xfer_type;
  394. };
  395. /**
  396. * null_cs_control - Dummy chip select function
  397. * @command: select/delect the chip
  398. *
  399. * If no chip select function is provided by client this is used as dummy
  400. * chip select
  401. */
  402. static void null_cs_control(u32 command)
  403. {
  404. pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
  405. }
  406. /**
  407. * internal_cs_control - Control chip select signals via SSP_CSR.
  408. * @pl022: SSP driver private data structure
  409. * @command: select/delect the chip
  410. *
  411. * Used on controller with internal chip select control via SSP_CSR register
  412. * (vendor extension). Each of the 5 LSB in the register controls one chip
  413. * select signal.
  414. */
  415. static void internal_cs_control(struct pl022 *pl022, u32 command)
  416. {
  417. u32 tmp;
  418. tmp = readw(SSP_CSR(pl022->virtbase));
  419. if (command == SSP_CHIP_SELECT)
  420. tmp &= ~BIT(pl022->cur_cs);
  421. else
  422. tmp |= BIT(pl022->cur_cs);
  423. writew(tmp, SSP_CSR(pl022->virtbase));
  424. }
  425. static void pl022_cs_control(struct pl022 *pl022, u32 command)
  426. {
  427. if (pl022->vendor->internal_cs_ctrl)
  428. internal_cs_control(pl022, command);
  429. else if (gpio_is_valid(pl022->cur_cs))
  430. gpio_set_value(pl022->cur_cs, command);
  431. else
  432. pl022->cur_chip->cs_control(command);
  433. }
  434. /**
  435. * giveback - current spi_message is over, schedule next message and call
  436. * callback of this message. Assumes that caller already
  437. * set message->status; dma and pio irqs are blocked
  438. * @pl022: SSP driver private data structure
  439. */
  440. static void giveback(struct pl022 *pl022)
  441. {
  442. struct spi_transfer *last_transfer;
  443. pl022->next_msg_cs_active = false;
  444. last_transfer = list_last_entry(&pl022->cur_msg->transfers,
  445. struct spi_transfer, transfer_list);
  446. /* Delay if requested before any change in chip select */
  447. /*
  448. * FIXME: This runs in interrupt context.
  449. * Is this really smart?
  450. */
  451. spi_transfer_delay_exec(last_transfer);
  452. if (!last_transfer->cs_change) {
  453. struct spi_message *next_msg;
  454. /*
  455. * cs_change was not set. We can keep the chip select
  456. * enabled if there is message in the queue and it is
  457. * for the same spi device.
  458. *
  459. * We cannot postpone this until pump_messages, because
  460. * after calling msg->complete (below) the driver that
  461. * sent the current message could be unloaded, which
  462. * could invalidate the cs_control() callback...
  463. */
  464. /* get a pointer to the next message, if any */
  465. next_msg = spi_get_next_queued_message(pl022->master);
  466. /*
  467. * see if the next and current messages point
  468. * to the same spi device.
  469. */
  470. if (next_msg && next_msg->spi != pl022->cur_msg->spi)
  471. next_msg = NULL;
  472. if (!next_msg || pl022->cur_msg->state == STATE_ERROR)
  473. pl022_cs_control(pl022, SSP_CHIP_DESELECT);
  474. else
  475. pl022->next_msg_cs_active = true;
  476. }
  477. pl022->cur_msg = NULL;
  478. pl022->cur_transfer = NULL;
  479. pl022->cur_chip = NULL;
  480. /* disable the SPI/SSP operation */
  481. writew((readw(SSP_CR1(pl022->virtbase)) &
  482. (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
  483. spi_finalize_current_message(pl022->master);
  484. }
  485. /**
  486. * flush - flush the FIFO to reach a clean state
  487. * @pl022: SSP driver private data structure
  488. */
  489. static int flush(struct pl022 *pl022)
  490. {
  491. unsigned long limit = loops_per_jiffy << 1;
  492. dev_dbg(&pl022->adev->dev, "flush\n");
  493. do {
  494. while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
  495. readw(SSP_DR(pl022->virtbase));
  496. } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
  497. pl022->exp_fifo_level = 0;
  498. return limit;
  499. }
  500. /**
  501. * restore_state - Load configuration of current chip
  502. * @pl022: SSP driver private data structure
  503. */
  504. static void restore_state(struct pl022 *pl022)
  505. {
  506. struct chip_data *chip = pl022->cur_chip;
  507. if (pl022->vendor->extended_cr)
  508. writel(chip->cr0, SSP_CR0(pl022->virtbase));
  509. else
  510. writew(chip->cr0, SSP_CR0(pl022->virtbase));
  511. writew(chip->cr1, SSP_CR1(pl022->virtbase));
  512. writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
  513. writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
  514. writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
  515. writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
  516. }
  517. /*
  518. * Default SSP Register Values
  519. */
  520. #define DEFAULT_SSP_REG_CR0 ( \
  521. GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
  522. GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
  523. GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
  524. GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
  525. GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
  526. )
  527. /* ST versions have slightly different bit layout */
  528. #define DEFAULT_SSP_REG_CR0_ST ( \
  529. GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
  530. GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
  531. GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
  532. GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
  533. GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
  534. GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
  535. GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
  536. )
  537. /* The PL023 version is slightly different again */
  538. #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
  539. GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
  540. GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
  541. GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
  542. GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
  543. )
  544. #define DEFAULT_SSP_REG_CR1 ( \
  545. GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
  546. GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
  547. GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
  548. GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
  549. )
  550. /* ST versions extend this register to use all 16 bits */
  551. #define DEFAULT_SSP_REG_CR1_ST ( \
  552. DEFAULT_SSP_REG_CR1 | \
  553. GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
  554. GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
  555. GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
  556. GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
  557. GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
  558. )
  559. /*
  560. * The PL023 variant has further differences: no loopback mode, no microwire
  561. * support, and a new clock feedback delay setting.
  562. */
  563. #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
  564. GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
  565. GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
  566. GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
  567. GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
  568. GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
  569. GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
  570. GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
  571. GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
  572. )
  573. #define DEFAULT_SSP_REG_CPSR ( \
  574. GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
  575. )
  576. #define DEFAULT_SSP_REG_DMACR (\
  577. GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
  578. GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
  579. )
  580. /**
  581. * load_ssp_default_config - Load default configuration for SSP
  582. * @pl022: SSP driver private data structure
  583. */
  584. static void load_ssp_default_config(struct pl022 *pl022)
  585. {
  586. if (pl022->vendor->pl023) {
  587. writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
  588. writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
  589. } else if (pl022->vendor->extended_cr) {
  590. writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
  591. writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
  592. } else {
  593. writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
  594. writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
  595. }
  596. writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
  597. writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
  598. writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
  599. writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
  600. }
  601. /*
  602. * This will write to TX and read from RX according to the parameters
  603. * set in pl022.
  604. */
  605. static void readwriter(struct pl022 *pl022)
  606. {
  607. /*
  608. * The FIFO depth is different between primecell variants.
  609. * I believe filling in too much in the FIFO might cause
  610. * errons in 8bit wide transfers on ARM variants (just 8 words
  611. * FIFO, means only 8x8 = 64 bits in FIFO) at least.
  612. *
  613. * To prevent this issue, the TX FIFO is only filled to the
  614. * unused RX FIFO fill length, regardless of what the TX
  615. * FIFO status flag indicates.
  616. */
  617. dev_dbg(&pl022->adev->dev,
  618. "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
  619. __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
  620. /* Read as much as you can */
  621. while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
  622. && (pl022->rx < pl022->rx_end)) {
  623. switch (pl022->read) {
  624. case READING_NULL:
  625. readw(SSP_DR(pl022->virtbase));
  626. break;
  627. case READING_U8:
  628. *(u8 *) (pl022->rx) =
  629. readw(SSP_DR(pl022->virtbase)) & 0xFFU;
  630. break;
  631. case READING_U16:
  632. *(u16 *) (pl022->rx) =
  633. (u16) readw(SSP_DR(pl022->virtbase));
  634. break;
  635. case READING_U32:
  636. *(u32 *) (pl022->rx) =
  637. readl(SSP_DR(pl022->virtbase));
  638. break;
  639. }
  640. pl022->rx += (pl022->cur_chip->n_bytes);
  641. pl022->exp_fifo_level--;
  642. }
  643. /*
  644. * Write as much as possible up to the RX FIFO size
  645. */
  646. while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
  647. && (pl022->tx < pl022->tx_end)) {
  648. switch (pl022->write) {
  649. case WRITING_NULL:
  650. writew(0x0, SSP_DR(pl022->virtbase));
  651. break;
  652. case WRITING_U8:
  653. writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
  654. break;
  655. case WRITING_U16:
  656. writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
  657. break;
  658. case WRITING_U32:
  659. writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
  660. break;
  661. }
  662. pl022->tx += (pl022->cur_chip->n_bytes);
  663. pl022->exp_fifo_level++;
  664. /*
  665. * This inner reader takes care of things appearing in the RX
  666. * FIFO as we're transmitting. This will happen a lot since the
  667. * clock starts running when you put things into the TX FIFO,
  668. * and then things are continuously clocked into the RX FIFO.
  669. */
  670. while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
  671. && (pl022->rx < pl022->rx_end)) {
  672. switch (pl022->read) {
  673. case READING_NULL:
  674. readw(SSP_DR(pl022->virtbase));
  675. break;
  676. case READING_U8:
  677. *(u8 *) (pl022->rx) =
  678. readw(SSP_DR(pl022->virtbase)) & 0xFFU;
  679. break;
  680. case READING_U16:
  681. *(u16 *) (pl022->rx) =
  682. (u16) readw(SSP_DR(pl022->virtbase));
  683. break;
  684. case READING_U32:
  685. *(u32 *) (pl022->rx) =
  686. readl(SSP_DR(pl022->virtbase));
  687. break;
  688. }
  689. pl022->rx += (pl022->cur_chip->n_bytes);
  690. pl022->exp_fifo_level--;
  691. }
  692. }
  693. /*
  694. * When we exit here the TX FIFO should be full and the RX FIFO
  695. * should be empty
  696. */
  697. }
  698. /**
  699. * next_transfer - Move to the Next transfer in the current spi message
  700. * @pl022: SSP driver private data structure
  701. *
  702. * This function moves though the linked list of spi transfers in the
  703. * current spi message and returns with the state of current spi
  704. * message i.e whether its last transfer is done(STATE_DONE) or
  705. * Next transfer is ready(STATE_RUNNING)
  706. */
  707. static void *next_transfer(struct pl022 *pl022)
  708. {
  709. struct spi_message *msg = pl022->cur_msg;
  710. struct spi_transfer *trans = pl022->cur_transfer;
  711. /* Move to next transfer */
  712. if (trans->transfer_list.next != &msg->transfers) {
  713. pl022->cur_transfer =
  714. list_entry(trans->transfer_list.next,
  715. struct spi_transfer, transfer_list);
  716. return STATE_RUNNING;
  717. }
  718. return STATE_DONE;
  719. }
  720. /*
  721. * This DMA functionality is only compiled in if we have
  722. * access to the generic DMA devices/DMA engine.
  723. */
  724. #ifdef CONFIG_DMA_ENGINE
  725. static void unmap_free_dma_scatter(struct pl022 *pl022)
  726. {
  727. /* Unmap and free the SG tables */
  728. dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
  729. pl022->sgt_tx.nents, DMA_TO_DEVICE);
  730. dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
  731. pl022->sgt_rx.nents, DMA_FROM_DEVICE);
  732. sg_free_table(&pl022->sgt_rx);
  733. sg_free_table(&pl022->sgt_tx);
  734. }
  735. static void dma_callback(void *data)
  736. {
  737. struct pl022 *pl022 = data;
  738. struct spi_message *msg = pl022->cur_msg;
  739. BUG_ON(!pl022->sgt_rx.sgl);
  740. #ifdef VERBOSE_DEBUG
  741. /*
  742. * Optionally dump out buffers to inspect contents, this is
  743. * good if you want to convince yourself that the loopback
  744. * read/write contents are the same, when adopting to a new
  745. * DMA engine.
  746. */
  747. {
  748. struct scatterlist *sg;
  749. unsigned int i;
  750. dma_sync_sg_for_cpu(&pl022->adev->dev,
  751. pl022->sgt_rx.sgl,
  752. pl022->sgt_rx.nents,
  753. DMA_FROM_DEVICE);
  754. for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
  755. dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
  756. print_hex_dump(KERN_ERR, "SPI RX: ",
  757. DUMP_PREFIX_OFFSET,
  758. 16,
  759. 1,
  760. sg_virt(sg),
  761. sg_dma_len(sg),
  762. 1);
  763. }
  764. for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
  765. dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
  766. print_hex_dump(KERN_ERR, "SPI TX: ",
  767. DUMP_PREFIX_OFFSET,
  768. 16,
  769. 1,
  770. sg_virt(sg),
  771. sg_dma_len(sg),
  772. 1);
  773. }
  774. }
  775. #endif
  776. unmap_free_dma_scatter(pl022);
  777. /* Update total bytes transferred */
  778. msg->actual_length += pl022->cur_transfer->len;
  779. /* Move to next transfer */
  780. msg->state = next_transfer(pl022);
  781. if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change)
  782. pl022_cs_control(pl022, SSP_CHIP_DESELECT);
  783. tasklet_schedule(&pl022->pump_transfers);
  784. }
  785. static void setup_dma_scatter(struct pl022 *pl022,
  786. void *buffer,
  787. unsigned int length,
  788. struct sg_table *sgtab)
  789. {
  790. struct scatterlist *sg;
  791. int bytesleft = length;
  792. void *bufp = buffer;
  793. int mapbytes;
  794. int i;
  795. if (buffer) {
  796. for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
  797. /*
  798. * If there are less bytes left than what fits
  799. * in the current page (plus page alignment offset)
  800. * we just feed in this, else we stuff in as much
  801. * as we can.
  802. */
  803. if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
  804. mapbytes = bytesleft;
  805. else
  806. mapbytes = PAGE_SIZE - offset_in_page(bufp);
  807. sg_set_page(sg, virt_to_page(bufp),
  808. mapbytes, offset_in_page(bufp));
  809. bufp += mapbytes;
  810. bytesleft -= mapbytes;
  811. dev_dbg(&pl022->adev->dev,
  812. "set RX/TX target page @ %p, %d bytes, %d left\n",
  813. bufp, mapbytes, bytesleft);
  814. }
  815. } else {
  816. /* Map the dummy buffer on every page */
  817. for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
  818. if (bytesleft < PAGE_SIZE)
  819. mapbytes = bytesleft;
  820. else
  821. mapbytes = PAGE_SIZE;
  822. sg_set_page(sg, virt_to_page(pl022->dummypage),
  823. mapbytes, 0);
  824. bytesleft -= mapbytes;
  825. dev_dbg(&pl022->adev->dev,
  826. "set RX/TX to dummy page %d bytes, %d left\n",
  827. mapbytes, bytesleft);
  828. }
  829. }
  830. BUG_ON(bytesleft);
  831. }
  832. /**
  833. * configure_dma - configures the channels for the next transfer
  834. * @pl022: SSP driver's private data structure
  835. */
  836. static int configure_dma(struct pl022 *pl022)
  837. {
  838. struct dma_slave_config rx_conf = {
  839. .src_addr = SSP_DR(pl022->phybase),
  840. .direction = DMA_DEV_TO_MEM,
  841. .device_fc = false,
  842. };
  843. struct dma_slave_config tx_conf = {
  844. .dst_addr = SSP_DR(pl022->phybase),
  845. .direction = DMA_MEM_TO_DEV,
  846. .device_fc = false,
  847. };
  848. unsigned int pages;
  849. int ret;
  850. int rx_sglen, tx_sglen;
  851. struct dma_chan *rxchan = pl022->dma_rx_channel;
  852. struct dma_chan *txchan = pl022->dma_tx_channel;
  853. struct dma_async_tx_descriptor *rxdesc;
  854. struct dma_async_tx_descriptor *txdesc;
  855. /* Check that the channels are available */
  856. if (!rxchan || !txchan)
  857. return -ENODEV;
  858. /*
  859. * If supplied, the DMA burstsize should equal the FIFO trigger level.
  860. * Notice that the DMA engine uses one-to-one mapping. Since we can
  861. * not trigger on 2 elements this needs explicit mapping rather than
  862. * calculation.
  863. */
  864. switch (pl022->rx_lev_trig) {
  865. case SSP_RX_1_OR_MORE_ELEM:
  866. rx_conf.src_maxburst = 1;
  867. break;
  868. case SSP_RX_4_OR_MORE_ELEM:
  869. rx_conf.src_maxburst = 4;
  870. break;
  871. case SSP_RX_8_OR_MORE_ELEM:
  872. rx_conf.src_maxburst = 8;
  873. break;
  874. case SSP_RX_16_OR_MORE_ELEM:
  875. rx_conf.src_maxburst = 16;
  876. break;
  877. case SSP_RX_32_OR_MORE_ELEM:
  878. rx_conf.src_maxburst = 32;
  879. break;
  880. default:
  881. rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
  882. break;
  883. }
  884. switch (pl022->tx_lev_trig) {
  885. case SSP_TX_1_OR_MORE_EMPTY_LOC:
  886. tx_conf.dst_maxburst = 1;
  887. break;
  888. case SSP_TX_4_OR_MORE_EMPTY_LOC:
  889. tx_conf.dst_maxburst = 4;
  890. break;
  891. case SSP_TX_8_OR_MORE_EMPTY_LOC:
  892. tx_conf.dst_maxburst = 8;
  893. break;
  894. case SSP_TX_16_OR_MORE_EMPTY_LOC:
  895. tx_conf.dst_maxburst = 16;
  896. break;
  897. case SSP_TX_32_OR_MORE_EMPTY_LOC:
  898. tx_conf.dst_maxburst = 32;
  899. break;
  900. default:
  901. tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
  902. break;
  903. }
  904. switch (pl022->read) {
  905. case READING_NULL:
  906. /* Use the same as for writing */
  907. rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
  908. break;
  909. case READING_U8:
  910. rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  911. break;
  912. case READING_U16:
  913. rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  914. break;
  915. case READING_U32:
  916. rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  917. break;
  918. }
  919. switch (pl022->write) {
  920. case WRITING_NULL:
  921. /* Use the same as for reading */
  922. tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
  923. break;
  924. case WRITING_U8:
  925. tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  926. break;
  927. case WRITING_U16:
  928. tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  929. break;
  930. case WRITING_U32:
  931. tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  932. break;
  933. }
  934. /* SPI pecularity: we need to read and write the same width */
  935. if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
  936. rx_conf.src_addr_width = tx_conf.dst_addr_width;
  937. if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
  938. tx_conf.dst_addr_width = rx_conf.src_addr_width;
  939. BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
  940. dmaengine_slave_config(rxchan, &rx_conf);
  941. dmaengine_slave_config(txchan, &tx_conf);
  942. /* Create sglists for the transfers */
  943. pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
  944. dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
  945. ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
  946. if (ret)
  947. goto err_alloc_rx_sg;
  948. ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
  949. if (ret)
  950. goto err_alloc_tx_sg;
  951. /* Fill in the scatterlists for the RX+TX buffers */
  952. setup_dma_scatter(pl022, pl022->rx,
  953. pl022->cur_transfer->len, &pl022->sgt_rx);
  954. setup_dma_scatter(pl022, pl022->tx,
  955. pl022->cur_transfer->len, &pl022->sgt_tx);
  956. /* Map DMA buffers */
  957. rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
  958. pl022->sgt_rx.nents, DMA_FROM_DEVICE);
  959. if (!rx_sglen)
  960. goto err_rx_sgmap;
  961. tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
  962. pl022->sgt_tx.nents, DMA_TO_DEVICE);
  963. if (!tx_sglen)
  964. goto err_tx_sgmap;
  965. /* Send both scatterlists */
  966. rxdesc = dmaengine_prep_slave_sg(rxchan,
  967. pl022->sgt_rx.sgl,
  968. rx_sglen,
  969. DMA_DEV_TO_MEM,
  970. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  971. if (!rxdesc)
  972. goto err_rxdesc;
  973. txdesc = dmaengine_prep_slave_sg(txchan,
  974. pl022->sgt_tx.sgl,
  975. tx_sglen,
  976. DMA_MEM_TO_DEV,
  977. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  978. if (!txdesc)
  979. goto err_txdesc;
  980. /* Put the callback on the RX transfer only, that should finish last */
  981. rxdesc->callback = dma_callback;
  982. rxdesc->callback_param = pl022;
  983. /* Submit and fire RX and TX with TX last so we're ready to read! */
  984. dmaengine_submit(rxdesc);
  985. dmaengine_submit(txdesc);
  986. dma_async_issue_pending(rxchan);
  987. dma_async_issue_pending(txchan);
  988. pl022->dma_running = true;
  989. return 0;
  990. err_txdesc:
  991. dmaengine_terminate_all(txchan);
  992. err_rxdesc:
  993. dmaengine_terminate_all(rxchan);
  994. dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
  995. pl022->sgt_tx.nents, DMA_TO_DEVICE);
  996. err_tx_sgmap:
  997. dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
  998. pl022->sgt_rx.nents, DMA_FROM_DEVICE);
  999. err_rx_sgmap:
  1000. sg_free_table(&pl022->sgt_tx);
  1001. err_alloc_tx_sg:
  1002. sg_free_table(&pl022->sgt_rx);
  1003. err_alloc_rx_sg:
  1004. return -ENOMEM;
  1005. }
  1006. static int pl022_dma_probe(struct pl022 *pl022)
  1007. {
  1008. dma_cap_mask_t mask;
  1009. /* Try to acquire a generic DMA engine slave channel */
  1010. dma_cap_zero(mask);
  1011. dma_cap_set(DMA_SLAVE, mask);
  1012. /*
  1013. * We need both RX and TX channels to do DMA, else do none
  1014. * of them.
  1015. */
  1016. pl022->dma_rx_channel = dma_request_channel(mask,
  1017. pl022->master_info->dma_filter,
  1018. pl022->master_info->dma_rx_param);
  1019. if (!pl022->dma_rx_channel) {
  1020. dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
  1021. goto err_no_rxchan;
  1022. }
  1023. pl022->dma_tx_channel = dma_request_channel(mask,
  1024. pl022->master_info->dma_filter,
  1025. pl022->master_info->dma_tx_param);
  1026. if (!pl022->dma_tx_channel) {
  1027. dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
  1028. goto err_no_txchan;
  1029. }
  1030. pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
  1031. if (!pl022->dummypage)
  1032. goto err_no_dummypage;
  1033. dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
  1034. dma_chan_name(pl022->dma_rx_channel),
  1035. dma_chan_name(pl022->dma_tx_channel));
  1036. return 0;
  1037. err_no_dummypage:
  1038. dma_release_channel(pl022->dma_tx_channel);
  1039. err_no_txchan:
  1040. dma_release_channel(pl022->dma_rx_channel);
  1041. pl022->dma_rx_channel = NULL;
  1042. err_no_rxchan:
  1043. dev_err(&pl022->adev->dev,
  1044. "Failed to work in dma mode, work without dma!\n");
  1045. return -ENODEV;
  1046. }
  1047. static int pl022_dma_autoprobe(struct pl022 *pl022)
  1048. {
  1049. struct device *dev = &pl022->adev->dev;
  1050. struct dma_chan *chan;
  1051. int err;
  1052. /* automatically configure DMA channels from platform, normally using DT */
  1053. chan = dma_request_chan(dev, "rx");
  1054. if (IS_ERR(chan)) {
  1055. err = PTR_ERR(chan);
  1056. goto err_no_rxchan;
  1057. }
  1058. pl022->dma_rx_channel = chan;
  1059. chan = dma_request_chan(dev, "tx");
  1060. if (IS_ERR(chan)) {
  1061. err = PTR_ERR(chan);
  1062. goto err_no_txchan;
  1063. }
  1064. pl022->dma_tx_channel = chan;
  1065. pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
  1066. if (!pl022->dummypage) {
  1067. err = -ENOMEM;
  1068. goto err_no_dummypage;
  1069. }
  1070. return 0;
  1071. err_no_dummypage:
  1072. dma_release_channel(pl022->dma_tx_channel);
  1073. pl022->dma_tx_channel = NULL;
  1074. err_no_txchan:
  1075. dma_release_channel(pl022->dma_rx_channel);
  1076. pl022->dma_rx_channel = NULL;
  1077. err_no_rxchan:
  1078. return err;
  1079. }
  1080. static void terminate_dma(struct pl022 *pl022)
  1081. {
  1082. struct dma_chan *rxchan = pl022->dma_rx_channel;
  1083. struct dma_chan *txchan = pl022->dma_tx_channel;
  1084. dmaengine_terminate_all(rxchan);
  1085. dmaengine_terminate_all(txchan);
  1086. unmap_free_dma_scatter(pl022);
  1087. pl022->dma_running = false;
  1088. }
  1089. static void pl022_dma_remove(struct pl022 *pl022)
  1090. {
  1091. if (pl022->dma_running)
  1092. terminate_dma(pl022);
  1093. if (pl022->dma_tx_channel)
  1094. dma_release_channel(pl022->dma_tx_channel);
  1095. if (pl022->dma_rx_channel)
  1096. dma_release_channel(pl022->dma_rx_channel);
  1097. kfree(pl022->dummypage);
  1098. }
  1099. #else
  1100. static inline int configure_dma(struct pl022 *pl022)
  1101. {
  1102. return -ENODEV;
  1103. }
  1104. static inline int pl022_dma_autoprobe(struct pl022 *pl022)
  1105. {
  1106. return 0;
  1107. }
  1108. static inline int pl022_dma_probe(struct pl022 *pl022)
  1109. {
  1110. return 0;
  1111. }
  1112. static inline void pl022_dma_remove(struct pl022 *pl022)
  1113. {
  1114. }
  1115. #endif
  1116. /**
  1117. * pl022_interrupt_handler - Interrupt handler for SSP controller
  1118. * @irq: IRQ number
  1119. * @dev_id: Local device data
  1120. *
  1121. * This function handles interrupts generated for an interrupt based transfer.
  1122. * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
  1123. * current message's state as STATE_ERROR and schedule the tasklet
  1124. * pump_transfers which will do the postprocessing of the current message by
  1125. * calling giveback(). Otherwise it reads data from RX FIFO till there is no
  1126. * more data, and writes data in TX FIFO till it is not full. If we complete
  1127. * the transfer we move to the next transfer and schedule the tasklet.
  1128. */
  1129. static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
  1130. {
  1131. struct pl022 *pl022 = dev_id;
  1132. struct spi_message *msg = pl022->cur_msg;
  1133. u16 irq_status = 0;
  1134. if (unlikely(!msg)) {
  1135. dev_err(&pl022->adev->dev,
  1136. "bad message state in interrupt handler");
  1137. /* Never fail */
  1138. return IRQ_HANDLED;
  1139. }
  1140. /* Read the Interrupt Status Register */
  1141. irq_status = readw(SSP_MIS(pl022->virtbase));
  1142. if (unlikely(!irq_status))
  1143. return IRQ_NONE;
  1144. /*
  1145. * This handles the FIFO interrupts, the timeout
  1146. * interrupts are flatly ignored, they cannot be
  1147. * trusted.
  1148. */
  1149. if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
  1150. /*
  1151. * Overrun interrupt - bail out since our Data has been
  1152. * corrupted
  1153. */
  1154. dev_err(&pl022->adev->dev, "FIFO overrun\n");
  1155. if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
  1156. dev_err(&pl022->adev->dev,
  1157. "RXFIFO is full\n");
  1158. /*
  1159. * Disable and clear interrupts, disable SSP,
  1160. * mark message with bad status so it can be
  1161. * retried.
  1162. */
  1163. writew(DISABLE_ALL_INTERRUPTS,
  1164. SSP_IMSC(pl022->virtbase));
  1165. writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
  1166. writew((readw(SSP_CR1(pl022->virtbase)) &
  1167. (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
  1168. msg->state = STATE_ERROR;
  1169. /* Schedule message queue handler */
  1170. tasklet_schedule(&pl022->pump_transfers);
  1171. return IRQ_HANDLED;
  1172. }
  1173. readwriter(pl022);
  1174. if (pl022->tx == pl022->tx_end) {
  1175. /* Disable Transmit interrupt, enable receive interrupt */
  1176. writew((readw(SSP_IMSC(pl022->virtbase)) &
  1177. ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM,
  1178. SSP_IMSC(pl022->virtbase));
  1179. }
  1180. /*
  1181. * Since all transactions must write as much as shall be read,
  1182. * we can conclude the entire transaction once RX is complete.
  1183. * At this point, all TX will always be finished.
  1184. */
  1185. if (pl022->rx >= pl022->rx_end) {
  1186. writew(DISABLE_ALL_INTERRUPTS,
  1187. SSP_IMSC(pl022->virtbase));
  1188. writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
  1189. if (unlikely(pl022->rx > pl022->rx_end)) {
  1190. dev_warn(&pl022->adev->dev, "read %u surplus "
  1191. "bytes (did you request an odd "
  1192. "number of bytes on a 16bit bus?)\n",
  1193. (u32) (pl022->rx - pl022->rx_end));
  1194. }
  1195. /* Update total bytes transferred */
  1196. msg->actual_length += pl022->cur_transfer->len;
  1197. /* Move to next transfer */
  1198. msg->state = next_transfer(pl022);
  1199. if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change)
  1200. pl022_cs_control(pl022, SSP_CHIP_DESELECT);
  1201. tasklet_schedule(&pl022->pump_transfers);
  1202. return IRQ_HANDLED;
  1203. }
  1204. return IRQ_HANDLED;
  1205. }
  1206. /*
  1207. * This sets up the pointers to memory for the next message to
  1208. * send out on the SPI bus.
  1209. */
  1210. static int set_up_next_transfer(struct pl022 *pl022,
  1211. struct spi_transfer *transfer)
  1212. {
  1213. int residue;
  1214. /* Sanity check the message for this bus width */
  1215. residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
  1216. if (unlikely(residue != 0)) {
  1217. dev_err(&pl022->adev->dev,
  1218. "message of %u bytes to transmit but the current "
  1219. "chip bus has a data width of %u bytes!\n",
  1220. pl022->cur_transfer->len,
  1221. pl022->cur_chip->n_bytes);
  1222. dev_err(&pl022->adev->dev, "skipping this message\n");
  1223. return -EIO;
  1224. }
  1225. pl022->tx = (void *)transfer->tx_buf;
  1226. pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
  1227. pl022->rx = (void *)transfer->rx_buf;
  1228. pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
  1229. pl022->write =
  1230. pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
  1231. pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
  1232. return 0;
  1233. }
  1234. /**
  1235. * pump_transfers - Tasklet function which schedules next transfer
  1236. * when running in interrupt or DMA transfer mode.
  1237. * @data: SSP driver private data structure
  1238. *
  1239. */
  1240. static void pump_transfers(unsigned long data)
  1241. {
  1242. struct pl022 *pl022 = (struct pl022 *) data;
  1243. struct spi_message *message = NULL;
  1244. struct spi_transfer *transfer = NULL;
  1245. struct spi_transfer *previous = NULL;
  1246. /* Get current state information */
  1247. message = pl022->cur_msg;
  1248. transfer = pl022->cur_transfer;
  1249. /* Handle for abort */
  1250. if (message->state == STATE_ERROR) {
  1251. message->status = -EIO;
  1252. giveback(pl022);
  1253. return;
  1254. }
  1255. /* Handle end of message */
  1256. if (message->state == STATE_DONE) {
  1257. message->status = 0;
  1258. giveback(pl022);
  1259. return;
  1260. }
  1261. /* Delay if requested at end of transfer before CS change */
  1262. if (message->state == STATE_RUNNING) {
  1263. previous = list_entry(transfer->transfer_list.prev,
  1264. struct spi_transfer,
  1265. transfer_list);
  1266. /*
  1267. * FIXME: This runs in interrupt context.
  1268. * Is this really smart?
  1269. */
  1270. spi_transfer_delay_exec(previous);
  1271. /* Reselect chip select only if cs_change was requested */
  1272. if (previous->cs_change)
  1273. pl022_cs_control(pl022, SSP_CHIP_SELECT);
  1274. } else {
  1275. /* STATE_START */
  1276. message->state = STATE_RUNNING;
  1277. }
  1278. if (set_up_next_transfer(pl022, transfer)) {
  1279. message->state = STATE_ERROR;
  1280. message->status = -EIO;
  1281. giveback(pl022);
  1282. return;
  1283. }
  1284. /* Flush the FIFOs and let's go! */
  1285. flush(pl022);
  1286. if (pl022->cur_chip->enable_dma) {
  1287. if (configure_dma(pl022)) {
  1288. dev_dbg(&pl022->adev->dev,
  1289. "configuration of DMA failed, fall back to interrupt mode\n");
  1290. goto err_config_dma;
  1291. }
  1292. return;
  1293. }
  1294. err_config_dma:
  1295. /* enable all interrupts except RX */
  1296. writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase));
  1297. }
  1298. static void do_interrupt_dma_transfer(struct pl022 *pl022)
  1299. {
  1300. /*
  1301. * Default is to enable all interrupts except RX -
  1302. * this will be enabled once TX is complete
  1303. */
  1304. u32 irqflags = (u32)(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM);
  1305. /* Enable target chip, if not already active */
  1306. if (!pl022->next_msg_cs_active)
  1307. pl022_cs_control(pl022, SSP_CHIP_SELECT);
  1308. if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
  1309. /* Error path */
  1310. pl022->cur_msg->state = STATE_ERROR;
  1311. pl022->cur_msg->status = -EIO;
  1312. giveback(pl022);
  1313. return;
  1314. }
  1315. /* If we're using DMA, set up DMA here */
  1316. if (pl022->cur_chip->enable_dma) {
  1317. /* Configure DMA transfer */
  1318. if (configure_dma(pl022)) {
  1319. dev_dbg(&pl022->adev->dev,
  1320. "configuration of DMA failed, fall back to interrupt mode\n");
  1321. goto err_config_dma;
  1322. }
  1323. /* Disable interrupts in DMA mode, IRQ from DMA controller */
  1324. irqflags = DISABLE_ALL_INTERRUPTS;
  1325. }
  1326. err_config_dma:
  1327. /* Enable SSP, turn on interrupts */
  1328. writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
  1329. SSP_CR1(pl022->virtbase));
  1330. writew(irqflags, SSP_IMSC(pl022->virtbase));
  1331. }
  1332. static void print_current_status(struct pl022 *pl022)
  1333. {
  1334. u32 read_cr0;
  1335. u16 read_cr1, read_dmacr, read_sr;
  1336. if (pl022->vendor->extended_cr)
  1337. read_cr0 = readl(SSP_CR0(pl022->virtbase));
  1338. else
  1339. read_cr0 = readw(SSP_CR0(pl022->virtbase));
  1340. read_cr1 = readw(SSP_CR1(pl022->virtbase));
  1341. read_dmacr = readw(SSP_DMACR(pl022->virtbase));
  1342. read_sr = readw(SSP_SR(pl022->virtbase));
  1343. dev_warn(&pl022->adev->dev, "spi-pl022 CR0: %x\n", read_cr0);
  1344. dev_warn(&pl022->adev->dev, "spi-pl022 CR1: %x\n", read_cr1);
  1345. dev_warn(&pl022->adev->dev, "spi-pl022 DMACR: %x\n", read_dmacr);
  1346. dev_warn(&pl022->adev->dev, "spi-pl022 SR: %x\n", read_sr);
  1347. dev_warn(&pl022->adev->dev,
  1348. "spi-pl022 exp_fifo_level/fifodepth: %u/%d\n",
  1349. pl022->exp_fifo_level,
  1350. pl022->vendor->fifodepth);
  1351. }
  1352. static void do_polling_transfer(struct pl022 *pl022)
  1353. {
  1354. struct spi_message *message = NULL;
  1355. struct spi_transfer *transfer = NULL;
  1356. struct spi_transfer *previous = NULL;
  1357. unsigned long time, timeout;
  1358. message = pl022->cur_msg;
  1359. while (message->state != STATE_DONE) {
  1360. /* Handle for abort */
  1361. if (message->state == STATE_ERROR)
  1362. break;
  1363. transfer = pl022->cur_transfer;
  1364. /* Delay if requested at end of transfer */
  1365. if (message->state == STATE_RUNNING) {
  1366. previous =
  1367. list_entry(transfer->transfer_list.prev,
  1368. struct spi_transfer, transfer_list);
  1369. spi_transfer_delay_exec(previous);
  1370. if (previous->cs_change)
  1371. pl022_cs_control(pl022, SSP_CHIP_SELECT);
  1372. } else {
  1373. /* STATE_START */
  1374. message->state = STATE_RUNNING;
  1375. if (!pl022->next_msg_cs_active)
  1376. pl022_cs_control(pl022, SSP_CHIP_SELECT);
  1377. }
  1378. /* Configuration Changing Per Transfer */
  1379. if (set_up_next_transfer(pl022, transfer)) {
  1380. /* Error path */
  1381. message->state = STATE_ERROR;
  1382. break;
  1383. }
  1384. /* Flush FIFOs and enable SSP */
  1385. flush(pl022);
  1386. writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
  1387. SSP_CR1(pl022->virtbase));
  1388. dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
  1389. timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
  1390. while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
  1391. time = jiffies;
  1392. readwriter(pl022);
  1393. if (time_after(time, timeout)) {
  1394. dev_warn(&pl022->adev->dev,
  1395. "%s: timeout!\n", __func__);
  1396. message->state = STATE_TIMEOUT;
  1397. print_current_status(pl022);
  1398. goto out;
  1399. }
  1400. cpu_relax();
  1401. }
  1402. /* Update total byte transferred */
  1403. message->actual_length += pl022->cur_transfer->len;
  1404. /* Move to next transfer */
  1405. message->state = next_transfer(pl022);
  1406. if (message->state != STATE_DONE
  1407. && pl022->cur_transfer->cs_change)
  1408. pl022_cs_control(pl022, SSP_CHIP_DESELECT);
  1409. }
  1410. out:
  1411. /* Handle end of message */
  1412. if (message->state == STATE_DONE)
  1413. message->status = 0;
  1414. else if (message->state == STATE_TIMEOUT)
  1415. message->status = -EAGAIN;
  1416. else
  1417. message->status = -EIO;
  1418. giveback(pl022);
  1419. return;
  1420. }
  1421. static int pl022_transfer_one_message(struct spi_master *master,
  1422. struct spi_message *msg)
  1423. {
  1424. struct pl022 *pl022 = spi_master_get_devdata(master);
  1425. /* Initial message state */
  1426. pl022->cur_msg = msg;
  1427. msg->state = STATE_START;
  1428. pl022->cur_transfer = list_entry(msg->transfers.next,
  1429. struct spi_transfer, transfer_list);
  1430. /* Setup the SPI using the per chip configuration */
  1431. pl022->cur_chip = spi_get_ctldata(msg->spi);
  1432. pl022->cur_cs = pl022->chipselects[msg->spi->chip_select];
  1433. restore_state(pl022);
  1434. flush(pl022);
  1435. if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
  1436. do_polling_transfer(pl022);
  1437. else
  1438. do_interrupt_dma_transfer(pl022);
  1439. return 0;
  1440. }
  1441. static int pl022_unprepare_transfer_hardware(struct spi_master *master)
  1442. {
  1443. struct pl022 *pl022 = spi_master_get_devdata(master);
  1444. /* nothing more to do - disable spi/ssp and power off */
  1445. writew((readw(SSP_CR1(pl022->virtbase)) &
  1446. (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
  1447. return 0;
  1448. }
  1449. static int verify_controller_parameters(struct pl022 *pl022,
  1450. struct pl022_config_chip const *chip_info)
  1451. {
  1452. if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
  1453. || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
  1454. dev_err(&pl022->adev->dev,
  1455. "interface is configured incorrectly\n");
  1456. return -EINVAL;
  1457. }
  1458. if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
  1459. (!pl022->vendor->unidir)) {
  1460. dev_err(&pl022->adev->dev,
  1461. "unidirectional mode not supported in this "
  1462. "hardware version\n");
  1463. return -EINVAL;
  1464. }
  1465. if ((chip_info->hierarchy != SSP_MASTER)
  1466. && (chip_info->hierarchy != SSP_SLAVE)) {
  1467. dev_err(&pl022->adev->dev,
  1468. "hierarchy is configured incorrectly\n");
  1469. return -EINVAL;
  1470. }
  1471. if ((chip_info->com_mode != INTERRUPT_TRANSFER)
  1472. && (chip_info->com_mode != DMA_TRANSFER)
  1473. && (chip_info->com_mode != POLLING_TRANSFER)) {
  1474. dev_err(&pl022->adev->dev,
  1475. "Communication mode is configured incorrectly\n");
  1476. return -EINVAL;
  1477. }
  1478. switch (chip_info->rx_lev_trig) {
  1479. case SSP_RX_1_OR_MORE_ELEM:
  1480. case SSP_RX_4_OR_MORE_ELEM:
  1481. case SSP_RX_8_OR_MORE_ELEM:
  1482. /* These are always OK, all variants can handle this */
  1483. break;
  1484. case SSP_RX_16_OR_MORE_ELEM:
  1485. if (pl022->vendor->fifodepth < 16) {
  1486. dev_err(&pl022->adev->dev,
  1487. "RX FIFO Trigger Level is configured incorrectly\n");
  1488. return -EINVAL;
  1489. }
  1490. break;
  1491. case SSP_RX_32_OR_MORE_ELEM:
  1492. if (pl022->vendor->fifodepth < 32) {
  1493. dev_err(&pl022->adev->dev,
  1494. "RX FIFO Trigger Level is configured incorrectly\n");
  1495. return -EINVAL;
  1496. }
  1497. break;
  1498. default:
  1499. dev_err(&pl022->adev->dev,
  1500. "RX FIFO Trigger Level is configured incorrectly\n");
  1501. return -EINVAL;
  1502. }
  1503. switch (chip_info->tx_lev_trig) {
  1504. case SSP_TX_1_OR_MORE_EMPTY_LOC:
  1505. case SSP_TX_4_OR_MORE_EMPTY_LOC:
  1506. case SSP_TX_8_OR_MORE_EMPTY_LOC:
  1507. /* These are always OK, all variants can handle this */
  1508. break;
  1509. case SSP_TX_16_OR_MORE_EMPTY_LOC:
  1510. if (pl022->vendor->fifodepth < 16) {
  1511. dev_err(&pl022->adev->dev,
  1512. "TX FIFO Trigger Level is configured incorrectly\n");
  1513. return -EINVAL;
  1514. }
  1515. break;
  1516. case SSP_TX_32_OR_MORE_EMPTY_LOC:
  1517. if (pl022->vendor->fifodepth < 32) {
  1518. dev_err(&pl022->adev->dev,
  1519. "TX FIFO Trigger Level is configured incorrectly\n");
  1520. return -EINVAL;
  1521. }
  1522. break;
  1523. default:
  1524. dev_err(&pl022->adev->dev,
  1525. "TX FIFO Trigger Level is configured incorrectly\n");
  1526. return -EINVAL;
  1527. }
  1528. if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
  1529. if ((chip_info->ctrl_len < SSP_BITS_4)
  1530. || (chip_info->ctrl_len > SSP_BITS_32)) {
  1531. dev_err(&pl022->adev->dev,
  1532. "CTRL LEN is configured incorrectly\n");
  1533. return -EINVAL;
  1534. }
  1535. if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
  1536. && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
  1537. dev_err(&pl022->adev->dev,
  1538. "Wait State is configured incorrectly\n");
  1539. return -EINVAL;
  1540. }
  1541. /* Half duplex is only available in the ST Micro version */
  1542. if (pl022->vendor->extended_cr) {
  1543. if ((chip_info->duplex !=
  1544. SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
  1545. && (chip_info->duplex !=
  1546. SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
  1547. dev_err(&pl022->adev->dev,
  1548. "Microwire duplex mode is configured incorrectly\n");
  1549. return -EINVAL;
  1550. }
  1551. } else {
  1552. if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) {
  1553. dev_err(&pl022->adev->dev,
  1554. "Microwire half duplex mode requested,"
  1555. " but this is only available in the"
  1556. " ST version of PL022\n");
  1557. return -EINVAL;
  1558. }
  1559. }
  1560. }
  1561. return 0;
  1562. }
  1563. static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
  1564. {
  1565. return rate / (cpsdvsr * (1 + scr));
  1566. }
  1567. static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
  1568. ssp_clock_params * clk_freq)
  1569. {
  1570. /* Lets calculate the frequency parameters */
  1571. u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN;
  1572. u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0,
  1573. best_scr = 0, tmp, found = 0;
  1574. rate = clk_get_rate(pl022->clk);
  1575. /* cpsdvscr = 2 & scr 0 */
  1576. max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN);
  1577. /* cpsdvsr = 254 & scr = 255 */
  1578. min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX);
  1579. if (freq > max_tclk)
  1580. dev_warn(&pl022->adev->dev,
  1581. "Max speed that can be programmed is %d Hz, you requested %d\n",
  1582. max_tclk, freq);
  1583. if (freq < min_tclk) {
  1584. dev_err(&pl022->adev->dev,
  1585. "Requested frequency: %d Hz is less than minimum possible %d Hz\n",
  1586. freq, min_tclk);
  1587. return -EINVAL;
  1588. }
  1589. /*
  1590. * best_freq will give closest possible available rate (<= requested
  1591. * freq) for all values of scr & cpsdvsr.
  1592. */
  1593. while ((cpsdvsr <= CPSDVR_MAX) && !found) {
  1594. while (scr <= SCR_MAX) {
  1595. tmp = spi_rate(rate, cpsdvsr, scr);
  1596. if (tmp > freq) {
  1597. /* we need lower freq */
  1598. scr++;
  1599. continue;
  1600. }
  1601. /*
  1602. * If found exact value, mark found and break.
  1603. * If found more closer value, update and break.
  1604. */
  1605. if (tmp > best_freq) {
  1606. best_freq = tmp;
  1607. best_cpsdvsr = cpsdvsr;
  1608. best_scr = scr;
  1609. if (tmp == freq)
  1610. found = 1;
  1611. }
  1612. /*
  1613. * increased scr will give lower rates, which are not
  1614. * required
  1615. */
  1616. break;
  1617. }
  1618. cpsdvsr += 2;
  1619. scr = SCR_MIN;
  1620. }
  1621. WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
  1622. freq);
  1623. clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
  1624. clk_freq->scr = (u8) (best_scr & 0xFF);
  1625. dev_dbg(&pl022->adev->dev,
  1626. "SSP Target Frequency is: %u, Effective Frequency is %u\n",
  1627. freq, best_freq);
  1628. dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
  1629. clk_freq->cpsdvsr, clk_freq->scr);
  1630. return 0;
  1631. }
  1632. /*
  1633. * A piece of default chip info unless the platform
  1634. * supplies it.
  1635. */
  1636. static const struct pl022_config_chip pl022_default_chip_info = {
  1637. .com_mode = POLLING_TRANSFER,
  1638. .iface = SSP_INTERFACE_MOTOROLA_SPI,
  1639. .hierarchy = SSP_SLAVE,
  1640. .slave_tx_disable = DO_NOT_DRIVE_TX,
  1641. .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
  1642. .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
  1643. .ctrl_len = SSP_BITS_8,
  1644. .wait_state = SSP_MWIRE_WAIT_ZERO,
  1645. .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
  1646. .cs_control = null_cs_control,
  1647. };
  1648. /**
  1649. * pl022_setup - setup function registered to SPI master framework
  1650. * @spi: spi device which is requesting setup
  1651. *
  1652. * This function is registered to the SPI framework for this SPI master
  1653. * controller. If it is the first time when setup is called by this device,
  1654. * this function will initialize the runtime state for this chip and save
  1655. * the same in the device structure. Else it will update the runtime info
  1656. * with the updated chip info. Nothing is really being written to the
  1657. * controller hardware here, that is not done until the actual transfer
  1658. * commence.
  1659. */
  1660. static int pl022_setup(struct spi_device *spi)
  1661. {
  1662. struct pl022_config_chip const *chip_info;
  1663. struct pl022_config_chip chip_info_dt;
  1664. struct chip_data *chip;
  1665. struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0};
  1666. int status = 0;
  1667. struct pl022 *pl022 = spi_master_get_devdata(spi->master);
  1668. unsigned int bits = spi->bits_per_word;
  1669. u32 tmp;
  1670. struct device_node *np = spi->dev.of_node;
  1671. if (!spi->max_speed_hz)
  1672. return -EINVAL;
  1673. /* Get controller_state if one is supplied */
  1674. chip = spi_get_ctldata(spi);
  1675. if (chip == NULL) {
  1676. chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
  1677. if (!chip)
  1678. return -ENOMEM;
  1679. dev_dbg(&spi->dev,
  1680. "allocated memory for controller's runtime state\n");
  1681. }
  1682. /* Get controller data if one is supplied */
  1683. chip_info = spi->controller_data;
  1684. if (chip_info == NULL) {
  1685. if (np) {
  1686. chip_info_dt = pl022_default_chip_info;
  1687. chip_info_dt.hierarchy = SSP_MASTER;
  1688. of_property_read_u32(np, "pl022,interface",
  1689. &chip_info_dt.iface);
  1690. of_property_read_u32(np, "pl022,com-mode",
  1691. &chip_info_dt.com_mode);
  1692. of_property_read_u32(np, "pl022,rx-level-trig",
  1693. &chip_info_dt.rx_lev_trig);
  1694. of_property_read_u32(np, "pl022,tx-level-trig",
  1695. &chip_info_dt.tx_lev_trig);
  1696. of_property_read_u32(np, "pl022,ctrl-len",
  1697. &chip_info_dt.ctrl_len);
  1698. of_property_read_u32(np, "pl022,wait-state",
  1699. &chip_info_dt.wait_state);
  1700. of_property_read_u32(np, "pl022,duplex",
  1701. &chip_info_dt.duplex);
  1702. chip_info = &chip_info_dt;
  1703. } else {
  1704. chip_info = &pl022_default_chip_info;
  1705. /* spi_board_info.controller_data not is supplied */
  1706. dev_dbg(&spi->dev,
  1707. "using default controller_data settings\n");
  1708. }
  1709. } else
  1710. dev_dbg(&spi->dev,
  1711. "using user supplied controller_data settings\n");
  1712. /*
  1713. * We can override with custom divisors, else we use the board
  1714. * frequency setting
  1715. */
  1716. if ((0 == chip_info->clk_freq.cpsdvsr)
  1717. && (0 == chip_info->clk_freq.scr)) {
  1718. status = calculate_effective_freq(pl022,
  1719. spi->max_speed_hz,
  1720. &clk_freq);
  1721. if (status < 0)
  1722. goto err_config_params;
  1723. } else {
  1724. memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
  1725. if ((clk_freq.cpsdvsr % 2) != 0)
  1726. clk_freq.cpsdvsr =
  1727. clk_freq.cpsdvsr - 1;
  1728. }
  1729. if ((clk_freq.cpsdvsr < CPSDVR_MIN)
  1730. || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
  1731. status = -EINVAL;
  1732. dev_err(&spi->dev,
  1733. "cpsdvsr is configured incorrectly\n");
  1734. goto err_config_params;
  1735. }
  1736. status = verify_controller_parameters(pl022, chip_info);
  1737. if (status) {
  1738. dev_err(&spi->dev, "controller data is incorrect");
  1739. goto err_config_params;
  1740. }
  1741. pl022->rx_lev_trig = chip_info->rx_lev_trig;
  1742. pl022->tx_lev_trig = chip_info->tx_lev_trig;
  1743. /* Now set controller state based on controller data */
  1744. chip->xfer_type = chip_info->com_mode;
  1745. if (!chip_info->cs_control) {
  1746. chip->cs_control = null_cs_control;
  1747. if (!gpio_is_valid(pl022->chipselects[spi->chip_select]))
  1748. dev_warn(&spi->dev,
  1749. "invalid chip select\n");
  1750. } else
  1751. chip->cs_control = chip_info->cs_control;
  1752. /* Check bits per word with vendor specific range */
  1753. if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) {
  1754. status = -ENOTSUPP;
  1755. dev_err(&spi->dev, "illegal data size for this controller!\n");
  1756. dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n",
  1757. pl022->vendor->max_bpw);
  1758. goto err_config_params;
  1759. } else if (bits <= 8) {
  1760. dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
  1761. chip->n_bytes = 1;
  1762. chip->read = READING_U8;
  1763. chip->write = WRITING_U8;
  1764. } else if (bits <= 16) {
  1765. dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
  1766. chip->n_bytes = 2;
  1767. chip->read = READING_U16;
  1768. chip->write = WRITING_U16;
  1769. } else {
  1770. dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
  1771. chip->n_bytes = 4;
  1772. chip->read = READING_U32;
  1773. chip->write = WRITING_U32;
  1774. }
  1775. /* Now Initialize all register settings required for this chip */
  1776. chip->cr0 = 0;
  1777. chip->cr1 = 0;
  1778. chip->dmacr = 0;
  1779. chip->cpsr = 0;
  1780. if ((chip_info->com_mode == DMA_TRANSFER)
  1781. && ((pl022->master_info)->enable_dma)) {
  1782. chip->enable_dma = true;
  1783. dev_dbg(&spi->dev, "DMA mode set in controller state\n");
  1784. SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
  1785. SSP_DMACR_MASK_RXDMAE, 0);
  1786. SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
  1787. SSP_DMACR_MASK_TXDMAE, 1);
  1788. } else {
  1789. chip->enable_dma = false;
  1790. dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
  1791. SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
  1792. SSP_DMACR_MASK_RXDMAE, 0);
  1793. SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
  1794. SSP_DMACR_MASK_TXDMAE, 1);
  1795. }
  1796. chip->cpsr = clk_freq.cpsdvsr;
  1797. /* Special setup for the ST micro extended control registers */
  1798. if (pl022->vendor->extended_cr) {
  1799. u32 etx;
  1800. if (pl022->vendor->pl023) {
  1801. /* These bits are only in the PL023 */
  1802. SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
  1803. SSP_CR1_MASK_FBCLKDEL_ST, 13);
  1804. } else {
  1805. /* These bits are in the PL022 but not PL023 */
  1806. SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
  1807. SSP_CR0_MASK_HALFDUP_ST, 5);
  1808. SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
  1809. SSP_CR0_MASK_CSS_ST, 16);
  1810. SSP_WRITE_BITS(chip->cr0, chip_info->iface,
  1811. SSP_CR0_MASK_FRF_ST, 21);
  1812. SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
  1813. SSP_CR1_MASK_MWAIT_ST, 6);
  1814. }
  1815. SSP_WRITE_BITS(chip->cr0, bits - 1,
  1816. SSP_CR0_MASK_DSS_ST, 0);
  1817. if (spi->mode & SPI_LSB_FIRST) {
  1818. tmp = SSP_RX_LSB;
  1819. etx = SSP_TX_LSB;
  1820. } else {
  1821. tmp = SSP_RX_MSB;
  1822. etx = SSP_TX_MSB;
  1823. }
  1824. SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
  1825. SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
  1826. SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
  1827. SSP_CR1_MASK_RXIFLSEL_ST, 7);
  1828. SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
  1829. SSP_CR1_MASK_TXIFLSEL_ST, 10);
  1830. } else {
  1831. SSP_WRITE_BITS(chip->cr0, bits - 1,
  1832. SSP_CR0_MASK_DSS, 0);
  1833. SSP_WRITE_BITS(chip->cr0, chip_info->iface,
  1834. SSP_CR0_MASK_FRF, 4);
  1835. }
  1836. /* Stuff that is common for all versions */
  1837. if (spi->mode & SPI_CPOL)
  1838. tmp = SSP_CLK_POL_IDLE_HIGH;
  1839. else
  1840. tmp = SSP_CLK_POL_IDLE_LOW;
  1841. SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
  1842. if (spi->mode & SPI_CPHA)
  1843. tmp = SSP_CLK_SECOND_EDGE;
  1844. else
  1845. tmp = SSP_CLK_FIRST_EDGE;
  1846. SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
  1847. SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
  1848. /* Loopback is available on all versions except PL023 */
  1849. if (pl022->vendor->loopback) {
  1850. if (spi->mode & SPI_LOOP)
  1851. tmp = LOOPBACK_ENABLED;
  1852. else
  1853. tmp = LOOPBACK_DISABLED;
  1854. SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
  1855. }
  1856. SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
  1857. SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
  1858. SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,
  1859. 3);
  1860. /* Save controller_state */
  1861. spi_set_ctldata(spi, chip);
  1862. return status;
  1863. err_config_params:
  1864. spi_set_ctldata(spi, NULL);
  1865. kfree(chip);
  1866. return status;
  1867. }
  1868. /**
  1869. * pl022_cleanup - cleanup function registered to SPI master framework
  1870. * @spi: spi device which is requesting cleanup
  1871. *
  1872. * This function is registered to the SPI framework for this SPI master
  1873. * controller. It will free the runtime state of chip.
  1874. */
  1875. static void pl022_cleanup(struct spi_device *spi)
  1876. {
  1877. struct chip_data *chip = spi_get_ctldata(spi);
  1878. spi_set_ctldata(spi, NULL);
  1879. kfree(chip);
  1880. }
  1881. static struct pl022_ssp_controller *
  1882. pl022_platform_data_dt_get(struct device *dev)
  1883. {
  1884. struct device_node *np = dev->of_node;
  1885. struct pl022_ssp_controller *pd;
  1886. u32 tmp = 0;
  1887. if (!np) {
  1888. dev_err(dev, "no dt node defined\n");
  1889. return NULL;
  1890. }
  1891. pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL);
  1892. if (!pd)
  1893. return NULL;
  1894. pd->bus_id = -1;
  1895. pd->enable_dma = 1;
  1896. of_property_read_u32(np, "num-cs", &tmp);
  1897. pd->num_chipselect = tmp;
  1898. of_property_read_u32(np, "pl022,autosuspend-delay",
  1899. &pd->autosuspend_delay);
  1900. pd->rt = of_property_read_bool(np, "pl022,rt");
  1901. return pd;
  1902. }
  1903. static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
  1904. {
  1905. struct device *dev = &adev->dev;
  1906. struct pl022_ssp_controller *platform_info =
  1907. dev_get_platdata(&adev->dev);
  1908. struct spi_master *master;
  1909. struct pl022 *pl022 = NULL; /*Data for this driver */
  1910. struct device_node *np = adev->dev.of_node;
  1911. int status = 0, i, num_cs;
  1912. dev_info(&adev->dev,
  1913. "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
  1914. if (!platform_info && IS_ENABLED(CONFIG_OF))
  1915. platform_info = pl022_platform_data_dt_get(dev);
  1916. if (!platform_info) {
  1917. dev_err(dev, "probe: no platform data defined\n");
  1918. return -ENODEV;
  1919. }
  1920. if (platform_info->num_chipselect) {
  1921. num_cs = platform_info->num_chipselect;
  1922. } else {
  1923. dev_err(dev, "probe: no chip select defined\n");
  1924. return -ENODEV;
  1925. }
  1926. /* Allocate master with space for data */
  1927. master = spi_alloc_master(dev, sizeof(struct pl022));
  1928. if (master == NULL) {
  1929. dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
  1930. return -ENOMEM;
  1931. }
  1932. pl022 = spi_master_get_devdata(master);
  1933. pl022->master = master;
  1934. pl022->master_info = platform_info;
  1935. pl022->adev = adev;
  1936. pl022->vendor = id->data;
  1937. pl022->chipselects = devm_kcalloc(dev, num_cs, sizeof(int),
  1938. GFP_KERNEL);
  1939. if (!pl022->chipselects) {
  1940. status = -ENOMEM;
  1941. goto err_no_mem;
  1942. }
  1943. /*
  1944. * Bus Number Which has been Assigned to this SSP controller
  1945. * on this board
  1946. */
  1947. master->bus_num = platform_info->bus_id;
  1948. master->num_chipselect = num_cs;
  1949. master->cleanup = pl022_cleanup;
  1950. master->setup = pl022_setup;
  1951. master->auto_runtime_pm = true;
  1952. master->transfer_one_message = pl022_transfer_one_message;
  1953. master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware;
  1954. master->rt = platform_info->rt;
  1955. master->dev.of_node = dev->of_node;
  1956. if (platform_info->num_chipselect && platform_info->chipselects) {
  1957. for (i = 0; i < num_cs; i++)
  1958. pl022->chipselects[i] = platform_info->chipselects[i];
  1959. } else if (pl022->vendor->internal_cs_ctrl) {
  1960. for (i = 0; i < num_cs; i++)
  1961. pl022->chipselects[i] = i;
  1962. } else if (IS_ENABLED(CONFIG_OF)) {
  1963. for (i = 0; i < num_cs; i++) {
  1964. int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
  1965. if (cs_gpio == -EPROBE_DEFER) {
  1966. status = -EPROBE_DEFER;
  1967. goto err_no_gpio;
  1968. }
  1969. pl022->chipselects[i] = cs_gpio;
  1970. if (gpio_is_valid(cs_gpio)) {
  1971. if (devm_gpio_request(dev, cs_gpio, "ssp-pl022"))
  1972. dev_err(&adev->dev,
  1973. "could not request %d gpio\n",
  1974. cs_gpio);
  1975. else if (gpio_direction_output(cs_gpio, 1))
  1976. dev_err(&adev->dev,
  1977. "could not set gpio %d as output\n",
  1978. cs_gpio);
  1979. }
  1980. }
  1981. }
  1982. /*
  1983. * Supports mode 0-3, loopback, and active low CS. Transfers are
  1984. * always MS bit first on the original pl022.
  1985. */
  1986. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
  1987. if (pl022->vendor->extended_cr)
  1988. master->mode_bits |= SPI_LSB_FIRST;
  1989. dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
  1990. status = amba_request_regions(adev, NULL);
  1991. if (status)
  1992. goto err_no_ioregion;
  1993. pl022->phybase = adev->res.start;
  1994. pl022->virtbase = devm_ioremap(dev, adev->res.start,
  1995. resource_size(&adev->res));
  1996. if (pl022->virtbase == NULL) {
  1997. status = -ENOMEM;
  1998. goto err_no_ioremap;
  1999. }
  2000. dev_info(&adev->dev, "mapped registers from %pa to %p\n",
  2001. &adev->res.start, pl022->virtbase);
  2002. pl022->clk = devm_clk_get(&adev->dev, NULL);
  2003. if (IS_ERR(pl022->clk)) {
  2004. status = PTR_ERR(pl022->clk);
  2005. dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
  2006. goto err_no_clk;
  2007. }
  2008. status = clk_prepare_enable(pl022->clk);
  2009. if (status) {
  2010. dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n");
  2011. goto err_no_clk_en;
  2012. }
  2013. /* Initialize transfer pump */
  2014. tasklet_init(&pl022->pump_transfers, pump_transfers,
  2015. (unsigned long)pl022);
  2016. /* Disable SSP */
  2017. writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
  2018. SSP_CR1(pl022->virtbase));
  2019. load_ssp_default_config(pl022);
  2020. status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler,
  2021. 0, "pl022", pl022);
  2022. if (status < 0) {
  2023. dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
  2024. goto err_no_irq;
  2025. }
  2026. /* Get DMA channels, try autoconfiguration first */
  2027. status = pl022_dma_autoprobe(pl022);
  2028. if (status == -EPROBE_DEFER) {
  2029. dev_dbg(dev, "deferring probe to get DMA channel\n");
  2030. goto err_no_irq;
  2031. }
  2032. /* If that failed, use channels from platform_info */
  2033. if (status == 0)
  2034. platform_info->enable_dma = 1;
  2035. else if (platform_info->enable_dma) {
  2036. status = pl022_dma_probe(pl022);
  2037. if (status != 0)
  2038. platform_info->enable_dma = 0;
  2039. }
  2040. /* Register with the SPI framework */
  2041. amba_set_drvdata(adev, pl022);
  2042. status = devm_spi_register_master(&adev->dev, master);
  2043. if (status != 0) {
  2044. dev_err(&adev->dev,
  2045. "probe - problem registering spi master\n");
  2046. goto err_spi_register;
  2047. }
  2048. dev_dbg(dev, "probe succeeded\n");
  2049. /* let runtime pm put suspend */
  2050. if (platform_info->autosuspend_delay > 0) {
  2051. dev_info(&adev->dev,
  2052. "will use autosuspend for runtime pm, delay %dms\n",
  2053. platform_info->autosuspend_delay);
  2054. pm_runtime_set_autosuspend_delay(dev,
  2055. platform_info->autosuspend_delay);
  2056. pm_runtime_use_autosuspend(dev);
  2057. }
  2058. pm_runtime_put(dev);
  2059. return 0;
  2060. err_spi_register:
  2061. if (platform_info->enable_dma)
  2062. pl022_dma_remove(pl022);
  2063. err_no_irq:
  2064. clk_disable_unprepare(pl022->clk);
  2065. err_no_clk_en:
  2066. err_no_clk:
  2067. err_no_ioremap:
  2068. amba_release_regions(adev);
  2069. err_no_ioregion:
  2070. err_no_gpio:
  2071. err_no_mem:
  2072. spi_master_put(master);
  2073. return status;
  2074. }
  2075. static void
  2076. pl022_remove(struct amba_device *adev)
  2077. {
  2078. struct pl022 *pl022 = amba_get_drvdata(adev);
  2079. if (!pl022)
  2080. return;
  2081. /*
  2082. * undo pm_runtime_put() in probe. I assume that we're not
  2083. * accessing the primecell here.
  2084. */
  2085. pm_runtime_get_noresume(&adev->dev);
  2086. load_ssp_default_config(pl022);
  2087. if (pl022->master_info->enable_dma)
  2088. pl022_dma_remove(pl022);
  2089. clk_disable_unprepare(pl022->clk);
  2090. amba_release_regions(adev);
  2091. tasklet_disable(&pl022->pump_transfers);
  2092. }
  2093. #ifdef CONFIG_PM_SLEEP
  2094. static int pl022_suspend(struct device *dev)
  2095. {
  2096. struct pl022 *pl022 = dev_get_drvdata(dev);
  2097. int ret;
  2098. ret = spi_master_suspend(pl022->master);
  2099. if (ret)
  2100. return ret;
  2101. ret = pm_runtime_force_suspend(dev);
  2102. if (ret) {
  2103. spi_master_resume(pl022->master);
  2104. return ret;
  2105. }
  2106. pinctrl_pm_select_sleep_state(dev);
  2107. dev_dbg(dev, "suspended\n");
  2108. return 0;
  2109. }
  2110. static int pl022_resume(struct device *dev)
  2111. {
  2112. struct pl022 *pl022 = dev_get_drvdata(dev);
  2113. int ret;
  2114. ret = pm_runtime_force_resume(dev);
  2115. if (ret)
  2116. dev_err(dev, "problem resuming\n");
  2117. /* Start the queue running */
  2118. ret = spi_master_resume(pl022->master);
  2119. if (!ret)
  2120. dev_dbg(dev, "resumed\n");
  2121. return ret;
  2122. }
  2123. #endif
  2124. #ifdef CONFIG_PM
  2125. static int pl022_runtime_suspend(struct device *dev)
  2126. {
  2127. struct pl022 *pl022 = dev_get_drvdata(dev);
  2128. clk_disable_unprepare(pl022->clk);
  2129. pinctrl_pm_select_idle_state(dev);
  2130. return 0;
  2131. }
  2132. static int pl022_runtime_resume(struct device *dev)
  2133. {
  2134. struct pl022 *pl022 = dev_get_drvdata(dev);
  2135. pinctrl_pm_select_default_state(dev);
  2136. clk_prepare_enable(pl022->clk);
  2137. return 0;
  2138. }
  2139. #endif
  2140. static const struct dev_pm_ops pl022_dev_pm_ops = {
  2141. SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
  2142. SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
  2143. };
  2144. static struct vendor_data vendor_arm = {
  2145. .fifodepth = 8,
  2146. .max_bpw = 16,
  2147. .unidir = false,
  2148. .extended_cr = false,
  2149. .pl023 = false,
  2150. .loopback = true,
  2151. .internal_cs_ctrl = false,
  2152. };
  2153. static struct vendor_data vendor_st = {
  2154. .fifodepth = 32,
  2155. .max_bpw = 32,
  2156. .unidir = false,
  2157. .extended_cr = true,
  2158. .pl023 = false,
  2159. .loopback = true,
  2160. .internal_cs_ctrl = false,
  2161. };
  2162. static struct vendor_data vendor_st_pl023 = {
  2163. .fifodepth = 32,
  2164. .max_bpw = 32,
  2165. .unidir = false,
  2166. .extended_cr = true,
  2167. .pl023 = true,
  2168. .loopback = false,
  2169. .internal_cs_ctrl = false,
  2170. };
  2171. static struct vendor_data vendor_lsi = {
  2172. .fifodepth = 8,
  2173. .max_bpw = 16,
  2174. .unidir = false,
  2175. .extended_cr = false,
  2176. .pl023 = false,
  2177. .loopback = true,
  2178. .internal_cs_ctrl = true,
  2179. };
  2180. static const struct amba_id pl022_ids[] = {
  2181. {
  2182. /*
  2183. * ARM PL022 variant, this has a 16bit wide
  2184. * and 8 locations deep TX/RX FIFO
  2185. */
  2186. .id = 0x00041022,
  2187. .mask = 0x000fffff,
  2188. .data = &vendor_arm,
  2189. },
  2190. {
  2191. /*
  2192. * ST Micro derivative, this has 32bit wide
  2193. * and 32 locations deep TX/RX FIFO
  2194. */
  2195. .id = 0x01080022,
  2196. .mask = 0xffffffff,
  2197. .data = &vendor_st,
  2198. },
  2199. {
  2200. /*
  2201. * ST-Ericsson derivative "PL023" (this is not
  2202. * an official ARM number), this is a PL022 SSP block
  2203. * stripped to SPI mode only, it has 32bit wide
  2204. * and 32 locations deep TX/RX FIFO but no extended
  2205. * CR0/CR1 register
  2206. */
  2207. .id = 0x00080023,
  2208. .mask = 0xffffffff,
  2209. .data = &vendor_st_pl023,
  2210. },
  2211. {
  2212. /*
  2213. * PL022 variant that has a chip select control register whih
  2214. * allows control of 5 output signals nCS[0:4].
  2215. */
  2216. .id = 0x000b6022,
  2217. .mask = 0x000fffff,
  2218. .data = &vendor_lsi,
  2219. },
  2220. { 0, 0 },
  2221. };
  2222. MODULE_DEVICE_TABLE(amba, pl022_ids);
  2223. static struct amba_driver pl022_driver = {
  2224. .drv = {
  2225. .name = "ssp-pl022",
  2226. .pm = &pl022_dev_pm_ops,
  2227. },
  2228. .id_table = pl022_ids,
  2229. .probe = pl022_probe,
  2230. .remove = pl022_remove,
  2231. };
  2232. static int __init pl022_init(void)
  2233. {
  2234. return amba_driver_register(&pl022_driver);
  2235. }
  2236. subsys_initcall(pl022_init);
  2237. static void __exit pl022_exit(void)
  2238. {
  2239. amba_driver_unregister(&pl022_driver);
  2240. }
  2241. module_exit(pl022_exit);
  2242. MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
  2243. MODULE_DESCRIPTION("PL022 SSP Controller Driver");
  2244. MODULE_LICENSE("GPL");