spi-pic32-sqi.c 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * PIC32 Quad SPI controller driver.
  4. *
  5. * Purna Chandra Mandal <purna.mandal@microchip.com>
  6. * Copyright (c) 2016, Microchip Technology Inc.
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/io.h>
  12. #include <linux/iopoll.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/slab.h>
  17. #include <linux/spi/spi.h>
  18. /* SQI registers */
  19. #define PESQI_XIP_CONF1_REG 0x00
  20. #define PESQI_XIP_CONF2_REG 0x04
  21. #define PESQI_CONF_REG 0x08
  22. #define PESQI_CTRL_REG 0x0C
  23. #define PESQI_CLK_CTRL_REG 0x10
  24. #define PESQI_CMD_THRES_REG 0x14
  25. #define PESQI_INT_THRES_REG 0x18
  26. #define PESQI_INT_ENABLE_REG 0x1C
  27. #define PESQI_INT_STAT_REG 0x20
  28. #define PESQI_TX_DATA_REG 0x24
  29. #define PESQI_RX_DATA_REG 0x28
  30. #define PESQI_STAT1_REG 0x2C
  31. #define PESQI_STAT2_REG 0x30
  32. #define PESQI_BD_CTRL_REG 0x34
  33. #define PESQI_BD_CUR_ADDR_REG 0x38
  34. #define PESQI_BD_BASE_ADDR_REG 0x40
  35. #define PESQI_BD_STAT_REG 0x44
  36. #define PESQI_BD_POLL_CTRL_REG 0x48
  37. #define PESQI_BD_TX_DMA_STAT_REG 0x4C
  38. #define PESQI_BD_RX_DMA_STAT_REG 0x50
  39. #define PESQI_THRES_REG 0x54
  40. #define PESQI_INT_SIGEN_REG 0x58
  41. /* PESQI_CONF_REG fields */
  42. #define PESQI_MODE 0x7
  43. #define PESQI_MODE_BOOT 0
  44. #define PESQI_MODE_PIO 1
  45. #define PESQI_MODE_DMA 2
  46. #define PESQI_MODE_XIP 3
  47. #define PESQI_MODE_SHIFT 0
  48. #define PESQI_CPHA BIT(3)
  49. #define PESQI_CPOL BIT(4)
  50. #define PESQI_LSBF BIT(5)
  51. #define PESQI_RXLATCH BIT(7)
  52. #define PESQI_SERMODE BIT(8)
  53. #define PESQI_WP_EN BIT(9)
  54. #define PESQI_HOLD_EN BIT(10)
  55. #define PESQI_BURST_EN BIT(12)
  56. #define PESQI_CS_CTRL_HW BIT(15)
  57. #define PESQI_SOFT_RESET BIT(16)
  58. #define PESQI_LANES_SHIFT 20
  59. #define PESQI_SINGLE_LANE 0
  60. #define PESQI_DUAL_LANE 1
  61. #define PESQI_QUAD_LANE 2
  62. #define PESQI_CSEN_SHIFT 24
  63. #define PESQI_EN BIT(23)
  64. /* PESQI_CLK_CTRL_REG fields */
  65. #define PESQI_CLK_EN BIT(0)
  66. #define PESQI_CLK_STABLE BIT(1)
  67. #define PESQI_CLKDIV_SHIFT 8
  68. #define PESQI_CLKDIV 0xff
  69. /* PESQI_INT_THR/CMD_THR_REG */
  70. #define PESQI_TXTHR_MASK 0x1f
  71. #define PESQI_TXTHR_SHIFT 8
  72. #define PESQI_RXTHR_MASK 0x1f
  73. #define PESQI_RXTHR_SHIFT 0
  74. /* PESQI_INT_EN/INT_STAT/INT_SIG_EN_REG */
  75. #define PESQI_TXEMPTY BIT(0)
  76. #define PESQI_TXFULL BIT(1)
  77. #define PESQI_TXTHR BIT(2)
  78. #define PESQI_RXEMPTY BIT(3)
  79. #define PESQI_RXFULL BIT(4)
  80. #define PESQI_RXTHR BIT(5)
  81. #define PESQI_BDDONE BIT(9) /* BD processing complete */
  82. #define PESQI_PKTCOMP BIT(10) /* packet processing complete */
  83. #define PESQI_DMAERR BIT(11) /* error */
  84. /* PESQI_BD_CTRL_REG */
  85. #define PESQI_DMA_EN BIT(0) /* enable DMA engine */
  86. #define PESQI_POLL_EN BIT(1) /* enable polling */
  87. #define PESQI_BDP_START BIT(2) /* start BD processor */
  88. /* PESQI controller buffer descriptor */
  89. struct buf_desc {
  90. u32 bd_ctrl; /* control */
  91. u32 bd_status; /* reserved */
  92. u32 bd_addr; /* DMA buffer addr */
  93. u32 bd_nextp; /* next item in chain */
  94. };
  95. /* bd_ctrl */
  96. #define BD_BUFLEN 0x1ff
  97. #define BD_CBD_INT_EN BIT(16) /* Current BD is processed */
  98. #define BD_PKT_INT_EN BIT(17) /* All BDs of PKT processed */
  99. #define BD_LIFM BIT(18) /* last data of pkt */
  100. #define BD_LAST BIT(19) /* end of list */
  101. #define BD_DATA_RECV BIT(20) /* receive data */
  102. #define BD_DDR BIT(21) /* DDR mode */
  103. #define BD_DUAL BIT(22) /* Dual SPI */
  104. #define BD_QUAD BIT(23) /* Quad SPI */
  105. #define BD_LSBF BIT(25) /* LSB First */
  106. #define BD_STAT_CHECK BIT(27) /* Status poll */
  107. #define BD_DEVSEL_SHIFT 28 /* CS */
  108. #define BD_CS_DEASSERT BIT(30) /* de-assert CS after current BD */
  109. #define BD_EN BIT(31) /* BD owned by H/W */
  110. /**
  111. * struct ring_desc - Representation of SQI ring descriptor
  112. * @list: list element to add to free or used list.
  113. * @bd: PESQI controller buffer descriptor
  114. * @bd_dma: DMA address of PESQI controller buffer descriptor
  115. * @xfer_len: transfer length
  116. */
  117. struct ring_desc {
  118. struct list_head list;
  119. struct buf_desc *bd;
  120. dma_addr_t bd_dma;
  121. u32 xfer_len;
  122. };
  123. /* Global constants */
  124. #define PESQI_BD_BUF_LEN_MAX 256
  125. #define PESQI_BD_COUNT 256 /* max 64KB data per spi message */
  126. struct pic32_sqi {
  127. void __iomem *regs;
  128. struct clk *sys_clk;
  129. struct clk *base_clk; /* drives spi clock */
  130. struct spi_master *master;
  131. int irq;
  132. struct completion xfer_done;
  133. struct ring_desc *ring;
  134. void *bd;
  135. dma_addr_t bd_dma;
  136. struct list_head bd_list_free; /* free */
  137. struct list_head bd_list_used; /* allocated */
  138. struct spi_device *cur_spi;
  139. u32 cur_speed;
  140. u8 cur_mode;
  141. };
  142. static inline void pic32_setbits(void __iomem *reg, u32 set)
  143. {
  144. writel(readl(reg) | set, reg);
  145. }
  146. static inline void pic32_clrbits(void __iomem *reg, u32 clr)
  147. {
  148. writel(readl(reg) & ~clr, reg);
  149. }
  150. static int pic32_sqi_set_clk_rate(struct pic32_sqi *sqi, u32 sck)
  151. {
  152. u32 val, div;
  153. /* div = base_clk / (2 * spi_clk) */
  154. div = clk_get_rate(sqi->base_clk) / (2 * sck);
  155. div &= PESQI_CLKDIV;
  156. val = readl(sqi->regs + PESQI_CLK_CTRL_REG);
  157. /* apply new divider */
  158. val &= ~(PESQI_CLK_STABLE | (PESQI_CLKDIV << PESQI_CLKDIV_SHIFT));
  159. val |= div << PESQI_CLKDIV_SHIFT;
  160. writel(val, sqi->regs + PESQI_CLK_CTRL_REG);
  161. /* wait for stability */
  162. return readl_poll_timeout(sqi->regs + PESQI_CLK_CTRL_REG, val,
  163. val & PESQI_CLK_STABLE, 1, 5000);
  164. }
  165. static inline void pic32_sqi_enable_int(struct pic32_sqi *sqi)
  166. {
  167. u32 mask = PESQI_DMAERR | PESQI_BDDONE | PESQI_PKTCOMP;
  168. writel(mask, sqi->regs + PESQI_INT_ENABLE_REG);
  169. /* INT_SIGEN works as interrupt-gate to INTR line */
  170. writel(mask, sqi->regs + PESQI_INT_SIGEN_REG);
  171. }
  172. static inline void pic32_sqi_disable_int(struct pic32_sqi *sqi)
  173. {
  174. writel(0, sqi->regs + PESQI_INT_ENABLE_REG);
  175. writel(0, sqi->regs + PESQI_INT_SIGEN_REG);
  176. }
  177. static irqreturn_t pic32_sqi_isr(int irq, void *dev_id)
  178. {
  179. struct pic32_sqi *sqi = dev_id;
  180. u32 enable, status;
  181. enable = readl(sqi->regs + PESQI_INT_ENABLE_REG);
  182. status = readl(sqi->regs + PESQI_INT_STAT_REG);
  183. /* check spurious interrupt */
  184. if (!status)
  185. return IRQ_NONE;
  186. if (status & PESQI_DMAERR) {
  187. enable = 0;
  188. goto irq_done;
  189. }
  190. if (status & PESQI_TXTHR)
  191. enable &= ~(PESQI_TXTHR | PESQI_TXFULL | PESQI_TXEMPTY);
  192. if (status & PESQI_RXTHR)
  193. enable &= ~(PESQI_RXTHR | PESQI_RXFULL | PESQI_RXEMPTY);
  194. if (status & PESQI_BDDONE)
  195. enable &= ~PESQI_BDDONE;
  196. /* packet processing completed */
  197. if (status & PESQI_PKTCOMP) {
  198. /* mask all interrupts */
  199. enable = 0;
  200. /* complete trasaction */
  201. complete(&sqi->xfer_done);
  202. }
  203. irq_done:
  204. /* interrupts are sticky, so mask when handled */
  205. writel(enable, sqi->regs + PESQI_INT_ENABLE_REG);
  206. return IRQ_HANDLED;
  207. }
  208. static struct ring_desc *ring_desc_get(struct pic32_sqi *sqi)
  209. {
  210. struct ring_desc *rdesc;
  211. if (list_empty(&sqi->bd_list_free))
  212. return NULL;
  213. rdesc = list_first_entry(&sqi->bd_list_free, struct ring_desc, list);
  214. list_move_tail(&rdesc->list, &sqi->bd_list_used);
  215. return rdesc;
  216. }
  217. static void ring_desc_put(struct pic32_sqi *sqi, struct ring_desc *rdesc)
  218. {
  219. list_move(&rdesc->list, &sqi->bd_list_free);
  220. }
  221. static int pic32_sqi_one_transfer(struct pic32_sqi *sqi,
  222. struct spi_message *mesg,
  223. struct spi_transfer *xfer)
  224. {
  225. struct spi_device *spi = mesg->spi;
  226. struct scatterlist *sg, *sgl;
  227. struct ring_desc *rdesc;
  228. struct buf_desc *bd;
  229. int nents, i;
  230. u32 bd_ctrl;
  231. u32 nbits;
  232. /* Device selection */
  233. bd_ctrl = spi->chip_select << BD_DEVSEL_SHIFT;
  234. /* half-duplex: select transfer buffer, direction and lane */
  235. if (xfer->rx_buf) {
  236. bd_ctrl |= BD_DATA_RECV;
  237. nbits = xfer->rx_nbits;
  238. sgl = xfer->rx_sg.sgl;
  239. nents = xfer->rx_sg.nents;
  240. } else {
  241. nbits = xfer->tx_nbits;
  242. sgl = xfer->tx_sg.sgl;
  243. nents = xfer->tx_sg.nents;
  244. }
  245. if (nbits & SPI_NBITS_QUAD)
  246. bd_ctrl |= BD_QUAD;
  247. else if (nbits & SPI_NBITS_DUAL)
  248. bd_ctrl |= BD_DUAL;
  249. /* LSB first */
  250. if (spi->mode & SPI_LSB_FIRST)
  251. bd_ctrl |= BD_LSBF;
  252. /* ownership to hardware */
  253. bd_ctrl |= BD_EN;
  254. for_each_sg(sgl, sg, nents, i) {
  255. /* get ring descriptor */
  256. rdesc = ring_desc_get(sqi);
  257. if (!rdesc)
  258. break;
  259. bd = rdesc->bd;
  260. /* BD CTRL: length */
  261. rdesc->xfer_len = sg_dma_len(sg);
  262. bd->bd_ctrl = bd_ctrl;
  263. bd->bd_ctrl |= rdesc->xfer_len;
  264. /* BD STAT */
  265. bd->bd_status = 0;
  266. /* BD BUFFER ADDRESS */
  267. bd->bd_addr = sg->dma_address;
  268. }
  269. return 0;
  270. }
  271. static int pic32_sqi_prepare_hardware(struct spi_master *master)
  272. {
  273. struct pic32_sqi *sqi = spi_master_get_devdata(master);
  274. /* enable spi interface */
  275. pic32_setbits(sqi->regs + PESQI_CONF_REG, PESQI_EN);
  276. /* enable spi clk */
  277. pic32_setbits(sqi->regs + PESQI_CLK_CTRL_REG, PESQI_CLK_EN);
  278. return 0;
  279. }
  280. static bool pic32_sqi_can_dma(struct spi_master *master,
  281. struct spi_device *spi,
  282. struct spi_transfer *x)
  283. {
  284. /* Do DMA irrespective of transfer size */
  285. return true;
  286. }
  287. static int pic32_sqi_one_message(struct spi_master *master,
  288. struct spi_message *msg)
  289. {
  290. struct spi_device *spi = msg->spi;
  291. struct ring_desc *rdesc, *next;
  292. struct spi_transfer *xfer;
  293. struct pic32_sqi *sqi;
  294. int ret = 0, mode;
  295. unsigned long timeout;
  296. u32 val;
  297. sqi = spi_master_get_devdata(master);
  298. reinit_completion(&sqi->xfer_done);
  299. msg->actual_length = 0;
  300. /* We can't handle spi_transfer specific "speed_hz", "bits_per_word"
  301. * and "delay_usecs". But spi_device specific speed and mode change
  302. * can be handled at best during spi chip-select switch.
  303. */
  304. if (sqi->cur_spi != spi) {
  305. /* set spi speed */
  306. if (sqi->cur_speed != spi->max_speed_hz) {
  307. sqi->cur_speed = spi->max_speed_hz;
  308. ret = pic32_sqi_set_clk_rate(sqi, spi->max_speed_hz);
  309. if (ret)
  310. dev_warn(&spi->dev, "set_clk, %d\n", ret);
  311. }
  312. /* set spi mode */
  313. mode = spi->mode & (SPI_MODE_3 | SPI_LSB_FIRST);
  314. if (sqi->cur_mode != mode) {
  315. val = readl(sqi->regs + PESQI_CONF_REG);
  316. val &= ~(PESQI_CPOL | PESQI_CPHA | PESQI_LSBF);
  317. if (mode & SPI_CPOL)
  318. val |= PESQI_CPOL;
  319. if (mode & SPI_LSB_FIRST)
  320. val |= PESQI_LSBF;
  321. val |= PESQI_CPHA;
  322. writel(val, sqi->regs + PESQI_CONF_REG);
  323. sqi->cur_mode = mode;
  324. }
  325. sqi->cur_spi = spi;
  326. }
  327. /* prepare hardware desc-list(BD) for transfer(s) */
  328. list_for_each_entry(xfer, &msg->transfers, transfer_list) {
  329. ret = pic32_sqi_one_transfer(sqi, msg, xfer);
  330. if (ret) {
  331. dev_err(&spi->dev, "xfer %p err\n", xfer);
  332. goto xfer_out;
  333. }
  334. }
  335. /* BDs are prepared and chained. Now mark LAST_BD, CS_DEASSERT at last
  336. * element of the list.
  337. */
  338. rdesc = list_last_entry(&sqi->bd_list_used, struct ring_desc, list);
  339. rdesc->bd->bd_ctrl |= BD_LAST | BD_CS_DEASSERT |
  340. BD_LIFM | BD_PKT_INT_EN;
  341. /* set base address BD list for DMA engine */
  342. rdesc = list_first_entry(&sqi->bd_list_used, struct ring_desc, list);
  343. writel(rdesc->bd_dma, sqi->regs + PESQI_BD_BASE_ADDR_REG);
  344. /* enable interrupt */
  345. pic32_sqi_enable_int(sqi);
  346. /* enable DMA engine */
  347. val = PESQI_DMA_EN | PESQI_POLL_EN | PESQI_BDP_START;
  348. writel(val, sqi->regs + PESQI_BD_CTRL_REG);
  349. /* wait for xfer completion */
  350. timeout = wait_for_completion_timeout(&sqi->xfer_done, 5 * HZ);
  351. if (timeout == 0) {
  352. dev_err(&sqi->master->dev, "wait timedout/interrupted\n");
  353. ret = -ETIMEDOUT;
  354. msg->status = ret;
  355. } else {
  356. /* success */
  357. msg->status = 0;
  358. ret = 0;
  359. }
  360. /* disable DMA */
  361. writel(0, sqi->regs + PESQI_BD_CTRL_REG);
  362. pic32_sqi_disable_int(sqi);
  363. xfer_out:
  364. list_for_each_entry_safe_reverse(rdesc, next,
  365. &sqi->bd_list_used, list) {
  366. /* Update total byte transferred */
  367. msg->actual_length += rdesc->xfer_len;
  368. /* release ring descr */
  369. ring_desc_put(sqi, rdesc);
  370. }
  371. spi_finalize_current_message(spi->master);
  372. return ret;
  373. }
  374. static int pic32_sqi_unprepare_hardware(struct spi_master *master)
  375. {
  376. struct pic32_sqi *sqi = spi_master_get_devdata(master);
  377. /* disable clk */
  378. pic32_clrbits(sqi->regs + PESQI_CLK_CTRL_REG, PESQI_CLK_EN);
  379. /* disable spi */
  380. pic32_clrbits(sqi->regs + PESQI_CONF_REG, PESQI_EN);
  381. return 0;
  382. }
  383. static int ring_desc_ring_alloc(struct pic32_sqi *sqi)
  384. {
  385. struct ring_desc *rdesc;
  386. struct buf_desc *bd;
  387. int i;
  388. /* allocate coherent DMAable memory for hardware buffer descriptors. */
  389. sqi->bd = dma_alloc_coherent(&sqi->master->dev,
  390. sizeof(*bd) * PESQI_BD_COUNT,
  391. &sqi->bd_dma, GFP_KERNEL);
  392. if (!sqi->bd) {
  393. dev_err(&sqi->master->dev, "failed allocating dma buffer\n");
  394. return -ENOMEM;
  395. }
  396. /* allocate software ring descriptors */
  397. sqi->ring = kcalloc(PESQI_BD_COUNT, sizeof(*rdesc), GFP_KERNEL);
  398. if (!sqi->ring) {
  399. dma_free_coherent(&sqi->master->dev,
  400. sizeof(*bd) * PESQI_BD_COUNT,
  401. sqi->bd, sqi->bd_dma);
  402. return -ENOMEM;
  403. }
  404. bd = (struct buf_desc *)sqi->bd;
  405. INIT_LIST_HEAD(&sqi->bd_list_free);
  406. INIT_LIST_HEAD(&sqi->bd_list_used);
  407. /* initialize ring-desc */
  408. for (i = 0, rdesc = sqi->ring; i < PESQI_BD_COUNT; i++, rdesc++) {
  409. INIT_LIST_HEAD(&rdesc->list);
  410. rdesc->bd = &bd[i];
  411. rdesc->bd_dma = sqi->bd_dma + (void *)&bd[i] - (void *)bd;
  412. list_add_tail(&rdesc->list, &sqi->bd_list_free);
  413. }
  414. /* Prepare BD: chain to next BD(s) */
  415. for (i = 0, rdesc = sqi->ring; i < PESQI_BD_COUNT - 1; i++)
  416. bd[i].bd_nextp = rdesc[i + 1].bd_dma;
  417. bd[PESQI_BD_COUNT - 1].bd_nextp = 0;
  418. return 0;
  419. }
  420. static void ring_desc_ring_free(struct pic32_sqi *sqi)
  421. {
  422. dma_free_coherent(&sqi->master->dev,
  423. sizeof(struct buf_desc) * PESQI_BD_COUNT,
  424. sqi->bd, sqi->bd_dma);
  425. kfree(sqi->ring);
  426. }
  427. static void pic32_sqi_hw_init(struct pic32_sqi *sqi)
  428. {
  429. unsigned long flags;
  430. u32 val;
  431. /* Soft-reset of PESQI controller triggers interrupt.
  432. * We are not yet ready to handle them so disable CPU
  433. * interrupt for the time being.
  434. */
  435. local_irq_save(flags);
  436. /* assert soft-reset */
  437. writel(PESQI_SOFT_RESET, sqi->regs + PESQI_CONF_REG);
  438. /* wait until clear */
  439. readl_poll_timeout_atomic(sqi->regs + PESQI_CONF_REG, val,
  440. !(val & PESQI_SOFT_RESET), 1, 5000);
  441. /* disable all interrupts */
  442. pic32_sqi_disable_int(sqi);
  443. /* Now it is safe to enable back CPU interrupt */
  444. local_irq_restore(flags);
  445. /* tx and rx fifo interrupt threshold */
  446. val = readl(sqi->regs + PESQI_CMD_THRES_REG);
  447. val &= ~(PESQI_TXTHR_MASK << PESQI_TXTHR_SHIFT);
  448. val &= ~(PESQI_RXTHR_MASK << PESQI_RXTHR_SHIFT);
  449. val |= (1U << PESQI_TXTHR_SHIFT) | (1U << PESQI_RXTHR_SHIFT);
  450. writel(val, sqi->regs + PESQI_CMD_THRES_REG);
  451. val = readl(sqi->regs + PESQI_INT_THRES_REG);
  452. val &= ~(PESQI_TXTHR_MASK << PESQI_TXTHR_SHIFT);
  453. val &= ~(PESQI_RXTHR_MASK << PESQI_RXTHR_SHIFT);
  454. val |= (1U << PESQI_TXTHR_SHIFT) | (1U << PESQI_RXTHR_SHIFT);
  455. writel(val, sqi->regs + PESQI_INT_THRES_REG);
  456. /* default configuration */
  457. val = readl(sqi->regs + PESQI_CONF_REG);
  458. /* set mode: DMA */
  459. val &= ~PESQI_MODE;
  460. val |= PESQI_MODE_DMA << PESQI_MODE_SHIFT;
  461. writel(val, sqi->regs + PESQI_CONF_REG);
  462. /* DATAEN - SQIID0-ID3 */
  463. val |= PESQI_QUAD_LANE << PESQI_LANES_SHIFT;
  464. /* burst/INCR4 enable */
  465. val |= PESQI_BURST_EN;
  466. /* CSEN - all CS */
  467. val |= 3U << PESQI_CSEN_SHIFT;
  468. writel(val, sqi->regs + PESQI_CONF_REG);
  469. /* write poll count */
  470. writel(0, sqi->regs + PESQI_BD_POLL_CTRL_REG);
  471. sqi->cur_speed = 0;
  472. sqi->cur_mode = -1;
  473. }
  474. static int pic32_sqi_probe(struct platform_device *pdev)
  475. {
  476. struct spi_master *master;
  477. struct pic32_sqi *sqi;
  478. int ret;
  479. master = spi_alloc_master(&pdev->dev, sizeof(*sqi));
  480. if (!master)
  481. return -ENOMEM;
  482. sqi = spi_master_get_devdata(master);
  483. sqi->master = master;
  484. sqi->regs = devm_platform_ioremap_resource(pdev, 0);
  485. if (IS_ERR(sqi->regs)) {
  486. ret = PTR_ERR(sqi->regs);
  487. goto err_free_master;
  488. }
  489. /* irq */
  490. sqi->irq = platform_get_irq(pdev, 0);
  491. if (sqi->irq < 0) {
  492. ret = sqi->irq;
  493. goto err_free_master;
  494. }
  495. /* clocks */
  496. sqi->sys_clk = devm_clk_get(&pdev->dev, "reg_ck");
  497. if (IS_ERR(sqi->sys_clk)) {
  498. ret = PTR_ERR(sqi->sys_clk);
  499. dev_err(&pdev->dev, "no sys_clk ?\n");
  500. goto err_free_master;
  501. }
  502. sqi->base_clk = devm_clk_get(&pdev->dev, "spi_ck");
  503. if (IS_ERR(sqi->base_clk)) {
  504. ret = PTR_ERR(sqi->base_clk);
  505. dev_err(&pdev->dev, "no base clk ?\n");
  506. goto err_free_master;
  507. }
  508. ret = clk_prepare_enable(sqi->sys_clk);
  509. if (ret) {
  510. dev_err(&pdev->dev, "sys clk enable failed\n");
  511. goto err_free_master;
  512. }
  513. ret = clk_prepare_enable(sqi->base_clk);
  514. if (ret) {
  515. dev_err(&pdev->dev, "base clk enable failed\n");
  516. clk_disable_unprepare(sqi->sys_clk);
  517. goto err_free_master;
  518. }
  519. init_completion(&sqi->xfer_done);
  520. /* initialize hardware */
  521. pic32_sqi_hw_init(sqi);
  522. /* allocate buffers & descriptors */
  523. ret = ring_desc_ring_alloc(sqi);
  524. if (ret) {
  525. dev_err(&pdev->dev, "ring alloc failed\n");
  526. goto err_disable_clk;
  527. }
  528. /* install irq handlers */
  529. ret = request_irq(sqi->irq, pic32_sqi_isr, 0,
  530. dev_name(&pdev->dev), sqi);
  531. if (ret < 0) {
  532. dev_err(&pdev->dev, "request_irq(%d), failed\n", sqi->irq);
  533. goto err_free_ring;
  534. }
  535. /* register master */
  536. master->num_chipselect = 2;
  537. master->max_speed_hz = clk_get_rate(sqi->base_clk);
  538. master->dma_alignment = 32;
  539. master->max_dma_len = PESQI_BD_BUF_LEN_MAX;
  540. master->dev.of_node = pdev->dev.of_node;
  541. master->mode_bits = SPI_MODE_3 | SPI_MODE_0 | SPI_TX_DUAL |
  542. SPI_RX_DUAL | SPI_TX_QUAD | SPI_RX_QUAD;
  543. master->flags = SPI_MASTER_HALF_DUPLEX;
  544. master->can_dma = pic32_sqi_can_dma;
  545. master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
  546. master->transfer_one_message = pic32_sqi_one_message;
  547. master->prepare_transfer_hardware = pic32_sqi_prepare_hardware;
  548. master->unprepare_transfer_hardware = pic32_sqi_unprepare_hardware;
  549. ret = devm_spi_register_master(&pdev->dev, master);
  550. if (ret) {
  551. dev_err(&master->dev, "failed registering spi master\n");
  552. free_irq(sqi->irq, sqi);
  553. goto err_free_ring;
  554. }
  555. platform_set_drvdata(pdev, sqi);
  556. return 0;
  557. err_free_ring:
  558. ring_desc_ring_free(sqi);
  559. err_disable_clk:
  560. clk_disable_unprepare(sqi->base_clk);
  561. clk_disable_unprepare(sqi->sys_clk);
  562. err_free_master:
  563. spi_master_put(master);
  564. return ret;
  565. }
  566. static int pic32_sqi_remove(struct platform_device *pdev)
  567. {
  568. struct pic32_sqi *sqi = platform_get_drvdata(pdev);
  569. /* release resources */
  570. free_irq(sqi->irq, sqi);
  571. ring_desc_ring_free(sqi);
  572. /* disable clk */
  573. clk_disable_unprepare(sqi->base_clk);
  574. clk_disable_unprepare(sqi->sys_clk);
  575. return 0;
  576. }
  577. static const struct of_device_id pic32_sqi_of_ids[] = {
  578. {.compatible = "microchip,pic32mzda-sqi",},
  579. {},
  580. };
  581. MODULE_DEVICE_TABLE(of, pic32_sqi_of_ids);
  582. static struct platform_driver pic32_sqi_driver = {
  583. .driver = {
  584. .name = "sqi-pic32",
  585. .of_match_table = of_match_ptr(pic32_sqi_of_ids),
  586. },
  587. .probe = pic32_sqi_probe,
  588. .remove = pic32_sqi_remove,
  589. };
  590. module_platform_driver(pic32_sqi_driver);
  591. MODULE_AUTHOR("Purna Chandra Mandal <purna.mandal@microchip.com>");
  592. MODULE_DESCRIPTION("Microchip SPI driver for PIC32 SQI controller.");
  593. MODULE_LICENSE("GPL v2");