spi-orion.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Marvell Orion SPI controller driver
  4. *
  5. * Author: Shadi Ammouri <shadi@marvell.com>
  6. * Copyright (C) 2007-2008 Marvell Ltd.
  7. */
  8. #include <linux/interrupt.h>
  9. #include <linux/delay.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/err.h>
  12. #include <linux/io.h>
  13. #include <linux/spi/spi.h>
  14. #include <linux/module.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/of.h>
  17. #include <linux/of_address.h>
  18. #include <linux/of_device.h>
  19. #include <linux/clk.h>
  20. #include <linux/sizes.h>
  21. #include <asm/unaligned.h>
  22. #define DRIVER_NAME "orion_spi"
  23. /* Runtime PM autosuspend timeout: PM is fairly light on this driver */
  24. #define SPI_AUTOSUSPEND_TIMEOUT 200
  25. /* Some SoCs using this driver support up to 8 chip selects.
  26. * It is up to the implementer to only use the chip selects
  27. * that are available.
  28. */
  29. #define ORION_NUM_CHIPSELECTS 8
  30. #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
  31. #define ORION_SPI_IF_CTRL_REG 0x00
  32. #define ORION_SPI_IF_CONFIG_REG 0x04
  33. #define ORION_SPI_IF_RXLSBF BIT(14)
  34. #define ORION_SPI_IF_TXLSBF BIT(13)
  35. #define ORION_SPI_DATA_OUT_REG 0x08
  36. #define ORION_SPI_DATA_IN_REG 0x0c
  37. #define ORION_SPI_INT_CAUSE_REG 0x10
  38. #define ORION_SPI_TIMING_PARAMS_REG 0x18
  39. /* Register for the "Direct Mode" */
  40. #define SPI_DIRECT_WRITE_CONFIG_REG 0x20
  41. #define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6)
  42. #define ORION_SPI_TMISO_SAMPLE_1 (1 << 6)
  43. #define ORION_SPI_TMISO_SAMPLE_2 (2 << 6)
  44. #define ORION_SPI_MODE_CPOL (1 << 11)
  45. #define ORION_SPI_MODE_CPHA (1 << 12)
  46. #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
  47. #define ORION_SPI_CLK_PRESCALE_MASK 0x1F
  48. #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF
  49. #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
  50. ORION_SPI_MODE_CPHA)
  51. #define ORION_SPI_CS_MASK 0x1C
  52. #define ORION_SPI_CS_SHIFT 2
  53. #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \
  54. ORION_SPI_CS_MASK)
  55. enum orion_spi_type {
  56. ORION_SPI,
  57. ARMADA_SPI,
  58. };
  59. struct orion_spi_dev {
  60. enum orion_spi_type typ;
  61. /*
  62. * min_divisor and max_hz should be exclusive, the only we can
  63. * have both is for managing the armada-370-spi case with old
  64. * device tree
  65. */
  66. unsigned long max_hz;
  67. unsigned int min_divisor;
  68. unsigned int max_divisor;
  69. u32 prescale_mask;
  70. bool is_errata_50mhz_ac;
  71. };
  72. struct orion_direct_acc {
  73. void __iomem *vaddr;
  74. u32 size;
  75. };
  76. struct orion_child_options {
  77. struct orion_direct_acc direct_access;
  78. };
  79. struct orion_spi {
  80. struct spi_master *master;
  81. void __iomem *base;
  82. struct clk *clk;
  83. struct clk *axi_clk;
  84. const struct orion_spi_dev *devdata;
  85. struct orion_child_options child[ORION_NUM_CHIPSELECTS];
  86. };
  87. static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
  88. {
  89. return orion_spi->base + reg;
  90. }
  91. static inline void
  92. orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
  93. {
  94. void __iomem *reg_addr = spi_reg(orion_spi, reg);
  95. u32 val;
  96. val = readl(reg_addr);
  97. val |= mask;
  98. writel(val, reg_addr);
  99. }
  100. static inline void
  101. orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
  102. {
  103. void __iomem *reg_addr = spi_reg(orion_spi, reg);
  104. u32 val;
  105. val = readl(reg_addr);
  106. val &= ~mask;
  107. writel(val, reg_addr);
  108. }
  109. static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
  110. {
  111. u32 tclk_hz;
  112. u32 rate;
  113. u32 prescale;
  114. u32 reg;
  115. struct orion_spi *orion_spi;
  116. const struct orion_spi_dev *devdata;
  117. orion_spi = spi_master_get_devdata(spi->master);
  118. devdata = orion_spi->devdata;
  119. tclk_hz = clk_get_rate(orion_spi->clk);
  120. if (devdata->typ == ARMADA_SPI) {
  121. /*
  122. * Given the core_clk (tclk_hz) and the target rate (speed) we
  123. * determine the best values for SPR (in [0 .. 15]) and SPPR (in
  124. * [0..7]) such that
  125. *
  126. * core_clk / (SPR * 2 ** SPPR)
  127. *
  128. * is as big as possible but not bigger than speed.
  129. */
  130. /* best integer divider: */
  131. unsigned divider = DIV_ROUND_UP(tclk_hz, speed);
  132. unsigned spr, sppr;
  133. if (divider < 16) {
  134. /* This is the easy case, divider is less than 16 */
  135. spr = divider;
  136. sppr = 0;
  137. } else {
  138. unsigned two_pow_sppr;
  139. /*
  140. * Find the highest bit set in divider. This and the
  141. * three next bits define SPR (apart from rounding).
  142. * SPPR is then the number of zero bits that must be
  143. * appended:
  144. */
  145. sppr = fls(divider) - 4;
  146. /*
  147. * As SPR only has 4 bits, we have to round divider up
  148. * to the next multiple of 2 ** sppr.
  149. */
  150. two_pow_sppr = 1 << sppr;
  151. divider = (divider + two_pow_sppr - 1) & -two_pow_sppr;
  152. /*
  153. * recalculate sppr as rounding up divider might have
  154. * increased it enough to change the position of the
  155. * highest set bit. In this case the bit that now
  156. * doesn't make it into SPR is 0, so there is no need to
  157. * round again.
  158. */
  159. sppr = fls(divider) - 4;
  160. spr = divider >> sppr;
  161. /*
  162. * Now do range checking. SPR is constructed to have a
  163. * width of 4 bits, so this is fine for sure. So we
  164. * still need to check for sppr to fit into 3 bits:
  165. */
  166. if (sppr > 7)
  167. return -EINVAL;
  168. }
  169. prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr;
  170. } else {
  171. /*
  172. * the supported rates are: 4,6,8...30
  173. * round up as we look for equal or less speed
  174. */
  175. rate = DIV_ROUND_UP(tclk_hz, speed);
  176. rate = roundup(rate, 2);
  177. /* check if requested speed is too small */
  178. if (rate > 30)
  179. return -EINVAL;
  180. if (rate < 4)
  181. rate = 4;
  182. /* Convert the rate to SPI clock divisor value. */
  183. prescale = 0x10 + rate/2;
  184. }
  185. reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
  186. reg = ((reg & ~devdata->prescale_mask) | prescale);
  187. writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
  188. return 0;
  189. }
  190. static void
  191. orion_spi_mode_set(struct spi_device *spi)
  192. {
  193. u32 reg;
  194. struct orion_spi *orion_spi;
  195. orion_spi = spi_master_get_devdata(spi->master);
  196. reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
  197. reg &= ~ORION_SPI_MODE_MASK;
  198. if (spi->mode & SPI_CPOL)
  199. reg |= ORION_SPI_MODE_CPOL;
  200. if (spi->mode & SPI_CPHA)
  201. reg |= ORION_SPI_MODE_CPHA;
  202. if (spi->mode & SPI_LSB_FIRST)
  203. reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF;
  204. else
  205. reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF);
  206. writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
  207. }
  208. static void
  209. orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed)
  210. {
  211. u32 reg;
  212. struct orion_spi *orion_spi;
  213. orion_spi = spi_master_get_devdata(spi->master);
  214. /*
  215. * Erratum description: (Erratum NO. FE-9144572) The device
  216. * SPI interface supports frequencies of up to 50 MHz.
  217. * However, due to this erratum, when the device core clock is
  218. * 250 MHz and the SPI interfaces is configured for 50MHz SPI
  219. * clock and CPOL=CPHA=1 there might occur data corruption on
  220. * reads from the SPI device.
  221. * Erratum Workaround:
  222. * Work in one of the following configurations:
  223. * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
  224. * Register".
  225. * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
  226. * Register" before setting the interface.
  227. */
  228. reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
  229. reg &= ~ORION_SPI_TMISO_SAMPLE_MASK;
  230. if (clk_get_rate(orion_spi->clk) == 250000000 &&
  231. speed == 50000000 && spi->mode & SPI_CPOL &&
  232. spi->mode & SPI_CPHA)
  233. reg |= ORION_SPI_TMISO_SAMPLE_2;
  234. else
  235. reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */
  236. writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
  237. }
  238. /*
  239. * called only when no transfer is active on the bus
  240. */
  241. static int
  242. orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
  243. {
  244. struct orion_spi *orion_spi;
  245. unsigned int speed = spi->max_speed_hz;
  246. unsigned int bits_per_word = spi->bits_per_word;
  247. int rc;
  248. orion_spi = spi_master_get_devdata(spi->master);
  249. if ((t != NULL) && t->speed_hz)
  250. speed = t->speed_hz;
  251. if ((t != NULL) && t->bits_per_word)
  252. bits_per_word = t->bits_per_word;
  253. orion_spi_mode_set(spi);
  254. if (orion_spi->devdata->is_errata_50mhz_ac)
  255. orion_spi_50mhz_ac_timing_erratum(spi, speed);
  256. rc = orion_spi_baudrate_set(spi, speed);
  257. if (rc)
  258. return rc;
  259. if (bits_per_word == 16)
  260. orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
  261. ORION_SPI_IF_8_16_BIT_MODE);
  262. else
  263. orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
  264. ORION_SPI_IF_8_16_BIT_MODE);
  265. return 0;
  266. }
  267. static void orion_spi_set_cs(struct spi_device *spi, bool enable)
  268. {
  269. struct orion_spi *orion_spi;
  270. orion_spi = spi_master_get_devdata(spi->master);
  271. /*
  272. * If this line is using a GPIO to control chip select, this internal
  273. * .set_cs() function will still be called, so we clear any previous
  274. * chip select. The CS we activate will not have any elecrical effect,
  275. * as it is handled by a GPIO, but that doesn't matter. What we need
  276. * is to deassert the old chip select and assert some other chip select.
  277. */
  278. orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK);
  279. orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG,
  280. ORION_SPI_CS(spi->chip_select));
  281. /*
  282. * Chip select logic is inverted from spi_set_cs(). For lines using a
  283. * GPIO to do chip select SPI_CS_HIGH is enforced and inversion happens
  284. * in the GPIO library, but we don't care about that, because in those
  285. * cases we are dealing with an unused native CS anyways so the polarity
  286. * doesn't matter.
  287. */
  288. if (!enable)
  289. orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
  290. else
  291. orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
  292. }
  293. static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
  294. {
  295. int i;
  296. for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
  297. if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
  298. return 1;
  299. udelay(1);
  300. }
  301. return -1;
  302. }
  303. static inline int
  304. orion_spi_write_read_8bit(struct spi_device *spi,
  305. const u8 **tx_buf, u8 **rx_buf)
  306. {
  307. void __iomem *tx_reg, *rx_reg, *int_reg;
  308. struct orion_spi *orion_spi;
  309. orion_spi = spi_master_get_devdata(spi->master);
  310. tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
  311. rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
  312. int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
  313. /* clear the interrupt cause register */
  314. writel(0x0, int_reg);
  315. if (tx_buf && *tx_buf)
  316. writel(*(*tx_buf)++, tx_reg);
  317. else
  318. writel(0, tx_reg);
  319. if (orion_spi_wait_till_ready(orion_spi) < 0) {
  320. dev_err(&spi->dev, "TXS timed out\n");
  321. return -1;
  322. }
  323. if (rx_buf && *rx_buf)
  324. *(*rx_buf)++ = readl(rx_reg);
  325. return 1;
  326. }
  327. static inline int
  328. orion_spi_write_read_16bit(struct spi_device *spi,
  329. const u16 **tx_buf, u16 **rx_buf)
  330. {
  331. void __iomem *tx_reg, *rx_reg, *int_reg;
  332. struct orion_spi *orion_spi;
  333. orion_spi = spi_master_get_devdata(spi->master);
  334. tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
  335. rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
  336. int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
  337. /* clear the interrupt cause register */
  338. writel(0x0, int_reg);
  339. if (tx_buf && *tx_buf)
  340. writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
  341. else
  342. writel(0, tx_reg);
  343. if (orion_spi_wait_till_ready(orion_spi) < 0) {
  344. dev_err(&spi->dev, "TXS timed out\n");
  345. return -1;
  346. }
  347. if (rx_buf && *rx_buf)
  348. put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
  349. return 1;
  350. }
  351. static unsigned int
  352. orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
  353. {
  354. unsigned int count;
  355. int word_len;
  356. struct orion_spi *orion_spi;
  357. int cs = spi->chip_select;
  358. void __iomem *vaddr;
  359. word_len = spi->bits_per_word;
  360. count = xfer->len;
  361. orion_spi = spi_master_get_devdata(spi->master);
  362. /*
  363. * Use SPI direct write mode if base address is available. Otherwise
  364. * fall back to PIO mode for this transfer.
  365. */
  366. vaddr = orion_spi->child[cs].direct_access.vaddr;
  367. if (vaddr && xfer->tx_buf && word_len == 8) {
  368. unsigned int cnt = count / 4;
  369. unsigned int rem = count % 4;
  370. /*
  371. * Send the TX-data to the SPI device via the direct
  372. * mapped address window
  373. */
  374. iowrite32_rep(vaddr, xfer->tx_buf, cnt);
  375. if (rem) {
  376. u32 *buf = (u32 *)xfer->tx_buf;
  377. iowrite8_rep(vaddr, &buf[cnt], rem);
  378. }
  379. return count;
  380. }
  381. if (word_len == 8) {
  382. const u8 *tx = xfer->tx_buf;
  383. u8 *rx = xfer->rx_buf;
  384. do {
  385. if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
  386. goto out;
  387. count--;
  388. spi_delay_exec(&xfer->word_delay, xfer);
  389. } while (count);
  390. } else if (word_len == 16) {
  391. const u16 *tx = xfer->tx_buf;
  392. u16 *rx = xfer->rx_buf;
  393. do {
  394. if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
  395. goto out;
  396. count -= 2;
  397. spi_delay_exec(&xfer->word_delay, xfer);
  398. } while (count);
  399. }
  400. out:
  401. return xfer->len - count;
  402. }
  403. static int orion_spi_transfer_one(struct spi_master *master,
  404. struct spi_device *spi,
  405. struct spi_transfer *t)
  406. {
  407. int status = 0;
  408. status = orion_spi_setup_transfer(spi, t);
  409. if (status < 0)
  410. return status;
  411. if (t->len)
  412. orion_spi_write_read(spi, t);
  413. return status;
  414. }
  415. static int orion_spi_setup(struct spi_device *spi)
  416. {
  417. return orion_spi_setup_transfer(spi, NULL);
  418. }
  419. static int orion_spi_reset(struct orion_spi *orion_spi)
  420. {
  421. /* Verify that the CS is deasserted */
  422. orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
  423. /* Don't deassert CS between the direct mapped SPI transfers */
  424. writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG));
  425. return 0;
  426. }
  427. static const struct orion_spi_dev orion_spi_dev_data = {
  428. .typ = ORION_SPI,
  429. .min_divisor = 4,
  430. .max_divisor = 30,
  431. .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK,
  432. };
  433. static const struct orion_spi_dev armada_370_spi_dev_data = {
  434. .typ = ARMADA_SPI,
  435. .min_divisor = 4,
  436. .max_divisor = 1920,
  437. .max_hz = 50000000,
  438. .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
  439. };
  440. static const struct orion_spi_dev armada_xp_spi_dev_data = {
  441. .typ = ARMADA_SPI,
  442. .max_hz = 50000000,
  443. .max_divisor = 1920,
  444. .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
  445. };
  446. static const struct orion_spi_dev armada_375_spi_dev_data = {
  447. .typ = ARMADA_SPI,
  448. .min_divisor = 15,
  449. .max_divisor = 1920,
  450. .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
  451. };
  452. static const struct orion_spi_dev armada_380_spi_dev_data = {
  453. .typ = ARMADA_SPI,
  454. .max_hz = 50000000,
  455. .max_divisor = 1920,
  456. .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
  457. .is_errata_50mhz_ac = true,
  458. };
  459. static const struct of_device_id orion_spi_of_match_table[] = {
  460. {
  461. .compatible = "marvell,orion-spi",
  462. .data = &orion_spi_dev_data,
  463. },
  464. {
  465. .compatible = "marvell,armada-370-spi",
  466. .data = &armada_370_spi_dev_data,
  467. },
  468. {
  469. .compatible = "marvell,armada-375-spi",
  470. .data = &armada_375_spi_dev_data,
  471. },
  472. {
  473. .compatible = "marvell,armada-380-spi",
  474. .data = &armada_380_spi_dev_data,
  475. },
  476. {
  477. .compatible = "marvell,armada-390-spi",
  478. .data = &armada_xp_spi_dev_data,
  479. },
  480. {
  481. .compatible = "marvell,armada-xp-spi",
  482. .data = &armada_xp_spi_dev_data,
  483. },
  484. {}
  485. };
  486. MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
  487. static int orion_spi_probe(struct platform_device *pdev)
  488. {
  489. const struct of_device_id *of_id;
  490. const struct orion_spi_dev *devdata;
  491. struct spi_master *master;
  492. struct orion_spi *spi;
  493. struct resource *r;
  494. unsigned long tclk_hz;
  495. int status = 0;
  496. struct device_node *np;
  497. master = spi_alloc_master(&pdev->dev, sizeof(*spi));
  498. if (master == NULL) {
  499. dev_dbg(&pdev->dev, "master allocation failed\n");
  500. return -ENOMEM;
  501. }
  502. if (pdev->id != -1)
  503. master->bus_num = pdev->id;
  504. if (pdev->dev.of_node) {
  505. u32 cell_index;
  506. if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
  507. &cell_index))
  508. master->bus_num = cell_index;
  509. }
  510. /* we support all 4 SPI modes and LSB first option */
  511. master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST;
  512. master->set_cs = orion_spi_set_cs;
  513. master->transfer_one = orion_spi_transfer_one;
  514. master->num_chipselect = ORION_NUM_CHIPSELECTS;
  515. master->setup = orion_spi_setup;
  516. master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
  517. master->auto_runtime_pm = true;
  518. master->use_gpio_descriptors = true;
  519. master->flags = SPI_MASTER_GPIO_SS;
  520. platform_set_drvdata(pdev, master);
  521. spi = spi_master_get_devdata(master);
  522. spi->master = master;
  523. of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
  524. devdata = (of_id) ? of_id->data : &orion_spi_dev_data;
  525. spi->devdata = devdata;
  526. spi->clk = devm_clk_get(&pdev->dev, NULL);
  527. if (IS_ERR(spi->clk)) {
  528. status = PTR_ERR(spi->clk);
  529. goto out;
  530. }
  531. status = clk_prepare_enable(spi->clk);
  532. if (status)
  533. goto out;
  534. /* The following clock is only used by some SoCs */
  535. spi->axi_clk = devm_clk_get(&pdev->dev, "axi");
  536. if (PTR_ERR(spi->axi_clk) == -EPROBE_DEFER) {
  537. status = -EPROBE_DEFER;
  538. goto out_rel_clk;
  539. }
  540. if (!IS_ERR(spi->axi_clk))
  541. clk_prepare_enable(spi->axi_clk);
  542. tclk_hz = clk_get_rate(spi->clk);
  543. /*
  544. * With old device tree, armada-370-spi could be used with
  545. * Armada XP, however for this SoC the maximum frequency is
  546. * 50MHz instead of tclk/4. On Armada 370, tclk cannot be
  547. * higher than 200MHz. So, in order to be able to handle both
  548. * SoCs, we can take the minimum of 50MHz and tclk/4.
  549. */
  550. if (of_device_is_compatible(pdev->dev.of_node,
  551. "marvell,armada-370-spi"))
  552. master->max_speed_hz = min(devdata->max_hz,
  553. DIV_ROUND_UP(tclk_hz, devdata->min_divisor));
  554. else if (devdata->min_divisor)
  555. master->max_speed_hz =
  556. DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
  557. else
  558. master->max_speed_hz = devdata->max_hz;
  559. master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
  560. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  561. spi->base = devm_ioremap_resource(&pdev->dev, r);
  562. if (IS_ERR(spi->base)) {
  563. status = PTR_ERR(spi->base);
  564. goto out_rel_axi_clk;
  565. }
  566. for_each_available_child_of_node(pdev->dev.of_node, np) {
  567. struct orion_direct_acc *dir_acc;
  568. u32 cs;
  569. /* Get chip-select number from the "reg" property */
  570. status = of_property_read_u32(np, "reg", &cs);
  571. if (status) {
  572. dev_err(&pdev->dev,
  573. "%pOF has no valid 'reg' property (%d)\n",
  574. np, status);
  575. continue;
  576. }
  577. /*
  578. * Check if an address is configured for this SPI device. If
  579. * not, the MBus mapping via the 'ranges' property in the 'soc'
  580. * node is not configured and this device should not use the
  581. * direct mode. In this case, just continue with the next
  582. * device.
  583. */
  584. status = of_address_to_resource(pdev->dev.of_node, cs + 1, r);
  585. if (status)
  586. continue;
  587. /*
  588. * Only map one page for direct access. This is enough for the
  589. * simple TX transfer which only writes to the first word.
  590. * This needs to get extended for the direct SPI NOR / SPI NAND
  591. * support, once this gets implemented.
  592. */
  593. dir_acc = &spi->child[cs].direct_access;
  594. dir_acc->vaddr = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE);
  595. if (!dir_acc->vaddr) {
  596. status = -ENOMEM;
  597. goto out_rel_axi_clk;
  598. }
  599. dir_acc->size = PAGE_SIZE;
  600. dev_info(&pdev->dev, "CS%d configured for direct access\n", cs);
  601. }
  602. pm_runtime_set_active(&pdev->dev);
  603. pm_runtime_use_autosuspend(&pdev->dev);
  604. pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
  605. pm_runtime_enable(&pdev->dev);
  606. status = orion_spi_reset(spi);
  607. if (status < 0)
  608. goto out_rel_pm;
  609. master->dev.of_node = pdev->dev.of_node;
  610. status = spi_register_master(master);
  611. if (status < 0)
  612. goto out_rel_pm;
  613. return status;
  614. out_rel_pm:
  615. pm_runtime_disable(&pdev->dev);
  616. out_rel_axi_clk:
  617. clk_disable_unprepare(spi->axi_clk);
  618. out_rel_clk:
  619. clk_disable_unprepare(spi->clk);
  620. out:
  621. spi_master_put(master);
  622. return status;
  623. }
  624. static int orion_spi_remove(struct platform_device *pdev)
  625. {
  626. struct spi_master *master = platform_get_drvdata(pdev);
  627. struct orion_spi *spi = spi_master_get_devdata(master);
  628. pm_runtime_get_sync(&pdev->dev);
  629. clk_disable_unprepare(spi->axi_clk);
  630. clk_disable_unprepare(spi->clk);
  631. spi_unregister_master(master);
  632. pm_runtime_disable(&pdev->dev);
  633. return 0;
  634. }
  635. MODULE_ALIAS("platform:" DRIVER_NAME);
  636. #ifdef CONFIG_PM
  637. static int orion_spi_runtime_suspend(struct device *dev)
  638. {
  639. struct spi_master *master = dev_get_drvdata(dev);
  640. struct orion_spi *spi = spi_master_get_devdata(master);
  641. clk_disable_unprepare(spi->axi_clk);
  642. clk_disable_unprepare(spi->clk);
  643. return 0;
  644. }
  645. static int orion_spi_runtime_resume(struct device *dev)
  646. {
  647. struct spi_master *master = dev_get_drvdata(dev);
  648. struct orion_spi *spi = spi_master_get_devdata(master);
  649. if (!IS_ERR(spi->axi_clk))
  650. clk_prepare_enable(spi->axi_clk);
  651. return clk_prepare_enable(spi->clk);
  652. }
  653. #endif
  654. static const struct dev_pm_ops orion_spi_pm_ops = {
  655. SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
  656. orion_spi_runtime_resume,
  657. NULL)
  658. };
  659. static struct platform_driver orion_spi_driver = {
  660. .driver = {
  661. .name = DRIVER_NAME,
  662. .pm = &orion_spi_pm_ops,
  663. .of_match_table = of_match_ptr(orion_spi_of_match_table),
  664. },
  665. .probe = orion_spi_probe,
  666. .remove = orion_spi_remove,
  667. };
  668. module_platform_driver(orion_spi_driver);
  669. MODULE_DESCRIPTION("Orion SPI driver");
  670. MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
  671. MODULE_LICENSE("GPL");