spi-omap2-mcspi.c 40 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * OMAP2 McSPI controller driver
  4. *
  5. * Copyright (C) 2005, 2006 Nokia Corporation
  6. * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
  7. * Juha Yrj�l� <juha.yrjola@nokia.com>
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/module.h>
  12. #include <linux/device.h>
  13. #include <linux/delay.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/dmaengine.h>
  16. #include <linux/pinctrl/consumer.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/err.h>
  19. #include <linux/clk.h>
  20. #include <linux/io.h>
  21. #include <linux/slab.h>
  22. #include <linux/pm_runtime.h>
  23. #include <linux/of.h>
  24. #include <linux/of_device.h>
  25. #include <linux/gcd.h>
  26. #include <linux/spi/spi.h>
  27. #include <linux/platform_data/spi-omap2-mcspi.h>
  28. #define OMAP2_MCSPI_MAX_FREQ 48000000
  29. #define OMAP2_MCSPI_MAX_DIVIDER 4096
  30. #define OMAP2_MCSPI_MAX_FIFODEPTH 64
  31. #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
  32. #define SPI_AUTOSUSPEND_TIMEOUT 2000
  33. #define OMAP2_MCSPI_REVISION 0x00
  34. #define OMAP2_MCSPI_SYSSTATUS 0x14
  35. #define OMAP2_MCSPI_IRQSTATUS 0x18
  36. #define OMAP2_MCSPI_IRQENABLE 0x1c
  37. #define OMAP2_MCSPI_WAKEUPENABLE 0x20
  38. #define OMAP2_MCSPI_SYST 0x24
  39. #define OMAP2_MCSPI_MODULCTRL 0x28
  40. #define OMAP2_MCSPI_XFERLEVEL 0x7c
  41. /* per-channel banks, 0x14 bytes each, first is: */
  42. #define OMAP2_MCSPI_CHCONF0 0x2c
  43. #define OMAP2_MCSPI_CHSTAT0 0x30
  44. #define OMAP2_MCSPI_CHCTRL0 0x34
  45. #define OMAP2_MCSPI_TX0 0x38
  46. #define OMAP2_MCSPI_RX0 0x3c
  47. /* per-register bitmasks: */
  48. #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
  49. #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
  50. #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
  51. #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
  52. #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
  53. #define OMAP2_MCSPI_CHCONF_POL BIT(1)
  54. #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
  55. #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
  56. #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
  57. #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
  58. #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
  59. #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
  60. #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
  61. #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
  62. #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
  63. #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
  64. #define OMAP2_MCSPI_CHCONF_IS BIT(18)
  65. #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
  66. #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
  67. #define OMAP2_MCSPI_CHCONF_FFET BIT(27)
  68. #define OMAP2_MCSPI_CHCONF_FFER BIT(28)
  69. #define OMAP2_MCSPI_CHCONF_CLKG BIT(29)
  70. #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
  71. #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
  72. #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
  73. #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
  74. #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
  75. #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8)
  76. #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
  77. /* We have 2 DMA channels per CS, one for RX and one for TX */
  78. struct omap2_mcspi_dma {
  79. struct dma_chan *dma_tx;
  80. struct dma_chan *dma_rx;
  81. struct completion dma_tx_completion;
  82. struct completion dma_rx_completion;
  83. char dma_rx_ch_name[14];
  84. char dma_tx_ch_name[14];
  85. };
  86. /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
  87. * cache operations; better heuristics consider wordsize and bitrate.
  88. */
  89. #define DMA_MIN_BYTES 160
  90. /*
  91. * Used for context save and restore, structure members to be updated whenever
  92. * corresponding registers are modified.
  93. */
  94. struct omap2_mcspi_regs {
  95. u32 modulctrl;
  96. u32 wakeupenable;
  97. struct list_head cs;
  98. };
  99. struct omap2_mcspi {
  100. struct completion txdone;
  101. struct spi_master *master;
  102. /* Virtual base address of the controller */
  103. void __iomem *base;
  104. unsigned long phys;
  105. /* SPI1 has 4 channels, while SPI2 has 2 */
  106. struct omap2_mcspi_dma *dma_channels;
  107. struct device *dev;
  108. struct omap2_mcspi_regs ctx;
  109. int fifo_depth;
  110. bool slave_aborted;
  111. unsigned int pin_dir:1;
  112. size_t max_xfer_len;
  113. };
  114. struct omap2_mcspi_cs {
  115. void __iomem *base;
  116. unsigned long phys;
  117. int word_len;
  118. u16 mode;
  119. struct list_head node;
  120. /* Context save and restore shadow register */
  121. u32 chconf0, chctrl0;
  122. };
  123. static inline void mcspi_write_reg(struct spi_master *master,
  124. int idx, u32 val)
  125. {
  126. struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
  127. writel_relaxed(val, mcspi->base + idx);
  128. }
  129. static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
  130. {
  131. struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
  132. return readl_relaxed(mcspi->base + idx);
  133. }
  134. static inline void mcspi_write_cs_reg(const struct spi_device *spi,
  135. int idx, u32 val)
  136. {
  137. struct omap2_mcspi_cs *cs = spi->controller_state;
  138. writel_relaxed(val, cs->base + idx);
  139. }
  140. static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
  141. {
  142. struct omap2_mcspi_cs *cs = spi->controller_state;
  143. return readl_relaxed(cs->base + idx);
  144. }
  145. static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
  146. {
  147. struct omap2_mcspi_cs *cs = spi->controller_state;
  148. return cs->chconf0;
  149. }
  150. static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
  151. {
  152. struct omap2_mcspi_cs *cs = spi->controller_state;
  153. cs->chconf0 = val;
  154. mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
  155. mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
  156. }
  157. static inline int mcspi_bytes_per_word(int word_len)
  158. {
  159. if (word_len <= 8)
  160. return 1;
  161. else if (word_len <= 16)
  162. return 2;
  163. else /* word_len <= 32 */
  164. return 4;
  165. }
  166. static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
  167. int is_read, int enable)
  168. {
  169. u32 l, rw;
  170. l = mcspi_cached_chconf0(spi);
  171. if (is_read) /* 1 is read, 0 write */
  172. rw = OMAP2_MCSPI_CHCONF_DMAR;
  173. else
  174. rw = OMAP2_MCSPI_CHCONF_DMAW;
  175. if (enable)
  176. l |= rw;
  177. else
  178. l &= ~rw;
  179. mcspi_write_chconf0(spi, l);
  180. }
  181. static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
  182. {
  183. struct omap2_mcspi_cs *cs = spi->controller_state;
  184. u32 l;
  185. l = cs->chctrl0;
  186. if (enable)
  187. l |= OMAP2_MCSPI_CHCTRL_EN;
  188. else
  189. l &= ~OMAP2_MCSPI_CHCTRL_EN;
  190. cs->chctrl0 = l;
  191. mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
  192. /* Flash post-writes */
  193. mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
  194. }
  195. static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
  196. {
  197. struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
  198. u32 l;
  199. /* The controller handles the inverted chip selects
  200. * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
  201. * the inversion from the core spi_set_cs function.
  202. */
  203. if (spi->mode & SPI_CS_HIGH)
  204. enable = !enable;
  205. if (spi->controller_state) {
  206. int err = pm_runtime_get_sync(mcspi->dev);
  207. if (err < 0) {
  208. pm_runtime_put_noidle(mcspi->dev);
  209. dev_err(mcspi->dev, "failed to get sync: %d\n", err);
  210. return;
  211. }
  212. l = mcspi_cached_chconf0(spi);
  213. if (enable)
  214. l &= ~OMAP2_MCSPI_CHCONF_FORCE;
  215. else
  216. l |= OMAP2_MCSPI_CHCONF_FORCE;
  217. mcspi_write_chconf0(spi, l);
  218. pm_runtime_mark_last_busy(mcspi->dev);
  219. pm_runtime_put_autosuspend(mcspi->dev);
  220. }
  221. }
  222. static void omap2_mcspi_set_mode(struct spi_master *master)
  223. {
  224. struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
  225. struct omap2_mcspi_regs *ctx = &mcspi->ctx;
  226. u32 l;
  227. /*
  228. * Choose master or slave mode
  229. */
  230. l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
  231. l &= ~(OMAP2_MCSPI_MODULCTRL_STEST);
  232. if (spi_controller_is_slave(master)) {
  233. l |= (OMAP2_MCSPI_MODULCTRL_MS);
  234. } else {
  235. l &= ~(OMAP2_MCSPI_MODULCTRL_MS);
  236. l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
  237. }
  238. mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
  239. ctx->modulctrl = l;
  240. }
  241. static void omap2_mcspi_set_fifo(const struct spi_device *spi,
  242. struct spi_transfer *t, int enable)
  243. {
  244. struct spi_master *master = spi->master;
  245. struct omap2_mcspi_cs *cs = spi->controller_state;
  246. struct omap2_mcspi *mcspi;
  247. unsigned int wcnt;
  248. int max_fifo_depth, bytes_per_word;
  249. u32 chconf, xferlevel;
  250. mcspi = spi_master_get_devdata(master);
  251. chconf = mcspi_cached_chconf0(spi);
  252. if (enable) {
  253. bytes_per_word = mcspi_bytes_per_word(cs->word_len);
  254. if (t->len % bytes_per_word != 0)
  255. goto disable_fifo;
  256. if (t->rx_buf != NULL && t->tx_buf != NULL)
  257. max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
  258. else
  259. max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
  260. wcnt = t->len / bytes_per_word;
  261. if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
  262. goto disable_fifo;
  263. xferlevel = wcnt << 16;
  264. if (t->rx_buf != NULL) {
  265. chconf |= OMAP2_MCSPI_CHCONF_FFER;
  266. xferlevel |= (bytes_per_word - 1) << 8;
  267. }
  268. if (t->tx_buf != NULL) {
  269. chconf |= OMAP2_MCSPI_CHCONF_FFET;
  270. xferlevel |= bytes_per_word - 1;
  271. }
  272. mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
  273. mcspi_write_chconf0(spi, chconf);
  274. mcspi->fifo_depth = max_fifo_depth;
  275. return;
  276. }
  277. disable_fifo:
  278. if (t->rx_buf != NULL)
  279. chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
  280. if (t->tx_buf != NULL)
  281. chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
  282. mcspi_write_chconf0(spi, chconf);
  283. mcspi->fifo_depth = 0;
  284. }
  285. static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
  286. {
  287. unsigned long timeout;
  288. timeout = jiffies + msecs_to_jiffies(1000);
  289. while (!(readl_relaxed(reg) & bit)) {
  290. if (time_after(jiffies, timeout)) {
  291. if (!(readl_relaxed(reg) & bit))
  292. return -ETIMEDOUT;
  293. else
  294. return 0;
  295. }
  296. cpu_relax();
  297. }
  298. return 0;
  299. }
  300. static int mcspi_wait_for_completion(struct omap2_mcspi *mcspi,
  301. struct completion *x)
  302. {
  303. if (spi_controller_is_slave(mcspi->master)) {
  304. if (wait_for_completion_interruptible(x) ||
  305. mcspi->slave_aborted)
  306. return -EINTR;
  307. } else {
  308. wait_for_completion(x);
  309. }
  310. return 0;
  311. }
  312. static void omap2_mcspi_rx_callback(void *data)
  313. {
  314. struct spi_device *spi = data;
  315. struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
  316. struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
  317. /* We must disable the DMA RX request */
  318. omap2_mcspi_set_dma_req(spi, 1, 0);
  319. complete(&mcspi_dma->dma_rx_completion);
  320. }
  321. static void omap2_mcspi_tx_callback(void *data)
  322. {
  323. struct spi_device *spi = data;
  324. struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
  325. struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
  326. /* We must disable the DMA TX request */
  327. omap2_mcspi_set_dma_req(spi, 0, 0);
  328. complete(&mcspi_dma->dma_tx_completion);
  329. }
  330. static void omap2_mcspi_tx_dma(struct spi_device *spi,
  331. struct spi_transfer *xfer,
  332. struct dma_slave_config cfg)
  333. {
  334. struct omap2_mcspi *mcspi;
  335. struct omap2_mcspi_dma *mcspi_dma;
  336. struct dma_async_tx_descriptor *tx;
  337. mcspi = spi_master_get_devdata(spi->master);
  338. mcspi_dma = &mcspi->dma_channels[spi->chip_select];
  339. dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
  340. tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
  341. xfer->tx_sg.nents,
  342. DMA_MEM_TO_DEV,
  343. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  344. if (tx) {
  345. tx->callback = omap2_mcspi_tx_callback;
  346. tx->callback_param = spi;
  347. dmaengine_submit(tx);
  348. } else {
  349. /* FIXME: fall back to PIO? */
  350. }
  351. dma_async_issue_pending(mcspi_dma->dma_tx);
  352. omap2_mcspi_set_dma_req(spi, 0, 1);
  353. }
  354. static unsigned
  355. omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
  356. struct dma_slave_config cfg,
  357. unsigned es)
  358. {
  359. struct omap2_mcspi *mcspi;
  360. struct omap2_mcspi_dma *mcspi_dma;
  361. unsigned int count, transfer_reduction = 0;
  362. struct scatterlist *sg_out[2];
  363. int nb_sizes = 0, out_mapped_nents[2], ret, x;
  364. size_t sizes[2];
  365. u32 l;
  366. int elements = 0;
  367. int word_len, element_count;
  368. struct omap2_mcspi_cs *cs = spi->controller_state;
  369. void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
  370. struct dma_async_tx_descriptor *tx;
  371. mcspi = spi_master_get_devdata(spi->master);
  372. mcspi_dma = &mcspi->dma_channels[spi->chip_select];
  373. count = xfer->len;
  374. /*
  375. * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM
  376. * it mentions reducing DMA transfer length by one element in master
  377. * normal mode.
  378. */
  379. if (mcspi->fifo_depth == 0)
  380. transfer_reduction = es;
  381. word_len = cs->word_len;
  382. l = mcspi_cached_chconf0(spi);
  383. if (word_len <= 8)
  384. element_count = count;
  385. else if (word_len <= 16)
  386. element_count = count >> 1;
  387. else /* word_len <= 32 */
  388. element_count = count >> 2;
  389. dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
  390. /*
  391. * Reduce DMA transfer length by one more if McSPI is
  392. * configured in turbo mode.
  393. */
  394. if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
  395. transfer_reduction += es;
  396. if (transfer_reduction) {
  397. /* Split sgl into two. The second sgl won't be used. */
  398. sizes[0] = count - transfer_reduction;
  399. sizes[1] = transfer_reduction;
  400. nb_sizes = 2;
  401. } else {
  402. /*
  403. * Don't bother splitting the sgl. This essentially
  404. * clones the original sgl.
  405. */
  406. sizes[0] = count;
  407. nb_sizes = 1;
  408. }
  409. ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents, 0, nb_sizes,
  410. sizes, sg_out, out_mapped_nents, GFP_KERNEL);
  411. if (ret < 0) {
  412. dev_err(&spi->dev, "sg_split failed\n");
  413. return 0;
  414. }
  415. tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, sg_out[0],
  416. out_mapped_nents[0], DMA_DEV_TO_MEM,
  417. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  418. if (tx) {
  419. tx->callback = omap2_mcspi_rx_callback;
  420. tx->callback_param = spi;
  421. dmaengine_submit(tx);
  422. } else {
  423. /* FIXME: fall back to PIO? */
  424. }
  425. dma_async_issue_pending(mcspi_dma->dma_rx);
  426. omap2_mcspi_set_dma_req(spi, 1, 1);
  427. ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_rx_completion);
  428. if (ret || mcspi->slave_aborted) {
  429. dmaengine_terminate_sync(mcspi_dma->dma_rx);
  430. omap2_mcspi_set_dma_req(spi, 1, 0);
  431. return 0;
  432. }
  433. for (x = 0; x < nb_sizes; x++)
  434. kfree(sg_out[x]);
  435. if (mcspi->fifo_depth > 0)
  436. return count;
  437. /*
  438. * Due to the DMA transfer length reduction the missing bytes must
  439. * be read manually to receive all of the expected data.
  440. */
  441. omap2_mcspi_set_enable(spi, 0);
  442. elements = element_count - 1;
  443. if (l & OMAP2_MCSPI_CHCONF_TURBO) {
  444. elements--;
  445. if (!mcspi_wait_for_reg_bit(chstat_reg,
  446. OMAP2_MCSPI_CHSTAT_RXS)) {
  447. u32 w;
  448. w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
  449. if (word_len <= 8)
  450. ((u8 *)xfer->rx_buf)[elements++] = w;
  451. else if (word_len <= 16)
  452. ((u16 *)xfer->rx_buf)[elements++] = w;
  453. else /* word_len <= 32 */
  454. ((u32 *)xfer->rx_buf)[elements++] = w;
  455. } else {
  456. int bytes_per_word = mcspi_bytes_per_word(word_len);
  457. dev_err(&spi->dev, "DMA RX penultimate word empty\n");
  458. count -= (bytes_per_word << 1);
  459. omap2_mcspi_set_enable(spi, 1);
  460. return count;
  461. }
  462. }
  463. if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) {
  464. u32 w;
  465. w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
  466. if (word_len <= 8)
  467. ((u8 *)xfer->rx_buf)[elements] = w;
  468. else if (word_len <= 16)
  469. ((u16 *)xfer->rx_buf)[elements] = w;
  470. else /* word_len <= 32 */
  471. ((u32 *)xfer->rx_buf)[elements] = w;
  472. } else {
  473. dev_err(&spi->dev, "DMA RX last word empty\n");
  474. count -= mcspi_bytes_per_word(word_len);
  475. }
  476. omap2_mcspi_set_enable(spi, 1);
  477. return count;
  478. }
  479. static unsigned
  480. omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
  481. {
  482. struct omap2_mcspi *mcspi;
  483. struct omap2_mcspi_cs *cs = spi->controller_state;
  484. struct omap2_mcspi_dma *mcspi_dma;
  485. unsigned int count;
  486. u8 *rx;
  487. const u8 *tx;
  488. struct dma_slave_config cfg;
  489. enum dma_slave_buswidth width;
  490. unsigned es;
  491. void __iomem *chstat_reg;
  492. void __iomem *irqstat_reg;
  493. int wait_res;
  494. mcspi = spi_master_get_devdata(spi->master);
  495. mcspi_dma = &mcspi->dma_channels[spi->chip_select];
  496. if (cs->word_len <= 8) {
  497. width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  498. es = 1;
  499. } else if (cs->word_len <= 16) {
  500. width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  501. es = 2;
  502. } else {
  503. width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  504. es = 4;
  505. }
  506. count = xfer->len;
  507. memset(&cfg, 0, sizeof(cfg));
  508. cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
  509. cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
  510. cfg.src_addr_width = width;
  511. cfg.dst_addr_width = width;
  512. cfg.src_maxburst = 1;
  513. cfg.dst_maxburst = 1;
  514. rx = xfer->rx_buf;
  515. tx = xfer->tx_buf;
  516. mcspi->slave_aborted = false;
  517. reinit_completion(&mcspi_dma->dma_tx_completion);
  518. reinit_completion(&mcspi_dma->dma_rx_completion);
  519. reinit_completion(&mcspi->txdone);
  520. if (tx) {
  521. /* Enable EOW IRQ to know end of tx in slave mode */
  522. if (spi_controller_is_slave(spi->master))
  523. mcspi_write_reg(spi->master,
  524. OMAP2_MCSPI_IRQENABLE,
  525. OMAP2_MCSPI_IRQSTATUS_EOW);
  526. omap2_mcspi_tx_dma(spi, xfer, cfg);
  527. }
  528. if (rx != NULL)
  529. count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
  530. if (tx != NULL) {
  531. int ret;
  532. ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_tx_completion);
  533. if (ret || mcspi->slave_aborted) {
  534. dmaengine_terminate_sync(mcspi_dma->dma_tx);
  535. omap2_mcspi_set_dma_req(spi, 0, 0);
  536. return 0;
  537. }
  538. if (spi_controller_is_slave(mcspi->master)) {
  539. ret = mcspi_wait_for_completion(mcspi, &mcspi->txdone);
  540. if (ret || mcspi->slave_aborted)
  541. return 0;
  542. }
  543. if (mcspi->fifo_depth > 0) {
  544. irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
  545. if (mcspi_wait_for_reg_bit(irqstat_reg,
  546. OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
  547. dev_err(&spi->dev, "EOW timed out\n");
  548. mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
  549. OMAP2_MCSPI_IRQSTATUS_EOW);
  550. }
  551. /* for TX_ONLY mode, be sure all words have shifted out */
  552. if (rx == NULL) {
  553. chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
  554. if (mcspi->fifo_depth > 0) {
  555. wait_res = mcspi_wait_for_reg_bit(chstat_reg,
  556. OMAP2_MCSPI_CHSTAT_TXFFE);
  557. if (wait_res < 0)
  558. dev_err(&spi->dev, "TXFFE timed out\n");
  559. } else {
  560. wait_res = mcspi_wait_for_reg_bit(chstat_reg,
  561. OMAP2_MCSPI_CHSTAT_TXS);
  562. if (wait_res < 0)
  563. dev_err(&spi->dev, "TXS timed out\n");
  564. }
  565. if (wait_res >= 0 &&
  566. (mcspi_wait_for_reg_bit(chstat_reg,
  567. OMAP2_MCSPI_CHSTAT_EOT) < 0))
  568. dev_err(&spi->dev, "EOT timed out\n");
  569. }
  570. }
  571. return count;
  572. }
  573. static unsigned
  574. omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
  575. {
  576. struct omap2_mcspi_cs *cs = spi->controller_state;
  577. unsigned int count, c;
  578. u32 l;
  579. void __iomem *base = cs->base;
  580. void __iomem *tx_reg;
  581. void __iomem *rx_reg;
  582. void __iomem *chstat_reg;
  583. int word_len;
  584. count = xfer->len;
  585. c = count;
  586. word_len = cs->word_len;
  587. l = mcspi_cached_chconf0(spi);
  588. /* We store the pre-calculated register addresses on stack to speed
  589. * up the transfer loop. */
  590. tx_reg = base + OMAP2_MCSPI_TX0;
  591. rx_reg = base + OMAP2_MCSPI_RX0;
  592. chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
  593. if (c < (word_len>>3))
  594. return 0;
  595. if (word_len <= 8) {
  596. u8 *rx;
  597. const u8 *tx;
  598. rx = xfer->rx_buf;
  599. tx = xfer->tx_buf;
  600. do {
  601. c -= 1;
  602. if (tx != NULL) {
  603. if (mcspi_wait_for_reg_bit(chstat_reg,
  604. OMAP2_MCSPI_CHSTAT_TXS) < 0) {
  605. dev_err(&spi->dev, "TXS timed out\n");
  606. goto out;
  607. }
  608. dev_vdbg(&spi->dev, "write-%d %02x\n",
  609. word_len, *tx);
  610. writel_relaxed(*tx++, tx_reg);
  611. }
  612. if (rx != NULL) {
  613. if (mcspi_wait_for_reg_bit(chstat_reg,
  614. OMAP2_MCSPI_CHSTAT_RXS) < 0) {
  615. dev_err(&spi->dev, "RXS timed out\n");
  616. goto out;
  617. }
  618. if (c == 1 && tx == NULL &&
  619. (l & OMAP2_MCSPI_CHCONF_TURBO)) {
  620. omap2_mcspi_set_enable(spi, 0);
  621. *rx++ = readl_relaxed(rx_reg);
  622. dev_vdbg(&spi->dev, "read-%d %02x\n",
  623. word_len, *(rx - 1));
  624. if (mcspi_wait_for_reg_bit(chstat_reg,
  625. OMAP2_MCSPI_CHSTAT_RXS) < 0) {
  626. dev_err(&spi->dev,
  627. "RXS timed out\n");
  628. goto out;
  629. }
  630. c = 0;
  631. } else if (c == 0 && tx == NULL) {
  632. omap2_mcspi_set_enable(spi, 0);
  633. }
  634. *rx++ = readl_relaxed(rx_reg);
  635. dev_vdbg(&spi->dev, "read-%d %02x\n",
  636. word_len, *(rx - 1));
  637. }
  638. } while (c);
  639. } else if (word_len <= 16) {
  640. u16 *rx;
  641. const u16 *tx;
  642. rx = xfer->rx_buf;
  643. tx = xfer->tx_buf;
  644. do {
  645. c -= 2;
  646. if (tx != NULL) {
  647. if (mcspi_wait_for_reg_bit(chstat_reg,
  648. OMAP2_MCSPI_CHSTAT_TXS) < 0) {
  649. dev_err(&spi->dev, "TXS timed out\n");
  650. goto out;
  651. }
  652. dev_vdbg(&spi->dev, "write-%d %04x\n",
  653. word_len, *tx);
  654. writel_relaxed(*tx++, tx_reg);
  655. }
  656. if (rx != NULL) {
  657. if (mcspi_wait_for_reg_bit(chstat_reg,
  658. OMAP2_MCSPI_CHSTAT_RXS) < 0) {
  659. dev_err(&spi->dev, "RXS timed out\n");
  660. goto out;
  661. }
  662. if (c == 2 && tx == NULL &&
  663. (l & OMAP2_MCSPI_CHCONF_TURBO)) {
  664. omap2_mcspi_set_enable(spi, 0);
  665. *rx++ = readl_relaxed(rx_reg);
  666. dev_vdbg(&spi->dev, "read-%d %04x\n",
  667. word_len, *(rx - 1));
  668. if (mcspi_wait_for_reg_bit(chstat_reg,
  669. OMAP2_MCSPI_CHSTAT_RXS) < 0) {
  670. dev_err(&spi->dev,
  671. "RXS timed out\n");
  672. goto out;
  673. }
  674. c = 0;
  675. } else if (c == 0 && tx == NULL) {
  676. omap2_mcspi_set_enable(spi, 0);
  677. }
  678. *rx++ = readl_relaxed(rx_reg);
  679. dev_vdbg(&spi->dev, "read-%d %04x\n",
  680. word_len, *(rx - 1));
  681. }
  682. } while (c >= 2);
  683. } else if (word_len <= 32) {
  684. u32 *rx;
  685. const u32 *tx;
  686. rx = xfer->rx_buf;
  687. tx = xfer->tx_buf;
  688. do {
  689. c -= 4;
  690. if (tx != NULL) {
  691. if (mcspi_wait_for_reg_bit(chstat_reg,
  692. OMAP2_MCSPI_CHSTAT_TXS) < 0) {
  693. dev_err(&spi->dev, "TXS timed out\n");
  694. goto out;
  695. }
  696. dev_vdbg(&spi->dev, "write-%d %08x\n",
  697. word_len, *tx);
  698. writel_relaxed(*tx++, tx_reg);
  699. }
  700. if (rx != NULL) {
  701. if (mcspi_wait_for_reg_bit(chstat_reg,
  702. OMAP2_MCSPI_CHSTAT_RXS) < 0) {
  703. dev_err(&spi->dev, "RXS timed out\n");
  704. goto out;
  705. }
  706. if (c == 4 && tx == NULL &&
  707. (l & OMAP2_MCSPI_CHCONF_TURBO)) {
  708. omap2_mcspi_set_enable(spi, 0);
  709. *rx++ = readl_relaxed(rx_reg);
  710. dev_vdbg(&spi->dev, "read-%d %08x\n",
  711. word_len, *(rx - 1));
  712. if (mcspi_wait_for_reg_bit(chstat_reg,
  713. OMAP2_MCSPI_CHSTAT_RXS) < 0) {
  714. dev_err(&spi->dev,
  715. "RXS timed out\n");
  716. goto out;
  717. }
  718. c = 0;
  719. } else if (c == 0 && tx == NULL) {
  720. omap2_mcspi_set_enable(spi, 0);
  721. }
  722. *rx++ = readl_relaxed(rx_reg);
  723. dev_vdbg(&spi->dev, "read-%d %08x\n",
  724. word_len, *(rx - 1));
  725. }
  726. } while (c >= 4);
  727. }
  728. /* for TX_ONLY mode, be sure all words have shifted out */
  729. if (xfer->rx_buf == NULL) {
  730. if (mcspi_wait_for_reg_bit(chstat_reg,
  731. OMAP2_MCSPI_CHSTAT_TXS) < 0) {
  732. dev_err(&spi->dev, "TXS timed out\n");
  733. } else if (mcspi_wait_for_reg_bit(chstat_reg,
  734. OMAP2_MCSPI_CHSTAT_EOT) < 0)
  735. dev_err(&spi->dev, "EOT timed out\n");
  736. /* disable chan to purge rx datas received in TX_ONLY transfer,
  737. * otherwise these rx datas will affect the direct following
  738. * RX_ONLY transfer.
  739. */
  740. omap2_mcspi_set_enable(spi, 0);
  741. }
  742. out:
  743. omap2_mcspi_set_enable(spi, 1);
  744. return count - c;
  745. }
  746. static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
  747. {
  748. u32 div;
  749. for (div = 0; div < 15; div++)
  750. if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
  751. return div;
  752. return 15;
  753. }
  754. /* called only when no transfer is active to this device */
  755. static int omap2_mcspi_setup_transfer(struct spi_device *spi,
  756. struct spi_transfer *t)
  757. {
  758. struct omap2_mcspi_cs *cs = spi->controller_state;
  759. struct omap2_mcspi *mcspi;
  760. u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
  761. u8 word_len = spi->bits_per_word;
  762. u32 speed_hz = spi->max_speed_hz;
  763. mcspi = spi_master_get_devdata(spi->master);
  764. if (t != NULL && t->bits_per_word)
  765. word_len = t->bits_per_word;
  766. cs->word_len = word_len;
  767. if (t && t->speed_hz)
  768. speed_hz = t->speed_hz;
  769. speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
  770. if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
  771. clkd = omap2_mcspi_calc_divisor(speed_hz);
  772. speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
  773. clkg = 0;
  774. } else {
  775. div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
  776. speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
  777. clkd = (div - 1) & 0xf;
  778. extclk = (div - 1) >> 4;
  779. clkg = OMAP2_MCSPI_CHCONF_CLKG;
  780. }
  781. l = mcspi_cached_chconf0(spi);
  782. /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
  783. * REVISIT: this controller could support SPI_3WIRE mode.
  784. */
  785. if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
  786. l &= ~OMAP2_MCSPI_CHCONF_IS;
  787. l &= ~OMAP2_MCSPI_CHCONF_DPE1;
  788. l |= OMAP2_MCSPI_CHCONF_DPE0;
  789. } else {
  790. l |= OMAP2_MCSPI_CHCONF_IS;
  791. l |= OMAP2_MCSPI_CHCONF_DPE1;
  792. l &= ~OMAP2_MCSPI_CHCONF_DPE0;
  793. }
  794. /* wordlength */
  795. l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
  796. l |= (word_len - 1) << 7;
  797. /* set chipselect polarity; manage with FORCE */
  798. if (!(spi->mode & SPI_CS_HIGH))
  799. l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
  800. else
  801. l &= ~OMAP2_MCSPI_CHCONF_EPOL;
  802. /* set clock divisor */
  803. l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
  804. l |= clkd << 2;
  805. /* set clock granularity */
  806. l &= ~OMAP2_MCSPI_CHCONF_CLKG;
  807. l |= clkg;
  808. if (clkg) {
  809. cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
  810. cs->chctrl0 |= extclk << 8;
  811. mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
  812. }
  813. /* set SPI mode 0..3 */
  814. if (spi->mode & SPI_CPOL)
  815. l |= OMAP2_MCSPI_CHCONF_POL;
  816. else
  817. l &= ~OMAP2_MCSPI_CHCONF_POL;
  818. if (spi->mode & SPI_CPHA)
  819. l |= OMAP2_MCSPI_CHCONF_PHA;
  820. else
  821. l &= ~OMAP2_MCSPI_CHCONF_PHA;
  822. mcspi_write_chconf0(spi, l);
  823. cs->mode = spi->mode;
  824. dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
  825. speed_hz,
  826. (spi->mode & SPI_CPHA) ? "trailing" : "leading",
  827. (spi->mode & SPI_CPOL) ? "inverted" : "normal");
  828. return 0;
  829. }
  830. /*
  831. * Note that we currently allow DMA only if we get a channel
  832. * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
  833. */
  834. static int omap2_mcspi_request_dma(struct omap2_mcspi *mcspi,
  835. struct omap2_mcspi_dma *mcspi_dma)
  836. {
  837. int ret = 0;
  838. mcspi_dma->dma_rx = dma_request_chan(mcspi->dev,
  839. mcspi_dma->dma_rx_ch_name);
  840. if (IS_ERR(mcspi_dma->dma_rx)) {
  841. ret = PTR_ERR(mcspi_dma->dma_rx);
  842. mcspi_dma->dma_rx = NULL;
  843. goto no_dma;
  844. }
  845. mcspi_dma->dma_tx = dma_request_chan(mcspi->dev,
  846. mcspi_dma->dma_tx_ch_name);
  847. if (IS_ERR(mcspi_dma->dma_tx)) {
  848. ret = PTR_ERR(mcspi_dma->dma_tx);
  849. mcspi_dma->dma_tx = NULL;
  850. dma_release_channel(mcspi_dma->dma_rx);
  851. mcspi_dma->dma_rx = NULL;
  852. }
  853. init_completion(&mcspi_dma->dma_rx_completion);
  854. init_completion(&mcspi_dma->dma_tx_completion);
  855. no_dma:
  856. return ret;
  857. }
  858. static void omap2_mcspi_release_dma(struct spi_master *master)
  859. {
  860. struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
  861. struct omap2_mcspi_dma *mcspi_dma;
  862. int i;
  863. for (i = 0; i < master->num_chipselect; i++) {
  864. mcspi_dma = &mcspi->dma_channels[i];
  865. if (mcspi_dma->dma_rx) {
  866. dma_release_channel(mcspi_dma->dma_rx);
  867. mcspi_dma->dma_rx = NULL;
  868. }
  869. if (mcspi_dma->dma_tx) {
  870. dma_release_channel(mcspi_dma->dma_tx);
  871. mcspi_dma->dma_tx = NULL;
  872. }
  873. }
  874. }
  875. static void omap2_mcspi_cleanup(struct spi_device *spi)
  876. {
  877. struct omap2_mcspi_cs *cs;
  878. if (spi->controller_state) {
  879. /* Unlink controller state from context save list */
  880. cs = spi->controller_state;
  881. list_del(&cs->node);
  882. kfree(cs);
  883. }
  884. }
  885. static int omap2_mcspi_setup(struct spi_device *spi)
  886. {
  887. bool initial_setup = false;
  888. int ret;
  889. struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
  890. struct omap2_mcspi_regs *ctx = &mcspi->ctx;
  891. struct omap2_mcspi_cs *cs = spi->controller_state;
  892. if (!cs) {
  893. cs = kzalloc(sizeof *cs, GFP_KERNEL);
  894. if (!cs)
  895. return -ENOMEM;
  896. cs->base = mcspi->base + spi->chip_select * 0x14;
  897. cs->phys = mcspi->phys + spi->chip_select * 0x14;
  898. cs->mode = 0;
  899. cs->chconf0 = 0;
  900. cs->chctrl0 = 0;
  901. spi->controller_state = cs;
  902. /* Link this to context save list */
  903. list_add_tail(&cs->node, &ctx->cs);
  904. initial_setup = true;
  905. }
  906. ret = pm_runtime_get_sync(mcspi->dev);
  907. if (ret < 0) {
  908. pm_runtime_put_noidle(mcspi->dev);
  909. if (initial_setup)
  910. omap2_mcspi_cleanup(spi);
  911. return ret;
  912. }
  913. ret = omap2_mcspi_setup_transfer(spi, NULL);
  914. if (ret && initial_setup)
  915. omap2_mcspi_cleanup(spi);
  916. pm_runtime_mark_last_busy(mcspi->dev);
  917. pm_runtime_put_autosuspend(mcspi->dev);
  918. return ret;
  919. }
  920. static irqreturn_t omap2_mcspi_irq_handler(int irq, void *data)
  921. {
  922. struct omap2_mcspi *mcspi = data;
  923. u32 irqstat;
  924. irqstat = mcspi_read_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS);
  925. if (!irqstat)
  926. return IRQ_NONE;
  927. /* Disable IRQ and wakeup slave xfer task */
  928. mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQENABLE, 0);
  929. if (irqstat & OMAP2_MCSPI_IRQSTATUS_EOW)
  930. complete(&mcspi->txdone);
  931. return IRQ_HANDLED;
  932. }
  933. static int omap2_mcspi_slave_abort(struct spi_master *master)
  934. {
  935. struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
  936. struct omap2_mcspi_dma *mcspi_dma = mcspi->dma_channels;
  937. mcspi->slave_aborted = true;
  938. complete(&mcspi_dma->dma_rx_completion);
  939. complete(&mcspi_dma->dma_tx_completion);
  940. complete(&mcspi->txdone);
  941. return 0;
  942. }
  943. static int omap2_mcspi_transfer_one(struct spi_master *master,
  944. struct spi_device *spi,
  945. struct spi_transfer *t)
  946. {
  947. /* We only enable one channel at a time -- the one whose message is
  948. * -- although this controller would gladly
  949. * arbitrate among multiple channels. This corresponds to "single
  950. * channel" master mode. As a side effect, we need to manage the
  951. * chipselect with the FORCE bit ... CS != channel enable.
  952. */
  953. struct omap2_mcspi *mcspi;
  954. struct omap2_mcspi_dma *mcspi_dma;
  955. struct omap2_mcspi_cs *cs;
  956. struct omap2_mcspi_device_config *cd;
  957. int par_override = 0;
  958. int status = 0;
  959. u32 chconf;
  960. mcspi = spi_master_get_devdata(master);
  961. mcspi_dma = mcspi->dma_channels + spi->chip_select;
  962. cs = spi->controller_state;
  963. cd = spi->controller_data;
  964. /*
  965. * The slave driver could have changed spi->mode in which case
  966. * it will be different from cs->mode (the current hardware setup).
  967. * If so, set par_override (even though its not a parity issue) so
  968. * omap2_mcspi_setup_transfer will be called to configure the hardware
  969. * with the correct mode on the first iteration of the loop below.
  970. */
  971. if (spi->mode != cs->mode)
  972. par_override = 1;
  973. omap2_mcspi_set_enable(spi, 0);
  974. if (spi->cs_gpiod)
  975. omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
  976. if (par_override ||
  977. (t->speed_hz != spi->max_speed_hz) ||
  978. (t->bits_per_word != spi->bits_per_word)) {
  979. par_override = 1;
  980. status = omap2_mcspi_setup_transfer(spi, t);
  981. if (status < 0)
  982. goto out;
  983. if (t->speed_hz == spi->max_speed_hz &&
  984. t->bits_per_word == spi->bits_per_word)
  985. par_override = 0;
  986. }
  987. if (cd && cd->cs_per_word) {
  988. chconf = mcspi->ctx.modulctrl;
  989. chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
  990. mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
  991. mcspi->ctx.modulctrl =
  992. mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
  993. }
  994. chconf = mcspi_cached_chconf0(spi);
  995. chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
  996. chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
  997. if (t->tx_buf == NULL)
  998. chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
  999. else if (t->rx_buf == NULL)
  1000. chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
  1001. if (cd && cd->turbo_mode && t->tx_buf == NULL) {
  1002. /* Turbo mode is for more than one word */
  1003. if (t->len > ((cs->word_len + 7) >> 3))
  1004. chconf |= OMAP2_MCSPI_CHCONF_TURBO;
  1005. }
  1006. mcspi_write_chconf0(spi, chconf);
  1007. if (t->len) {
  1008. unsigned count;
  1009. if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
  1010. master->cur_msg_mapped &&
  1011. master->can_dma(master, spi, t))
  1012. omap2_mcspi_set_fifo(spi, t, 1);
  1013. omap2_mcspi_set_enable(spi, 1);
  1014. /* RX_ONLY mode needs dummy data in TX reg */
  1015. if (t->tx_buf == NULL)
  1016. writel_relaxed(0, cs->base
  1017. + OMAP2_MCSPI_TX0);
  1018. if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
  1019. master->cur_msg_mapped &&
  1020. master->can_dma(master, spi, t))
  1021. count = omap2_mcspi_txrx_dma(spi, t);
  1022. else
  1023. count = omap2_mcspi_txrx_pio(spi, t);
  1024. if (count != t->len) {
  1025. status = -EIO;
  1026. goto out;
  1027. }
  1028. }
  1029. omap2_mcspi_set_enable(spi, 0);
  1030. if (mcspi->fifo_depth > 0)
  1031. omap2_mcspi_set_fifo(spi, t, 0);
  1032. out:
  1033. /* Restore defaults if they were overriden */
  1034. if (par_override) {
  1035. par_override = 0;
  1036. status = omap2_mcspi_setup_transfer(spi, NULL);
  1037. }
  1038. if (cd && cd->cs_per_word) {
  1039. chconf = mcspi->ctx.modulctrl;
  1040. chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
  1041. mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
  1042. mcspi->ctx.modulctrl =
  1043. mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
  1044. }
  1045. omap2_mcspi_set_enable(spi, 0);
  1046. if (spi->cs_gpiod)
  1047. omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
  1048. if (mcspi->fifo_depth > 0 && t)
  1049. omap2_mcspi_set_fifo(spi, t, 0);
  1050. return status;
  1051. }
  1052. static int omap2_mcspi_prepare_message(struct spi_master *master,
  1053. struct spi_message *msg)
  1054. {
  1055. struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
  1056. struct omap2_mcspi_regs *ctx = &mcspi->ctx;
  1057. struct omap2_mcspi_cs *cs;
  1058. /* Only a single channel can have the FORCE bit enabled
  1059. * in its chconf0 register.
  1060. * Scan all channels and disable them except the current one.
  1061. * A FORCE can remain from a last transfer having cs_change enabled
  1062. */
  1063. list_for_each_entry(cs, &ctx->cs, node) {
  1064. if (msg->spi->controller_state == cs)
  1065. continue;
  1066. if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
  1067. cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
  1068. writel_relaxed(cs->chconf0,
  1069. cs->base + OMAP2_MCSPI_CHCONF0);
  1070. readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
  1071. }
  1072. }
  1073. return 0;
  1074. }
  1075. static bool omap2_mcspi_can_dma(struct spi_master *master,
  1076. struct spi_device *spi,
  1077. struct spi_transfer *xfer)
  1078. {
  1079. struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
  1080. struct omap2_mcspi_dma *mcspi_dma =
  1081. &mcspi->dma_channels[spi->chip_select];
  1082. if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx)
  1083. return false;
  1084. if (spi_controller_is_slave(master))
  1085. return true;
  1086. master->dma_rx = mcspi_dma->dma_rx;
  1087. master->dma_tx = mcspi_dma->dma_tx;
  1088. return (xfer->len >= DMA_MIN_BYTES);
  1089. }
  1090. static size_t omap2_mcspi_max_xfer_size(struct spi_device *spi)
  1091. {
  1092. struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
  1093. struct omap2_mcspi_dma *mcspi_dma =
  1094. &mcspi->dma_channels[spi->chip_select];
  1095. if (mcspi->max_xfer_len && mcspi_dma->dma_rx)
  1096. return mcspi->max_xfer_len;
  1097. return SIZE_MAX;
  1098. }
  1099. static int omap2_mcspi_controller_setup(struct omap2_mcspi *mcspi)
  1100. {
  1101. struct spi_master *master = mcspi->master;
  1102. struct omap2_mcspi_regs *ctx = &mcspi->ctx;
  1103. int ret = 0;
  1104. ret = pm_runtime_get_sync(mcspi->dev);
  1105. if (ret < 0) {
  1106. pm_runtime_put_noidle(mcspi->dev);
  1107. return ret;
  1108. }
  1109. mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
  1110. OMAP2_MCSPI_WAKEUPENABLE_WKEN);
  1111. ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
  1112. omap2_mcspi_set_mode(master);
  1113. pm_runtime_mark_last_busy(mcspi->dev);
  1114. pm_runtime_put_autosuspend(mcspi->dev);
  1115. return 0;
  1116. }
  1117. /*
  1118. * When SPI wake up from off-mode, CS is in activate state. If it was in
  1119. * inactive state when driver was suspend, then force it to inactive state at
  1120. * wake up.
  1121. */
  1122. static int omap_mcspi_runtime_resume(struct device *dev)
  1123. {
  1124. struct spi_master *master = dev_get_drvdata(dev);
  1125. struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
  1126. struct omap2_mcspi_regs *ctx = &mcspi->ctx;
  1127. struct omap2_mcspi_cs *cs;
  1128. /* McSPI: context restore */
  1129. mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
  1130. mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
  1131. list_for_each_entry(cs, &ctx->cs, node) {
  1132. /*
  1133. * We need to toggle CS state for OMAP take this
  1134. * change in account.
  1135. */
  1136. if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
  1137. cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
  1138. writel_relaxed(cs->chconf0,
  1139. cs->base + OMAP2_MCSPI_CHCONF0);
  1140. cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
  1141. writel_relaxed(cs->chconf0,
  1142. cs->base + OMAP2_MCSPI_CHCONF0);
  1143. } else {
  1144. writel_relaxed(cs->chconf0,
  1145. cs->base + OMAP2_MCSPI_CHCONF0);
  1146. }
  1147. }
  1148. return 0;
  1149. }
  1150. static struct omap2_mcspi_platform_config omap2_pdata = {
  1151. .regs_offset = 0,
  1152. };
  1153. static struct omap2_mcspi_platform_config omap4_pdata = {
  1154. .regs_offset = OMAP4_MCSPI_REG_OFFSET,
  1155. };
  1156. static struct omap2_mcspi_platform_config am654_pdata = {
  1157. .regs_offset = OMAP4_MCSPI_REG_OFFSET,
  1158. .max_xfer_len = SZ_4K - 1,
  1159. };
  1160. static const struct of_device_id omap_mcspi_of_match[] = {
  1161. {
  1162. .compatible = "ti,omap2-mcspi",
  1163. .data = &omap2_pdata,
  1164. },
  1165. {
  1166. .compatible = "ti,omap4-mcspi",
  1167. .data = &omap4_pdata,
  1168. },
  1169. {
  1170. .compatible = "ti,am654-mcspi",
  1171. .data = &am654_pdata,
  1172. },
  1173. { },
  1174. };
  1175. MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
  1176. static int omap2_mcspi_probe(struct platform_device *pdev)
  1177. {
  1178. struct spi_master *master;
  1179. const struct omap2_mcspi_platform_config *pdata;
  1180. struct omap2_mcspi *mcspi;
  1181. struct resource *r;
  1182. int status = 0, i;
  1183. u32 regs_offset = 0;
  1184. struct device_node *node = pdev->dev.of_node;
  1185. const struct of_device_id *match;
  1186. if (of_property_read_bool(node, "spi-slave"))
  1187. master = spi_alloc_slave(&pdev->dev, sizeof(*mcspi));
  1188. else
  1189. master = spi_alloc_master(&pdev->dev, sizeof(*mcspi));
  1190. if (!master)
  1191. return -ENOMEM;
  1192. /* the spi->mode bits understood by this driver: */
  1193. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
  1194. master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
  1195. master->setup = omap2_mcspi_setup;
  1196. master->auto_runtime_pm = true;
  1197. master->prepare_message = omap2_mcspi_prepare_message;
  1198. master->can_dma = omap2_mcspi_can_dma;
  1199. master->transfer_one = omap2_mcspi_transfer_one;
  1200. master->set_cs = omap2_mcspi_set_cs;
  1201. master->cleanup = omap2_mcspi_cleanup;
  1202. master->slave_abort = omap2_mcspi_slave_abort;
  1203. master->dev.of_node = node;
  1204. master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
  1205. master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
  1206. master->use_gpio_descriptors = true;
  1207. platform_set_drvdata(pdev, master);
  1208. mcspi = spi_master_get_devdata(master);
  1209. mcspi->master = master;
  1210. match = of_match_device(omap_mcspi_of_match, &pdev->dev);
  1211. if (match) {
  1212. u32 num_cs = 1; /* default number of chipselect */
  1213. pdata = match->data;
  1214. of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
  1215. master->num_chipselect = num_cs;
  1216. if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
  1217. mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
  1218. } else {
  1219. pdata = dev_get_platdata(&pdev->dev);
  1220. master->num_chipselect = pdata->num_cs;
  1221. mcspi->pin_dir = pdata->pin_dir;
  1222. }
  1223. regs_offset = pdata->regs_offset;
  1224. if (pdata->max_xfer_len) {
  1225. mcspi->max_xfer_len = pdata->max_xfer_len;
  1226. master->max_transfer_size = omap2_mcspi_max_xfer_size;
  1227. }
  1228. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1229. mcspi->base = devm_ioremap_resource(&pdev->dev, r);
  1230. if (IS_ERR(mcspi->base)) {
  1231. status = PTR_ERR(mcspi->base);
  1232. goto free_master;
  1233. }
  1234. mcspi->phys = r->start + regs_offset;
  1235. mcspi->base += regs_offset;
  1236. mcspi->dev = &pdev->dev;
  1237. INIT_LIST_HEAD(&mcspi->ctx.cs);
  1238. mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
  1239. sizeof(struct omap2_mcspi_dma),
  1240. GFP_KERNEL);
  1241. if (mcspi->dma_channels == NULL) {
  1242. status = -ENOMEM;
  1243. goto free_master;
  1244. }
  1245. for (i = 0; i < master->num_chipselect; i++) {
  1246. sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
  1247. sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
  1248. status = omap2_mcspi_request_dma(mcspi,
  1249. &mcspi->dma_channels[i]);
  1250. if (status == -EPROBE_DEFER)
  1251. goto free_master;
  1252. }
  1253. status = platform_get_irq(pdev, 0);
  1254. if (status == -EPROBE_DEFER)
  1255. goto free_master;
  1256. if (status < 0) {
  1257. dev_err(&pdev->dev, "no irq resource found\n");
  1258. goto free_master;
  1259. }
  1260. init_completion(&mcspi->txdone);
  1261. status = devm_request_irq(&pdev->dev, status,
  1262. omap2_mcspi_irq_handler, 0, pdev->name,
  1263. mcspi);
  1264. if (status) {
  1265. dev_err(&pdev->dev, "Cannot request IRQ");
  1266. goto free_master;
  1267. }
  1268. pm_runtime_use_autosuspend(&pdev->dev);
  1269. pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
  1270. pm_runtime_enable(&pdev->dev);
  1271. status = omap2_mcspi_controller_setup(mcspi);
  1272. if (status < 0)
  1273. goto disable_pm;
  1274. status = devm_spi_register_controller(&pdev->dev, master);
  1275. if (status < 0)
  1276. goto disable_pm;
  1277. return status;
  1278. disable_pm:
  1279. pm_runtime_dont_use_autosuspend(&pdev->dev);
  1280. pm_runtime_put_sync(&pdev->dev);
  1281. pm_runtime_disable(&pdev->dev);
  1282. free_master:
  1283. omap2_mcspi_release_dma(master);
  1284. spi_master_put(master);
  1285. return status;
  1286. }
  1287. static int omap2_mcspi_remove(struct platform_device *pdev)
  1288. {
  1289. struct spi_master *master = platform_get_drvdata(pdev);
  1290. struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
  1291. omap2_mcspi_release_dma(master);
  1292. pm_runtime_dont_use_autosuspend(mcspi->dev);
  1293. pm_runtime_put_sync(mcspi->dev);
  1294. pm_runtime_disable(&pdev->dev);
  1295. return 0;
  1296. }
  1297. /* work with hotplug and coldplug */
  1298. MODULE_ALIAS("platform:omap2_mcspi");
  1299. static int __maybe_unused omap2_mcspi_suspend(struct device *dev)
  1300. {
  1301. struct spi_master *master = dev_get_drvdata(dev);
  1302. struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
  1303. int error;
  1304. error = pinctrl_pm_select_sleep_state(dev);
  1305. if (error)
  1306. dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
  1307. __func__, error);
  1308. error = spi_master_suspend(master);
  1309. if (error)
  1310. dev_warn(mcspi->dev, "%s: master suspend failed: %i\n",
  1311. __func__, error);
  1312. return pm_runtime_force_suspend(dev);
  1313. }
  1314. static int __maybe_unused omap2_mcspi_resume(struct device *dev)
  1315. {
  1316. struct spi_master *master = dev_get_drvdata(dev);
  1317. struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
  1318. int error;
  1319. error = pinctrl_pm_select_default_state(dev);
  1320. if (error)
  1321. dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
  1322. __func__, error);
  1323. error = spi_master_resume(master);
  1324. if (error)
  1325. dev_warn(mcspi->dev, "%s: master resume failed: %i\n",
  1326. __func__, error);
  1327. return pm_runtime_force_resume(dev);
  1328. }
  1329. static const struct dev_pm_ops omap2_mcspi_pm_ops = {
  1330. SET_SYSTEM_SLEEP_PM_OPS(omap2_mcspi_suspend,
  1331. omap2_mcspi_resume)
  1332. .runtime_resume = omap_mcspi_runtime_resume,
  1333. };
  1334. static struct platform_driver omap2_mcspi_driver = {
  1335. .driver = {
  1336. .name = "omap2_mcspi",
  1337. .pm = &omap2_mcspi_pm_ops,
  1338. .of_match_table = omap_mcspi_of_match,
  1339. },
  1340. .probe = omap2_mcspi_probe,
  1341. .remove = omap2_mcspi_remove,
  1342. };
  1343. module_platform_driver(omap2_mcspi_driver);
  1344. MODULE_LICENSE("GPL");