spi-nxp-fspi.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * NXP FlexSPI(FSPI) controller driver.
  4. *
  5. * Copyright 2019-2020 NXP
  6. * Copyright 2020 Puresoftware Ltd.
  7. *
  8. * FlexSPI is a flexsible SPI host controller which supports two SPI
  9. * channels and up to 4 external devices. Each channel supports
  10. * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
  11. * data lines).
  12. *
  13. * FlexSPI controller is driven by the LUT(Look-up Table) registers
  14. * LUT registers are a look-up-table for sequences of instructions.
  15. * A valid sequence consists of four LUT registers.
  16. * Maximum 32 LUT sequences can be programmed simultaneously.
  17. *
  18. * LUTs are being created at run-time based on the commands passed
  19. * from the spi-mem framework, thus using single LUT index.
  20. *
  21. * Software triggered Flash read/write access by IP Bus.
  22. *
  23. * Memory mapped read access by AHB Bus.
  24. *
  25. * Based on SPI MEM interface and spi-fsl-qspi.c driver.
  26. *
  27. * Author:
  28. * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
  29. * Boris Brezillon <bbrezillon@kernel.org>
  30. * Frieder Schrempf <frieder.schrempf@kontron.de>
  31. */
  32. #include <linux/acpi.h>
  33. #include <linux/bitops.h>
  34. #include <linux/clk.h>
  35. #include <linux/completion.h>
  36. #include <linux/delay.h>
  37. #include <linux/err.h>
  38. #include <linux/errno.h>
  39. #include <linux/interrupt.h>
  40. #include <linux/io.h>
  41. #include <linux/iopoll.h>
  42. #include <linux/jiffies.h>
  43. #include <linux/kernel.h>
  44. #include <linux/module.h>
  45. #include <linux/mutex.h>
  46. #include <linux/of.h>
  47. #include <linux/of_device.h>
  48. #include <linux/platform_device.h>
  49. #include <linux/pm_qos.h>
  50. #include <linux/sizes.h>
  51. #include <linux/spi/spi.h>
  52. #include <linux/spi/spi-mem.h>
  53. /*
  54. * The driver only uses one single LUT entry, that is updated on
  55. * each call of exec_op(). Index 0 is preset at boot with a basic
  56. * read operation, so let's use the last entry (31).
  57. */
  58. #define SEQID_LUT 31
  59. /* Registers used by the driver */
  60. #define FSPI_MCR0 0x00
  61. #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24)
  62. #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16)
  63. #define FSPI_MCR0_LEARN_EN BIT(15)
  64. #define FSPI_MCR0_SCRFRUN_EN BIT(14)
  65. #define FSPI_MCR0_OCTCOMB_EN BIT(13)
  66. #define FSPI_MCR0_DOZE_EN BIT(12)
  67. #define FSPI_MCR0_HSEN BIT(11)
  68. #define FSPI_MCR0_SERCLKDIV BIT(8)
  69. #define FSPI_MCR0_ATDF_EN BIT(7)
  70. #define FSPI_MCR0_ARDF_EN BIT(6)
  71. #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4)
  72. #define FSPI_MCR0_END_CFG(x) ((x) << 2)
  73. #define FSPI_MCR0_MDIS BIT(1)
  74. #define FSPI_MCR0_SWRST BIT(0)
  75. #define FSPI_MCR1 0x04
  76. #define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16)
  77. #define FSPI_MCR1_AHB_TIMEOUT(x) (x)
  78. #define FSPI_MCR2 0x08
  79. #define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24)
  80. #define FSPI_MCR2_SAMEDEVICEEN BIT(15)
  81. #define FSPI_MCR2_CLRLRPHS BIT(14)
  82. #define FSPI_MCR2_ABRDATSZ BIT(8)
  83. #define FSPI_MCR2_ABRLEARN BIT(7)
  84. #define FSPI_MCR2_ABR_READ BIT(6)
  85. #define FSPI_MCR2_ABRWRITE BIT(5)
  86. #define FSPI_MCR2_ABRDUMMY BIT(4)
  87. #define FSPI_MCR2_ABR_MODE BIT(3)
  88. #define FSPI_MCR2_ABRCADDR BIT(2)
  89. #define FSPI_MCR2_ABRRADDR BIT(1)
  90. #define FSPI_MCR2_ABR_CMD BIT(0)
  91. #define FSPI_AHBCR 0x0c
  92. #define FSPI_AHBCR_RDADDROPT BIT(6)
  93. #define FSPI_AHBCR_PREF_EN BIT(5)
  94. #define FSPI_AHBCR_BUFF_EN BIT(4)
  95. #define FSPI_AHBCR_CACH_EN BIT(3)
  96. #define FSPI_AHBCR_CLRTXBUF BIT(2)
  97. #define FSPI_AHBCR_CLRRXBUF BIT(1)
  98. #define FSPI_AHBCR_PAR_EN BIT(0)
  99. #define FSPI_INTEN 0x10
  100. #define FSPI_INTEN_SCLKSBWR BIT(9)
  101. #define FSPI_INTEN_SCLKSBRD BIT(8)
  102. #define FSPI_INTEN_DATALRNFL BIT(7)
  103. #define FSPI_INTEN_IPTXWE BIT(6)
  104. #define FSPI_INTEN_IPRXWA BIT(5)
  105. #define FSPI_INTEN_AHBCMDERR BIT(4)
  106. #define FSPI_INTEN_IPCMDERR BIT(3)
  107. #define FSPI_INTEN_AHBCMDGE BIT(2)
  108. #define FSPI_INTEN_IPCMDGE BIT(1)
  109. #define FSPI_INTEN_IPCMDDONE BIT(0)
  110. #define FSPI_INTR 0x14
  111. #define FSPI_INTR_SCLKSBWR BIT(9)
  112. #define FSPI_INTR_SCLKSBRD BIT(8)
  113. #define FSPI_INTR_DATALRNFL BIT(7)
  114. #define FSPI_INTR_IPTXWE BIT(6)
  115. #define FSPI_INTR_IPRXWA BIT(5)
  116. #define FSPI_INTR_AHBCMDERR BIT(4)
  117. #define FSPI_INTR_IPCMDERR BIT(3)
  118. #define FSPI_INTR_AHBCMDGE BIT(2)
  119. #define FSPI_INTR_IPCMDGE BIT(1)
  120. #define FSPI_INTR_IPCMDDONE BIT(0)
  121. #define FSPI_LUTKEY 0x18
  122. #define FSPI_LUTKEY_VALUE 0x5AF05AF0
  123. #define FSPI_LCKCR 0x1C
  124. #define FSPI_LCKER_LOCK 0x1
  125. #define FSPI_LCKER_UNLOCK 0x2
  126. #define FSPI_BUFXCR_INVALID_MSTRID 0xE
  127. #define FSPI_AHBRX_BUF0CR0 0x20
  128. #define FSPI_AHBRX_BUF1CR0 0x24
  129. #define FSPI_AHBRX_BUF2CR0 0x28
  130. #define FSPI_AHBRX_BUF3CR0 0x2C
  131. #define FSPI_AHBRX_BUF4CR0 0x30
  132. #define FSPI_AHBRX_BUF5CR0 0x34
  133. #define FSPI_AHBRX_BUF6CR0 0x38
  134. #define FSPI_AHBRX_BUF7CR0 0x3C
  135. #define FSPI_AHBRXBUF0CR7_PREF BIT(31)
  136. #define FSPI_AHBRX_BUF0CR1 0x40
  137. #define FSPI_AHBRX_BUF1CR1 0x44
  138. #define FSPI_AHBRX_BUF2CR1 0x48
  139. #define FSPI_AHBRX_BUF3CR1 0x4C
  140. #define FSPI_AHBRX_BUF4CR1 0x50
  141. #define FSPI_AHBRX_BUF5CR1 0x54
  142. #define FSPI_AHBRX_BUF6CR1 0x58
  143. #define FSPI_AHBRX_BUF7CR1 0x5C
  144. #define FSPI_FLSHA1CR0 0x60
  145. #define FSPI_FLSHA2CR0 0x64
  146. #define FSPI_FLSHB1CR0 0x68
  147. #define FSPI_FLSHB2CR0 0x6C
  148. #define FSPI_FLSHXCR0_SZ_KB 10
  149. #define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB)
  150. #define FSPI_FLSHA1CR1 0x70
  151. #define FSPI_FLSHA2CR1 0x74
  152. #define FSPI_FLSHB1CR1 0x78
  153. #define FSPI_FLSHB2CR1 0x7C
  154. #define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16)
  155. #define FSPI_FLSHXCR1_CAS(x) ((x) << 11)
  156. #define FSPI_FLSHXCR1_WA BIT(10)
  157. #define FSPI_FLSHXCR1_TCSH(x) ((x) << 5)
  158. #define FSPI_FLSHXCR1_TCSS(x) (x)
  159. #define FSPI_FLSHA1CR2 0x80
  160. #define FSPI_FLSHA2CR2 0x84
  161. #define FSPI_FLSHB1CR2 0x88
  162. #define FSPI_FLSHB2CR2 0x8C
  163. #define FSPI_FLSHXCR2_CLRINSP BIT(24)
  164. #define FSPI_FLSHXCR2_AWRWAIT BIT(16)
  165. #define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13
  166. #define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8
  167. #define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5
  168. #define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0
  169. #define FSPI_IPCR0 0xA0
  170. #define FSPI_IPCR1 0xA4
  171. #define FSPI_IPCR1_IPAREN BIT(31)
  172. #define FSPI_IPCR1_SEQNUM_SHIFT 24
  173. #define FSPI_IPCR1_SEQID_SHIFT 16
  174. #define FSPI_IPCR1_IDATSZ(x) (x)
  175. #define FSPI_IPCMD 0xB0
  176. #define FSPI_IPCMD_TRG BIT(0)
  177. #define FSPI_DLPR 0xB4
  178. #define FSPI_IPRXFCR 0xB8
  179. #define FSPI_IPRXFCR_CLR BIT(0)
  180. #define FSPI_IPRXFCR_DMA_EN BIT(1)
  181. #define FSPI_IPRXFCR_WMRK(x) ((x) << 2)
  182. #define FSPI_IPTXFCR 0xBC
  183. #define FSPI_IPTXFCR_CLR BIT(0)
  184. #define FSPI_IPTXFCR_DMA_EN BIT(1)
  185. #define FSPI_IPTXFCR_WMRK(x) ((x) << 2)
  186. #define FSPI_DLLACR 0xC0
  187. #define FSPI_DLLACR_OVRDEN BIT(8)
  188. #define FSPI_DLLBCR 0xC4
  189. #define FSPI_DLLBCR_OVRDEN BIT(8)
  190. #define FSPI_STS0 0xE0
  191. #define FSPI_STS0_DLPHB(x) ((x) << 8)
  192. #define FSPI_STS0_DLPHA(x) ((x) << 4)
  193. #define FSPI_STS0_CMD_SRC(x) ((x) << 2)
  194. #define FSPI_STS0_ARB_IDLE BIT(1)
  195. #define FSPI_STS0_SEQ_IDLE BIT(0)
  196. #define FSPI_STS1 0xE4
  197. #define FSPI_STS1_IP_ERRCD(x) ((x) << 24)
  198. #define FSPI_STS1_IP_ERRID(x) ((x) << 16)
  199. #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8)
  200. #define FSPI_STS1_AHB_ERRID(x) (x)
  201. #define FSPI_AHBSPNST 0xEC
  202. #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16)
  203. #define FSPI_AHBSPNST_BUFID(x) ((x) << 1)
  204. #define FSPI_AHBSPNST_ACTIVE BIT(0)
  205. #define FSPI_IPRXFSTS 0xF0
  206. #define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16)
  207. #define FSPI_IPRXFSTS_FILL(x) (x)
  208. #define FSPI_IPTXFSTS 0xF4
  209. #define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16)
  210. #define FSPI_IPTXFSTS_FILL(x) (x)
  211. #define FSPI_RFDR 0x100
  212. #define FSPI_TFDR 0x180
  213. #define FSPI_LUT_BASE 0x200
  214. #define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
  215. #define FSPI_LUT_REG(idx) \
  216. (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4)
  217. /* register map end */
  218. /* Instruction set for the LUT register. */
  219. #define LUT_STOP 0x00
  220. #define LUT_CMD 0x01
  221. #define LUT_ADDR 0x02
  222. #define LUT_CADDR_SDR 0x03
  223. #define LUT_MODE 0x04
  224. #define LUT_MODE2 0x05
  225. #define LUT_MODE4 0x06
  226. #define LUT_MODE8 0x07
  227. #define LUT_NXP_WRITE 0x08
  228. #define LUT_NXP_READ 0x09
  229. #define LUT_LEARN_SDR 0x0A
  230. #define LUT_DATSZ_SDR 0x0B
  231. #define LUT_DUMMY 0x0C
  232. #define LUT_DUMMY_RWDS_SDR 0x0D
  233. #define LUT_JMP_ON_CS 0x1F
  234. #define LUT_CMD_DDR 0x21
  235. #define LUT_ADDR_DDR 0x22
  236. #define LUT_CADDR_DDR 0x23
  237. #define LUT_MODE_DDR 0x24
  238. #define LUT_MODE2_DDR 0x25
  239. #define LUT_MODE4_DDR 0x26
  240. #define LUT_MODE8_DDR 0x27
  241. #define LUT_WRITE_DDR 0x28
  242. #define LUT_READ_DDR 0x29
  243. #define LUT_LEARN_DDR 0x2A
  244. #define LUT_DATSZ_DDR 0x2B
  245. #define LUT_DUMMY_DDR 0x2C
  246. #define LUT_DUMMY_RWDS_DDR 0x2D
  247. /*
  248. * Calculate number of required PAD bits for LUT register.
  249. *
  250. * The pad stands for the number of IO lines [0:7].
  251. * For example, the octal read needs eight IO lines,
  252. * so you should use LUT_PAD(8). This macro
  253. * returns 3 i.e. use eight (2^3) IP lines for read.
  254. */
  255. #define LUT_PAD(x) (fls(x) - 1)
  256. /*
  257. * Macro for constructing the LUT entries with the following
  258. * register layout:
  259. *
  260. * ---------------------------------------------------
  261. * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
  262. * ---------------------------------------------------
  263. */
  264. #define PAD_SHIFT 8
  265. #define INSTR_SHIFT 10
  266. #define OPRND_SHIFT 16
  267. /* Macros for constructing the LUT register. */
  268. #define LUT_DEF(idx, ins, pad, opr) \
  269. ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \
  270. (opr)) << (((idx) % 2) * OPRND_SHIFT))
  271. #define POLL_TOUT 5000
  272. #define NXP_FSPI_MAX_CHIPSELECT 4
  273. #define NXP_FSPI_MIN_IOMAP SZ_4M
  274. struct nxp_fspi_devtype_data {
  275. unsigned int rxfifo;
  276. unsigned int txfifo;
  277. unsigned int ahb_buf_size;
  278. unsigned int quirks;
  279. bool little_endian;
  280. };
  281. static const struct nxp_fspi_devtype_data lx2160a_data = {
  282. .rxfifo = SZ_512, /* (64 * 64 bits) */
  283. .txfifo = SZ_1K, /* (128 * 64 bits) */
  284. .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
  285. .quirks = 0,
  286. .little_endian = true, /* little-endian */
  287. };
  288. static const struct nxp_fspi_devtype_data imx8mm_data = {
  289. .rxfifo = SZ_512, /* (64 * 64 bits) */
  290. .txfifo = SZ_1K, /* (128 * 64 bits) */
  291. .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
  292. .quirks = 0,
  293. .little_endian = true, /* little-endian */
  294. };
  295. static const struct nxp_fspi_devtype_data imx8qxp_data = {
  296. .rxfifo = SZ_512, /* (64 * 64 bits) */
  297. .txfifo = SZ_1K, /* (128 * 64 bits) */
  298. .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
  299. .quirks = 0,
  300. .little_endian = true, /* little-endian */
  301. };
  302. struct nxp_fspi {
  303. void __iomem *iobase;
  304. void __iomem *ahb_addr;
  305. u32 memmap_phy;
  306. u32 memmap_phy_size;
  307. u32 memmap_start;
  308. u32 memmap_len;
  309. struct clk *clk, *clk_en;
  310. struct device *dev;
  311. struct completion c;
  312. const struct nxp_fspi_devtype_data *devtype_data;
  313. struct mutex lock;
  314. struct pm_qos_request pm_qos_req;
  315. int selected;
  316. };
  317. /*
  318. * R/W functions for big- or little-endian registers:
  319. * The FSPI controller's endianness is independent of
  320. * the CPU core's endianness. So far, although the CPU
  321. * core is little-endian the FSPI controller can use
  322. * big-endian or little-endian.
  323. */
  324. static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr)
  325. {
  326. if (f->devtype_data->little_endian)
  327. iowrite32(val, addr);
  328. else
  329. iowrite32be(val, addr);
  330. }
  331. static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr)
  332. {
  333. if (f->devtype_data->little_endian)
  334. return ioread32(addr);
  335. else
  336. return ioread32be(addr);
  337. }
  338. static irqreturn_t nxp_fspi_irq_handler(int irq, void *dev_id)
  339. {
  340. struct nxp_fspi *f = dev_id;
  341. u32 reg;
  342. /* clear interrupt */
  343. reg = fspi_readl(f, f->iobase + FSPI_INTR);
  344. fspi_writel(f, FSPI_INTR_IPCMDDONE, f->iobase + FSPI_INTR);
  345. if (reg & FSPI_INTR_IPCMDDONE)
  346. complete(&f->c);
  347. return IRQ_HANDLED;
  348. }
  349. static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width)
  350. {
  351. switch (width) {
  352. case 1:
  353. case 2:
  354. case 4:
  355. case 8:
  356. return 0;
  357. }
  358. return -ENOTSUPP;
  359. }
  360. static bool nxp_fspi_supports_op(struct spi_mem *mem,
  361. const struct spi_mem_op *op)
  362. {
  363. struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
  364. int ret;
  365. ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth);
  366. if (op->addr.nbytes)
  367. ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth);
  368. if (op->dummy.nbytes)
  369. ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth);
  370. if (op->data.nbytes)
  371. ret |= nxp_fspi_check_buswidth(f, op->data.buswidth);
  372. if (ret)
  373. return false;
  374. /*
  375. * The number of address bytes should be equal to or less than 4 bytes.
  376. */
  377. if (op->addr.nbytes > 4)
  378. return false;
  379. /*
  380. * If requested address value is greater than controller assigned
  381. * memory mapped space, return error as it didn't fit in the range
  382. * of assigned address space.
  383. */
  384. if (op->addr.val >= f->memmap_phy_size)
  385. return false;
  386. /* Max 64 dummy clock cycles supported */
  387. if (op->dummy.buswidth &&
  388. (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
  389. return false;
  390. /* Max data length, check controller limits and alignment */
  391. if (op->data.dir == SPI_MEM_DATA_IN &&
  392. (op->data.nbytes > f->devtype_data->ahb_buf_size ||
  393. (op->data.nbytes > f->devtype_data->rxfifo - 4 &&
  394. !IS_ALIGNED(op->data.nbytes, 8))))
  395. return false;
  396. if (op->data.dir == SPI_MEM_DATA_OUT &&
  397. op->data.nbytes > f->devtype_data->txfifo)
  398. return false;
  399. return spi_mem_default_supports_op(mem, op);
  400. }
  401. /* Instead of busy looping invoke readl_poll_timeout functionality. */
  402. static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base,
  403. u32 mask, u32 delay_us,
  404. u32 timeout_us, bool c)
  405. {
  406. u32 reg;
  407. if (!f->devtype_data->little_endian)
  408. mask = (u32)cpu_to_be32(mask);
  409. if (c)
  410. return readl_poll_timeout(base, reg, (reg & mask),
  411. delay_us, timeout_us);
  412. else
  413. return readl_poll_timeout(base, reg, !(reg & mask),
  414. delay_us, timeout_us);
  415. }
  416. /*
  417. * If the slave device content being changed by Write/Erase, need to
  418. * invalidate the AHB buffer. This can be achieved by doing the reset
  419. * of controller after setting MCR0[SWRESET] bit.
  420. */
  421. static inline void nxp_fspi_invalid(struct nxp_fspi *f)
  422. {
  423. u32 reg;
  424. int ret;
  425. reg = fspi_readl(f, f->iobase + FSPI_MCR0);
  426. fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0);
  427. /* w1c register, wait unit clear */
  428. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
  429. FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
  430. WARN_ON(ret);
  431. }
  432. static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
  433. const struct spi_mem_op *op)
  434. {
  435. void __iomem *base = f->iobase;
  436. u32 lutval[4] = {};
  437. int lutidx = 1, i;
  438. /* cmd */
  439. lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
  440. op->cmd.opcode);
  441. /* addr bytes */
  442. if (op->addr.nbytes) {
  443. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
  444. LUT_PAD(op->addr.buswidth),
  445. op->addr.nbytes * 8);
  446. lutidx++;
  447. }
  448. /* dummy bytes, if needed */
  449. if (op->dummy.nbytes) {
  450. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
  451. /*
  452. * Due to FlexSPI controller limitation number of PAD for dummy
  453. * buswidth needs to be programmed as equal to data buswidth.
  454. */
  455. LUT_PAD(op->data.buswidth),
  456. op->dummy.nbytes * 8 /
  457. op->dummy.buswidth);
  458. lutidx++;
  459. }
  460. /* read/write data bytes */
  461. if (op->data.nbytes) {
  462. lutval[lutidx / 2] |= LUT_DEF(lutidx,
  463. op->data.dir == SPI_MEM_DATA_IN ?
  464. LUT_NXP_READ : LUT_NXP_WRITE,
  465. LUT_PAD(op->data.buswidth),
  466. 0);
  467. lutidx++;
  468. }
  469. /* stop condition. */
  470. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
  471. /* unlock LUT */
  472. fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
  473. fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR);
  474. /* fill LUT */
  475. for (i = 0; i < ARRAY_SIZE(lutval); i++)
  476. fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i));
  477. dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
  478. op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
  479. /* lock LUT */
  480. fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
  481. fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR);
  482. }
  483. static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f)
  484. {
  485. int ret;
  486. if (is_acpi_node(f->dev->fwnode))
  487. return 0;
  488. ret = clk_prepare_enable(f->clk_en);
  489. if (ret)
  490. return ret;
  491. ret = clk_prepare_enable(f->clk);
  492. if (ret) {
  493. clk_disable_unprepare(f->clk_en);
  494. return ret;
  495. }
  496. return 0;
  497. }
  498. static int nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
  499. {
  500. if (is_acpi_node(f->dev->fwnode))
  501. return 0;
  502. clk_disable_unprepare(f->clk);
  503. clk_disable_unprepare(f->clk_en);
  504. return 0;
  505. }
  506. /*
  507. * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
  508. * register and start base address of the slave device.
  509. *
  510. * (Higher address)
  511. * -------- <-- FLSHB2CR0
  512. * | B2 |
  513. * | |
  514. * B2 start address --> -------- <-- FLSHB1CR0
  515. * | B1 |
  516. * | |
  517. * B1 start address --> -------- <-- FLSHA2CR0
  518. * | A2 |
  519. * | |
  520. * A2 start address --> -------- <-- FLSHA1CR0
  521. * | A1 |
  522. * | |
  523. * A1 start address --> -------- (Lower address)
  524. *
  525. *
  526. * Start base address defines the starting address range for given CS and
  527. * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS.
  528. *
  529. * But, different targets are having different combinations of number of CS,
  530. * some targets only have single CS or two CS covering controller's full
  531. * memory mapped space area.
  532. * Thus, implementation is being done as independent of the size and number
  533. * of the connected slave device.
  534. * Assign controller memory mapped space size as the size to the connected
  535. * slave device.
  536. * Mark FLSHxxCR0 as zero initially and then assign value only to the selected
  537. * chip-select Flash configuration register.
  538. *
  539. * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the
  540. * memory mapped size of the controller.
  541. * Value for rest of the CS FLSHxxCR0 register would be zero.
  542. *
  543. */
  544. static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi)
  545. {
  546. unsigned long rate = spi->max_speed_hz;
  547. int ret;
  548. uint64_t size_kb;
  549. /*
  550. * Return, if previously selected slave device is same as current
  551. * requested slave device.
  552. */
  553. if (f->selected == spi->chip_select)
  554. return;
  555. /* Reset FLSHxxCR0 registers */
  556. fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0);
  557. fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0);
  558. fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0);
  559. fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0);
  560. /* Assign controller memory mapped space as size, KBytes, of flash. */
  561. size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size);
  562. fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 +
  563. 4 * spi->chip_select);
  564. dev_dbg(f->dev, "Slave device [CS:%x] selected\n", spi->chip_select);
  565. nxp_fspi_clk_disable_unprep(f);
  566. ret = clk_set_rate(f->clk, rate);
  567. if (ret)
  568. return;
  569. ret = nxp_fspi_clk_prep_enable(f);
  570. if (ret)
  571. return;
  572. f->selected = spi->chip_select;
  573. }
  574. static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
  575. {
  576. u32 start = op->addr.val;
  577. u32 len = op->data.nbytes;
  578. /* if necessary, ioremap before AHB read */
  579. if ((!f->ahb_addr) || start < f->memmap_start ||
  580. start + len > f->memmap_start + f->memmap_len) {
  581. if (f->ahb_addr)
  582. iounmap(f->ahb_addr);
  583. f->memmap_start = start;
  584. f->memmap_len = len > NXP_FSPI_MIN_IOMAP ?
  585. len : NXP_FSPI_MIN_IOMAP;
  586. f->ahb_addr = ioremap_wc(f->memmap_phy + f->memmap_start,
  587. f->memmap_len);
  588. if (!f->ahb_addr) {
  589. dev_err(f->dev, "failed to alloc memory\n");
  590. return -ENOMEM;
  591. }
  592. }
  593. /* Read out the data directly from the AHB buffer. */
  594. memcpy_fromio(op->data.buf.in,
  595. f->ahb_addr + start - f->memmap_start, len);
  596. return 0;
  597. }
  598. static void nxp_fspi_fill_txfifo(struct nxp_fspi *f,
  599. const struct spi_mem_op *op)
  600. {
  601. void __iomem *base = f->iobase;
  602. int i, ret;
  603. u8 *buf = (u8 *) op->data.buf.out;
  604. /* clear the TX FIFO. */
  605. fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR);
  606. /*
  607. * Default value of water mark level is 8 bytes, hence in single
  608. * write request controller can write max 8 bytes of data.
  609. */
  610. for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) {
  611. /* Wait for TXFIFO empty */
  612. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
  613. FSPI_INTR_IPTXWE, 0,
  614. POLL_TOUT, true);
  615. WARN_ON(ret);
  616. fspi_writel(f, *(u32 *) (buf + i), base + FSPI_TFDR);
  617. fspi_writel(f, *(u32 *) (buf + i + 4), base + FSPI_TFDR + 4);
  618. fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
  619. }
  620. if (i < op->data.nbytes) {
  621. u32 data = 0;
  622. int j;
  623. /* Wait for TXFIFO empty */
  624. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
  625. FSPI_INTR_IPTXWE, 0,
  626. POLL_TOUT, true);
  627. WARN_ON(ret);
  628. for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) {
  629. memcpy(&data, buf + i + j, 4);
  630. fspi_writel(f, data, base + FSPI_TFDR + j);
  631. }
  632. fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
  633. }
  634. }
  635. static void nxp_fspi_read_rxfifo(struct nxp_fspi *f,
  636. const struct spi_mem_op *op)
  637. {
  638. void __iomem *base = f->iobase;
  639. int i, ret;
  640. int len = op->data.nbytes;
  641. u8 *buf = (u8 *) op->data.buf.in;
  642. /*
  643. * Default value of water mark level is 8 bytes, hence in single
  644. * read request controller can read max 8 bytes of data.
  645. */
  646. for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) {
  647. /* Wait for RXFIFO available */
  648. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
  649. FSPI_INTR_IPRXWA, 0,
  650. POLL_TOUT, true);
  651. WARN_ON(ret);
  652. *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR);
  653. *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4);
  654. /* move the FIFO pointer */
  655. fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
  656. }
  657. if (i < len) {
  658. u32 tmp;
  659. int size, j;
  660. buf = op->data.buf.in + i;
  661. /* Wait for RXFIFO available */
  662. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
  663. FSPI_INTR_IPRXWA, 0,
  664. POLL_TOUT, true);
  665. WARN_ON(ret);
  666. len = op->data.nbytes - i;
  667. for (j = 0; j < op->data.nbytes - i; j += 4) {
  668. tmp = fspi_readl(f, base + FSPI_RFDR + j);
  669. size = min(len, 4);
  670. memcpy(buf + j, &tmp, size);
  671. len -= size;
  672. }
  673. }
  674. /* invalid the RXFIFO */
  675. fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR);
  676. /* move the FIFO pointer */
  677. fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
  678. }
  679. static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
  680. {
  681. void __iomem *base = f->iobase;
  682. int seqnum = 0;
  683. int err = 0;
  684. u32 reg;
  685. reg = fspi_readl(f, base + FSPI_IPRXFCR);
  686. /* invalid RXFIFO first */
  687. reg &= ~FSPI_IPRXFCR_DMA_EN;
  688. reg = reg | FSPI_IPRXFCR_CLR;
  689. fspi_writel(f, reg, base + FSPI_IPRXFCR);
  690. init_completion(&f->c);
  691. fspi_writel(f, op->addr.val, base + FSPI_IPCR0);
  692. /*
  693. * Always start the sequence at the same index since we update
  694. * the LUT at each exec_op() call. And also specify the DATA
  695. * length, since it's has not been specified in the LUT.
  696. */
  697. fspi_writel(f, op->data.nbytes |
  698. (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) |
  699. (seqnum << FSPI_IPCR1_SEQNUM_SHIFT),
  700. base + FSPI_IPCR1);
  701. /* Trigger the LUT now. */
  702. fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD);
  703. /* Wait for the interrupt. */
  704. if (!wait_for_completion_timeout(&f->c, msecs_to_jiffies(1000)))
  705. err = -ETIMEDOUT;
  706. /* Invoke IP data read, if request is of data read. */
  707. if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
  708. nxp_fspi_read_rxfifo(f, op);
  709. return err;
  710. }
  711. static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
  712. {
  713. struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
  714. int err = 0;
  715. mutex_lock(&f->lock);
  716. /* Wait for controller being ready. */
  717. err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
  718. FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true);
  719. WARN_ON(err);
  720. nxp_fspi_select_mem(f, mem->spi);
  721. nxp_fspi_prepare_lut(f, op);
  722. /*
  723. * If we have large chunks of data, we read them through the AHB bus
  724. * by accessing the mapped memory. In all other cases we use
  725. * IP commands to access the flash.
  726. */
  727. if (op->data.nbytes > (f->devtype_data->rxfifo - 4) &&
  728. op->data.dir == SPI_MEM_DATA_IN) {
  729. err = nxp_fspi_read_ahb(f, op);
  730. } else {
  731. if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
  732. nxp_fspi_fill_txfifo(f, op);
  733. err = nxp_fspi_do_op(f, op);
  734. }
  735. /* Invalidate the data in the AHB buffer. */
  736. nxp_fspi_invalid(f);
  737. mutex_unlock(&f->lock);
  738. return err;
  739. }
  740. static int nxp_fspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
  741. {
  742. struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
  743. if (op->data.dir == SPI_MEM_DATA_OUT) {
  744. if (op->data.nbytes > f->devtype_data->txfifo)
  745. op->data.nbytes = f->devtype_data->txfifo;
  746. } else {
  747. if (op->data.nbytes > f->devtype_data->ahb_buf_size)
  748. op->data.nbytes = f->devtype_data->ahb_buf_size;
  749. else if (op->data.nbytes > (f->devtype_data->rxfifo - 4))
  750. op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
  751. }
  752. return 0;
  753. }
  754. static int nxp_fspi_default_setup(struct nxp_fspi *f)
  755. {
  756. void __iomem *base = f->iobase;
  757. int ret, i;
  758. u32 reg;
  759. /* disable and unprepare clock to avoid glitch pass to controller */
  760. nxp_fspi_clk_disable_unprep(f);
  761. /* the default frequency, we will change it later if necessary. */
  762. ret = clk_set_rate(f->clk, 20000000);
  763. if (ret)
  764. return ret;
  765. ret = nxp_fspi_clk_prep_enable(f);
  766. if (ret)
  767. return ret;
  768. /* Reset the module */
  769. /* w1c register, wait unit clear */
  770. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
  771. FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
  772. WARN_ON(ret);
  773. /* Disable the module */
  774. fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0);
  775. /* Reset the DLL register to default value */
  776. fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR);
  777. fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);
  778. /* enable module */
  779. fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) |
  780. FSPI_MCR0_IP_TIMEOUT(0xFF) | (u32) FSPI_MCR0_OCTCOMB_EN,
  781. base + FSPI_MCR0);
  782. /*
  783. * Disable same device enable bit and configure all slave devices
  784. * independently.
  785. */
  786. reg = fspi_readl(f, f->iobase + FSPI_MCR2);
  787. reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN);
  788. fspi_writel(f, reg, base + FSPI_MCR2);
  789. /* AHB configuration for access buffer 0~7. */
  790. for (i = 0; i < 7; i++)
  791. fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i);
  792. /*
  793. * Set ADATSZ with the maximum AHB buffer size to improve the read
  794. * performance.
  795. */
  796. fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 |
  797. FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0);
  798. /* prefetch and no start address alignment limitation */
  799. fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT,
  800. base + FSPI_AHBCR);
  801. /* AHB Read - Set lut sequence ID for all CS. */
  802. fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2);
  803. fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2);
  804. fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2);
  805. fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2);
  806. f->selected = -1;
  807. /* enable the interrupt */
  808. fspi_writel(f, FSPI_INTEN_IPCMDDONE, base + FSPI_INTEN);
  809. return 0;
  810. }
  811. static const char *nxp_fspi_get_name(struct spi_mem *mem)
  812. {
  813. struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
  814. struct device *dev = &mem->spi->dev;
  815. const char *name;
  816. // Set custom name derived from the platform_device of the controller.
  817. if (of_get_available_child_count(f->dev->of_node) == 1)
  818. return dev_name(f->dev);
  819. name = devm_kasprintf(dev, GFP_KERNEL,
  820. "%s-%d", dev_name(f->dev),
  821. mem->spi->chip_select);
  822. if (!name) {
  823. dev_err(dev, "failed to get memory for custom flash name\n");
  824. return ERR_PTR(-ENOMEM);
  825. }
  826. return name;
  827. }
  828. static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
  829. .adjust_op_size = nxp_fspi_adjust_op_size,
  830. .supports_op = nxp_fspi_supports_op,
  831. .exec_op = nxp_fspi_exec_op,
  832. .get_name = nxp_fspi_get_name,
  833. };
  834. static int nxp_fspi_probe(struct platform_device *pdev)
  835. {
  836. struct spi_controller *ctlr;
  837. struct device *dev = &pdev->dev;
  838. struct device_node *np = dev->of_node;
  839. struct resource *res;
  840. struct nxp_fspi *f;
  841. int ret;
  842. u32 reg;
  843. ctlr = spi_alloc_master(&pdev->dev, sizeof(*f));
  844. if (!ctlr)
  845. return -ENOMEM;
  846. ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL |
  847. SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL;
  848. f = spi_controller_get_devdata(ctlr);
  849. f->dev = dev;
  850. f->devtype_data = device_get_match_data(dev);
  851. if (!f->devtype_data) {
  852. ret = -ENODEV;
  853. goto err_put_ctrl;
  854. }
  855. platform_set_drvdata(pdev, f);
  856. /* find the resources - configuration register address space */
  857. if (is_acpi_node(f->dev->fwnode))
  858. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  859. else
  860. res = platform_get_resource_byname(pdev,
  861. IORESOURCE_MEM, "fspi_base");
  862. f->iobase = devm_ioremap_resource(dev, res);
  863. if (IS_ERR(f->iobase)) {
  864. ret = PTR_ERR(f->iobase);
  865. goto err_put_ctrl;
  866. }
  867. /* find the resources - controller memory mapped space */
  868. if (is_acpi_node(f->dev->fwnode))
  869. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  870. else
  871. res = platform_get_resource_byname(pdev,
  872. IORESOURCE_MEM, "fspi_mmap");
  873. if (!res) {
  874. ret = -ENODEV;
  875. goto err_put_ctrl;
  876. }
  877. /* assign memory mapped starting address and mapped size. */
  878. f->memmap_phy = res->start;
  879. f->memmap_phy_size = resource_size(res);
  880. /* find the clocks */
  881. if (dev_of_node(&pdev->dev)) {
  882. f->clk_en = devm_clk_get(dev, "fspi_en");
  883. if (IS_ERR(f->clk_en)) {
  884. ret = PTR_ERR(f->clk_en);
  885. goto err_put_ctrl;
  886. }
  887. f->clk = devm_clk_get(dev, "fspi");
  888. if (IS_ERR(f->clk)) {
  889. ret = PTR_ERR(f->clk);
  890. goto err_put_ctrl;
  891. }
  892. ret = nxp_fspi_clk_prep_enable(f);
  893. if (ret) {
  894. dev_err(dev, "can not enable the clock\n");
  895. goto err_put_ctrl;
  896. }
  897. }
  898. /* Clear potential interrupts */
  899. reg = fspi_readl(f, f->iobase + FSPI_INTR);
  900. if (reg)
  901. fspi_writel(f, reg, f->iobase + FSPI_INTR);
  902. /* find the irq */
  903. ret = platform_get_irq(pdev, 0);
  904. if (ret < 0)
  905. goto err_disable_clk;
  906. ret = devm_request_irq(dev, ret,
  907. nxp_fspi_irq_handler, 0, pdev->name, f);
  908. if (ret) {
  909. dev_err(dev, "failed to request irq: %d\n", ret);
  910. goto err_disable_clk;
  911. }
  912. mutex_init(&f->lock);
  913. ctlr->bus_num = -1;
  914. ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT;
  915. ctlr->mem_ops = &nxp_fspi_mem_ops;
  916. nxp_fspi_default_setup(f);
  917. ctlr->dev.of_node = np;
  918. ret = devm_spi_register_controller(&pdev->dev, ctlr);
  919. if (ret)
  920. goto err_destroy_mutex;
  921. return 0;
  922. err_destroy_mutex:
  923. mutex_destroy(&f->lock);
  924. err_disable_clk:
  925. nxp_fspi_clk_disable_unprep(f);
  926. err_put_ctrl:
  927. spi_controller_put(ctlr);
  928. dev_err(dev, "NXP FSPI probe failed\n");
  929. return ret;
  930. }
  931. static int nxp_fspi_remove(struct platform_device *pdev)
  932. {
  933. struct nxp_fspi *f = platform_get_drvdata(pdev);
  934. /* disable the hardware */
  935. fspi_writel(f, FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0);
  936. nxp_fspi_clk_disable_unprep(f);
  937. mutex_destroy(&f->lock);
  938. if (f->ahb_addr)
  939. iounmap(f->ahb_addr);
  940. return 0;
  941. }
  942. static int nxp_fspi_suspend(struct device *dev)
  943. {
  944. return 0;
  945. }
  946. static int nxp_fspi_resume(struct device *dev)
  947. {
  948. struct nxp_fspi *f = dev_get_drvdata(dev);
  949. nxp_fspi_default_setup(f);
  950. return 0;
  951. }
  952. static const struct of_device_id nxp_fspi_dt_ids[] = {
  953. { .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, },
  954. { .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, },
  955. { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, },
  956. { /* sentinel */ }
  957. };
  958. MODULE_DEVICE_TABLE(of, nxp_fspi_dt_ids);
  959. #ifdef CONFIG_ACPI
  960. static const struct acpi_device_id nxp_fspi_acpi_ids[] = {
  961. { "NXP0009", .driver_data = (kernel_ulong_t)&lx2160a_data, },
  962. {}
  963. };
  964. MODULE_DEVICE_TABLE(acpi, nxp_fspi_acpi_ids);
  965. #endif
  966. static const struct dev_pm_ops nxp_fspi_pm_ops = {
  967. .suspend = nxp_fspi_suspend,
  968. .resume = nxp_fspi_resume,
  969. };
  970. static struct platform_driver nxp_fspi_driver = {
  971. .driver = {
  972. .name = "nxp-fspi",
  973. .of_match_table = nxp_fspi_dt_ids,
  974. .acpi_match_table = ACPI_PTR(nxp_fspi_acpi_ids),
  975. .pm = &nxp_fspi_pm_ops,
  976. },
  977. .probe = nxp_fspi_probe,
  978. .remove = nxp_fspi_remove,
  979. };
  980. module_platform_driver(nxp_fspi_driver);
  981. MODULE_DESCRIPTION("NXP FSPI Controller Driver");
  982. MODULE_AUTHOR("NXP Semiconductor");
  983. MODULE_AUTHOR("Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>");
  984. MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>");
  985. MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>");
  986. MODULE_LICENSE("GPL v2");