spi-npcm-pspi.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2018 Nuvoton Technology corporation.
  3. #include <linux/kernel.h>
  4. #include <linux/bitfield.h>
  5. #include <linux/bitops.h>
  6. #include <linux/clk.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/io.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/spi/spi.h>
  12. #include <linux/reset.h>
  13. #include <asm/unaligned.h>
  14. #include <linux/regmap.h>
  15. #include <linux/mfd/syscon.h>
  16. struct npcm_pspi {
  17. struct completion xfer_done;
  18. struct reset_control *reset;
  19. struct spi_master *master;
  20. unsigned int tx_bytes;
  21. unsigned int rx_bytes;
  22. void __iomem *base;
  23. bool is_save_param;
  24. u8 bits_per_word;
  25. const u8 *tx_buf;
  26. struct clk *clk;
  27. u32 speed_hz;
  28. u8 *rx_buf;
  29. u16 mode;
  30. u32 id;
  31. };
  32. #define DRIVER_NAME "npcm-pspi"
  33. #define NPCM_PSPI_DATA 0x00
  34. #define NPCM_PSPI_CTL1 0x02
  35. #define NPCM_PSPI_STAT 0x04
  36. /* definitions for control and status register */
  37. #define NPCM_PSPI_CTL1_SPIEN BIT(0)
  38. #define NPCM_PSPI_CTL1_MOD BIT(2)
  39. #define NPCM_PSPI_CTL1_EIR BIT(5)
  40. #define NPCM_PSPI_CTL1_EIW BIT(6)
  41. #define NPCM_PSPI_CTL1_SCM BIT(7)
  42. #define NPCM_PSPI_CTL1_SCIDL BIT(8)
  43. #define NPCM_PSPI_CTL1_SCDV6_0 GENMASK(15, 9)
  44. #define NPCM_PSPI_STAT_BSY BIT(0)
  45. #define NPCM_PSPI_STAT_RBF BIT(1)
  46. /* general definitions */
  47. #define NPCM_PSPI_TIMEOUT_MS 2000
  48. #define NPCM_PSPI_MAX_CLK_DIVIDER 256
  49. #define NPCM_PSPI_MIN_CLK_DIVIDER 4
  50. #define NPCM_PSPI_DEFAULT_CLK 25000000
  51. static inline unsigned int bytes_per_word(unsigned int bits)
  52. {
  53. return bits <= 8 ? 1 : 2;
  54. }
  55. static inline void npcm_pspi_irq_enable(struct npcm_pspi *priv, u16 mask)
  56. {
  57. u16 val;
  58. val = ioread16(priv->base + NPCM_PSPI_CTL1);
  59. val |= mask;
  60. iowrite16(val, priv->base + NPCM_PSPI_CTL1);
  61. }
  62. static inline void npcm_pspi_irq_disable(struct npcm_pspi *priv, u16 mask)
  63. {
  64. u16 val;
  65. val = ioread16(priv->base + NPCM_PSPI_CTL1);
  66. val &= ~mask;
  67. iowrite16(val, priv->base + NPCM_PSPI_CTL1);
  68. }
  69. static inline void npcm_pspi_enable(struct npcm_pspi *priv)
  70. {
  71. u16 val;
  72. val = ioread16(priv->base + NPCM_PSPI_CTL1);
  73. val |= NPCM_PSPI_CTL1_SPIEN;
  74. iowrite16(val, priv->base + NPCM_PSPI_CTL1);
  75. }
  76. static inline void npcm_pspi_disable(struct npcm_pspi *priv)
  77. {
  78. u16 val;
  79. val = ioread16(priv->base + NPCM_PSPI_CTL1);
  80. val &= ~NPCM_PSPI_CTL1_SPIEN;
  81. iowrite16(val, priv->base + NPCM_PSPI_CTL1);
  82. }
  83. static void npcm_pspi_set_mode(struct spi_device *spi)
  84. {
  85. struct npcm_pspi *priv = spi_master_get_devdata(spi->master);
  86. u16 regtemp;
  87. u16 mode_val;
  88. switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
  89. case SPI_MODE_0:
  90. mode_val = 0;
  91. break;
  92. case SPI_MODE_1:
  93. mode_val = NPCM_PSPI_CTL1_SCIDL;
  94. break;
  95. case SPI_MODE_2:
  96. mode_val = NPCM_PSPI_CTL1_SCM;
  97. break;
  98. case SPI_MODE_3:
  99. mode_val = NPCM_PSPI_CTL1_SCIDL | NPCM_PSPI_CTL1_SCM;
  100. break;
  101. }
  102. regtemp = ioread16(priv->base + NPCM_PSPI_CTL1);
  103. regtemp &= ~(NPCM_PSPI_CTL1_SCM | NPCM_PSPI_CTL1_SCIDL);
  104. iowrite16(regtemp | mode_val, priv->base + NPCM_PSPI_CTL1);
  105. }
  106. static void npcm_pspi_set_transfer_size(struct npcm_pspi *priv, int size)
  107. {
  108. u16 regtemp;
  109. regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base);
  110. switch (size) {
  111. case 8:
  112. regtemp &= ~NPCM_PSPI_CTL1_MOD;
  113. break;
  114. case 16:
  115. regtemp |= NPCM_PSPI_CTL1_MOD;
  116. break;
  117. }
  118. iowrite16(regtemp, NPCM_PSPI_CTL1 + priv->base);
  119. }
  120. static void npcm_pspi_set_baudrate(struct npcm_pspi *priv, unsigned int speed)
  121. {
  122. u32 ckdiv;
  123. u16 regtemp;
  124. /* the supported rates are numbers from 4 to 256. */
  125. ckdiv = DIV_ROUND_CLOSEST(clk_get_rate(priv->clk), (2 * speed)) - 1;
  126. regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base);
  127. regtemp &= ~NPCM_PSPI_CTL1_SCDV6_0;
  128. iowrite16(regtemp | (ckdiv << 9), NPCM_PSPI_CTL1 + priv->base);
  129. }
  130. static void npcm_pspi_setup_transfer(struct spi_device *spi,
  131. struct spi_transfer *t)
  132. {
  133. struct npcm_pspi *priv = spi_master_get_devdata(spi->master);
  134. priv->tx_buf = t->tx_buf;
  135. priv->rx_buf = t->rx_buf;
  136. priv->tx_bytes = t->len;
  137. priv->rx_bytes = t->len;
  138. if (!priv->is_save_param || priv->mode != spi->mode) {
  139. npcm_pspi_set_mode(spi);
  140. priv->mode = spi->mode;
  141. }
  142. /*
  143. * If transfer is even length, and 8 bits per word transfer,
  144. * then implement 16 bits-per-word transfer.
  145. */
  146. if (priv->bits_per_word == 8 && !(t->len & 0x1))
  147. t->bits_per_word = 16;
  148. if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) {
  149. npcm_pspi_set_transfer_size(priv, t->bits_per_word);
  150. priv->bits_per_word = t->bits_per_word;
  151. }
  152. if (!priv->is_save_param || priv->speed_hz != t->speed_hz) {
  153. npcm_pspi_set_baudrate(priv, t->speed_hz);
  154. priv->speed_hz = t->speed_hz;
  155. }
  156. if (!priv->is_save_param)
  157. priv->is_save_param = true;
  158. }
  159. static void npcm_pspi_send(struct npcm_pspi *priv)
  160. {
  161. int wsize;
  162. u16 val;
  163. wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
  164. priv->tx_bytes -= wsize;
  165. if (!priv->tx_buf)
  166. return;
  167. switch (wsize) {
  168. case 1:
  169. val = *priv->tx_buf++;
  170. iowrite8(val, NPCM_PSPI_DATA + priv->base);
  171. break;
  172. case 2:
  173. val = *priv->tx_buf++;
  174. val = *priv->tx_buf++ | (val << 8);
  175. iowrite16(val, NPCM_PSPI_DATA + priv->base);
  176. break;
  177. default:
  178. WARN_ON_ONCE(1);
  179. return;
  180. }
  181. }
  182. static void npcm_pspi_recv(struct npcm_pspi *priv)
  183. {
  184. int rsize;
  185. u16 val;
  186. rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes);
  187. priv->rx_bytes -= rsize;
  188. if (!priv->rx_buf)
  189. return;
  190. switch (rsize) {
  191. case 1:
  192. *priv->rx_buf++ = ioread8(priv->base + NPCM_PSPI_DATA);
  193. break;
  194. case 2:
  195. val = ioread16(priv->base + NPCM_PSPI_DATA);
  196. *priv->rx_buf++ = (val >> 8);
  197. *priv->rx_buf++ = val & 0xff;
  198. break;
  199. default:
  200. WARN_ON_ONCE(1);
  201. return;
  202. }
  203. }
  204. static int npcm_pspi_transfer_one(struct spi_master *master,
  205. struct spi_device *spi,
  206. struct spi_transfer *t)
  207. {
  208. struct npcm_pspi *priv = spi_master_get_devdata(master);
  209. int status;
  210. npcm_pspi_setup_transfer(spi, t);
  211. reinit_completion(&priv->xfer_done);
  212. npcm_pspi_enable(priv);
  213. status = wait_for_completion_timeout(&priv->xfer_done,
  214. msecs_to_jiffies
  215. (NPCM_PSPI_TIMEOUT_MS));
  216. if (status == 0) {
  217. npcm_pspi_disable(priv);
  218. return -ETIMEDOUT;
  219. }
  220. return 0;
  221. }
  222. static int npcm_pspi_prepare_transfer_hardware(struct spi_master *master)
  223. {
  224. struct npcm_pspi *priv = spi_master_get_devdata(master);
  225. npcm_pspi_irq_enable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW);
  226. return 0;
  227. }
  228. static int npcm_pspi_unprepare_transfer_hardware(struct spi_master *master)
  229. {
  230. struct npcm_pspi *priv = spi_master_get_devdata(master);
  231. npcm_pspi_irq_disable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW);
  232. return 0;
  233. }
  234. static void npcm_pspi_reset_hw(struct npcm_pspi *priv)
  235. {
  236. reset_control_assert(priv->reset);
  237. udelay(5);
  238. reset_control_deassert(priv->reset);
  239. }
  240. static irqreturn_t npcm_pspi_handler(int irq, void *dev_id)
  241. {
  242. struct npcm_pspi *priv = dev_id;
  243. u8 stat;
  244. stat = ioread8(priv->base + NPCM_PSPI_STAT);
  245. if (!priv->tx_buf && !priv->rx_buf)
  246. return IRQ_NONE;
  247. if (priv->tx_buf) {
  248. if (stat & NPCM_PSPI_STAT_RBF) {
  249. ioread8(NPCM_PSPI_DATA + priv->base);
  250. if (priv->tx_bytes == 0) {
  251. npcm_pspi_disable(priv);
  252. complete(&priv->xfer_done);
  253. return IRQ_HANDLED;
  254. }
  255. }
  256. if ((stat & NPCM_PSPI_STAT_BSY) == 0)
  257. if (priv->tx_bytes)
  258. npcm_pspi_send(priv);
  259. }
  260. if (priv->rx_buf) {
  261. if (stat & NPCM_PSPI_STAT_RBF) {
  262. if (!priv->rx_bytes)
  263. return IRQ_NONE;
  264. npcm_pspi_recv(priv);
  265. if (!priv->rx_bytes) {
  266. npcm_pspi_disable(priv);
  267. complete(&priv->xfer_done);
  268. return IRQ_HANDLED;
  269. }
  270. }
  271. if (((stat & NPCM_PSPI_STAT_BSY) == 0) && !priv->tx_buf)
  272. iowrite8(0x0, NPCM_PSPI_DATA + priv->base);
  273. }
  274. return IRQ_HANDLED;
  275. }
  276. static int npcm_pspi_probe(struct platform_device *pdev)
  277. {
  278. struct npcm_pspi *priv;
  279. struct spi_master *master;
  280. unsigned long clk_hz;
  281. int irq;
  282. int ret;
  283. master = spi_alloc_master(&pdev->dev, sizeof(*priv));
  284. if (!master)
  285. return -ENOMEM;
  286. platform_set_drvdata(pdev, master);
  287. priv = spi_master_get_devdata(master);
  288. priv->master = master;
  289. priv->is_save_param = false;
  290. priv->base = devm_platform_ioremap_resource(pdev, 0);
  291. if (IS_ERR(priv->base)) {
  292. ret = PTR_ERR(priv->base);
  293. goto out_master_put;
  294. }
  295. priv->clk = devm_clk_get(&pdev->dev, NULL);
  296. if (IS_ERR(priv->clk)) {
  297. dev_err(&pdev->dev, "failed to get clock\n");
  298. ret = PTR_ERR(priv->clk);
  299. goto out_master_put;
  300. }
  301. ret = clk_prepare_enable(priv->clk);
  302. if (ret)
  303. goto out_master_put;
  304. irq = platform_get_irq(pdev, 0);
  305. if (irq < 0) {
  306. ret = irq;
  307. goto out_disable_clk;
  308. }
  309. priv->reset = devm_reset_control_get(&pdev->dev, NULL);
  310. if (IS_ERR(priv->reset)) {
  311. ret = PTR_ERR(priv->reset);
  312. goto out_disable_clk;
  313. }
  314. /* reset SPI-HW block */
  315. npcm_pspi_reset_hw(priv);
  316. ret = devm_request_irq(&pdev->dev, irq, npcm_pspi_handler, 0,
  317. "npcm-pspi", priv);
  318. if (ret) {
  319. dev_err(&pdev->dev, "failed to request IRQ\n");
  320. goto out_disable_clk;
  321. }
  322. init_completion(&priv->xfer_done);
  323. clk_hz = clk_get_rate(priv->clk);
  324. master->max_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MIN_CLK_DIVIDER);
  325. master->min_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MAX_CLK_DIVIDER);
  326. master->mode_bits = SPI_CPHA | SPI_CPOL;
  327. master->dev.of_node = pdev->dev.of_node;
  328. master->bus_num = -1;
  329. master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
  330. master->transfer_one = npcm_pspi_transfer_one;
  331. master->prepare_transfer_hardware =
  332. npcm_pspi_prepare_transfer_hardware;
  333. master->unprepare_transfer_hardware =
  334. npcm_pspi_unprepare_transfer_hardware;
  335. master->use_gpio_descriptors = true;
  336. /* set to default clock rate */
  337. npcm_pspi_set_baudrate(priv, NPCM_PSPI_DEFAULT_CLK);
  338. ret = devm_spi_register_master(&pdev->dev, master);
  339. if (ret)
  340. goto out_disable_clk;
  341. pr_info("NPCM Peripheral SPI %d probed\n", master->bus_num);
  342. return 0;
  343. out_disable_clk:
  344. clk_disable_unprepare(priv->clk);
  345. out_master_put:
  346. spi_master_put(master);
  347. return ret;
  348. }
  349. static int npcm_pspi_remove(struct platform_device *pdev)
  350. {
  351. struct spi_master *master = platform_get_drvdata(pdev);
  352. struct npcm_pspi *priv = spi_master_get_devdata(master);
  353. npcm_pspi_reset_hw(priv);
  354. clk_disable_unprepare(priv->clk);
  355. return 0;
  356. }
  357. static const struct of_device_id npcm_pspi_match[] = {
  358. { .compatible = "nuvoton,npcm750-pspi", .data = NULL },
  359. {}
  360. };
  361. MODULE_DEVICE_TABLE(of, npcm_pspi_match);
  362. static struct platform_driver npcm_pspi_driver = {
  363. .driver = {
  364. .name = DRIVER_NAME,
  365. .of_match_table = npcm_pspi_match,
  366. },
  367. .probe = npcm_pspi_probe,
  368. .remove = npcm_pspi_remove,
  369. };
  370. module_platform_driver(npcm_pspi_driver);
  371. MODULE_DESCRIPTION("NPCM peripheral SPI Controller driver");
  372. MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
  373. MODULE_LICENSE("GPL v2");