spi-npcm-fiu.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2019 Nuvoton Technology corporation.
  3. #include <linux/bits.h>
  4. #include <linux/init.h>
  5. #include <linux/kernel.h>
  6. #include <linux/device.h>
  7. #include <linux/module.h>
  8. #include <linux/ioport.h>
  9. #include <linux/clk.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/io.h>
  12. #include <linux/vmalloc.h>
  13. #include <linux/regmap.h>
  14. #include <linux/of_device.h>
  15. #include <linux/spi/spi-mem.h>
  16. #include <linux/mfd/syscon.h>
  17. /* NPCM7xx GCR module */
  18. #define NPCM7XX_INTCR3_OFFSET 0x9C
  19. #define NPCM7XX_INTCR3_FIU_FIX BIT(6)
  20. /* Flash Interface Unit (FIU) Registers */
  21. #define NPCM_FIU_DRD_CFG 0x00
  22. #define NPCM_FIU_DWR_CFG 0x04
  23. #define NPCM_FIU_UMA_CFG 0x08
  24. #define NPCM_FIU_UMA_CTS 0x0C
  25. #define NPCM_FIU_UMA_CMD 0x10
  26. #define NPCM_FIU_UMA_ADDR 0x14
  27. #define NPCM_FIU_PRT_CFG 0x18
  28. #define NPCM_FIU_UMA_DW0 0x20
  29. #define NPCM_FIU_UMA_DW1 0x24
  30. #define NPCM_FIU_UMA_DW2 0x28
  31. #define NPCM_FIU_UMA_DW3 0x2C
  32. #define NPCM_FIU_UMA_DR0 0x30
  33. #define NPCM_FIU_UMA_DR1 0x34
  34. #define NPCM_FIU_UMA_DR2 0x38
  35. #define NPCM_FIU_UMA_DR3 0x3C
  36. #define NPCM_FIU_MAX_REG_LIMIT 0x80
  37. /* FIU Direct Read Configuration Register */
  38. #define NPCM_FIU_DRD_CFG_LCK BIT(31)
  39. #define NPCM_FIU_DRD_CFG_R_BURST GENMASK(25, 24)
  40. #define NPCM_FIU_DRD_CFG_ADDSIZ GENMASK(17, 16)
  41. #define NPCM_FIU_DRD_CFG_DBW GENMASK(13, 12)
  42. #define NPCM_FIU_DRD_CFG_ACCTYPE GENMASK(9, 8)
  43. #define NPCM_FIU_DRD_CFG_RDCMD GENMASK(7, 0)
  44. #define NPCM_FIU_DRD_ADDSIZ_SHIFT 16
  45. #define NPCM_FIU_DRD_DBW_SHIFT 12
  46. #define NPCM_FIU_DRD_ACCTYPE_SHIFT 8
  47. /* FIU Direct Write Configuration Register */
  48. #define NPCM_FIU_DWR_CFG_LCK BIT(31)
  49. #define NPCM_FIU_DWR_CFG_W_BURST GENMASK(25, 24)
  50. #define NPCM_FIU_DWR_CFG_ADDSIZ GENMASK(17, 16)
  51. #define NPCM_FIU_DWR_CFG_ABPCK GENMASK(11, 10)
  52. #define NPCM_FIU_DWR_CFG_DBPCK GENMASK(9, 8)
  53. #define NPCM_FIU_DWR_CFG_WRCMD GENMASK(7, 0)
  54. #define NPCM_FIU_DWR_ADDSIZ_SHIFT 16
  55. #define NPCM_FIU_DWR_ABPCK_SHIFT 10
  56. #define NPCM_FIU_DWR_DBPCK_SHIFT 8
  57. /* FIU UMA Configuration Register */
  58. #define NPCM_FIU_UMA_CFG_LCK BIT(31)
  59. #define NPCM_FIU_UMA_CFG_CMMLCK BIT(30)
  60. #define NPCM_FIU_UMA_CFG_RDATSIZ GENMASK(28, 24)
  61. #define NPCM_FIU_UMA_CFG_DBSIZ GENMASK(23, 21)
  62. #define NPCM_FIU_UMA_CFG_WDATSIZ GENMASK(20, 16)
  63. #define NPCM_FIU_UMA_CFG_ADDSIZ GENMASK(13, 11)
  64. #define NPCM_FIU_UMA_CFG_CMDSIZ BIT(10)
  65. #define NPCM_FIU_UMA_CFG_RDBPCK GENMASK(9, 8)
  66. #define NPCM_FIU_UMA_CFG_DBPCK GENMASK(7, 6)
  67. #define NPCM_FIU_UMA_CFG_WDBPCK GENMASK(5, 4)
  68. #define NPCM_FIU_UMA_CFG_ADBPCK GENMASK(3, 2)
  69. #define NPCM_FIU_UMA_CFG_CMBPCK GENMASK(1, 0)
  70. #define NPCM_FIU_UMA_CFG_ADBPCK_SHIFT 2
  71. #define NPCM_FIU_UMA_CFG_WDBPCK_SHIFT 4
  72. #define NPCM_FIU_UMA_CFG_DBPCK_SHIFT 6
  73. #define NPCM_FIU_UMA_CFG_RDBPCK_SHIFT 8
  74. #define NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT 11
  75. #define NPCM_FIU_UMA_CFG_WDATSIZ_SHIFT 16
  76. #define NPCM_FIU_UMA_CFG_DBSIZ_SHIFT 21
  77. #define NPCM_FIU_UMA_CFG_RDATSIZ_SHIFT 24
  78. /* FIU UMA Control and Status Register */
  79. #define NPCM_FIU_UMA_CTS_RDYIE BIT(25)
  80. #define NPCM_FIU_UMA_CTS_RDYST BIT(24)
  81. #define NPCM_FIU_UMA_CTS_SW_CS BIT(16)
  82. #define NPCM_FIU_UMA_CTS_DEV_NUM GENMASK(9, 8)
  83. #define NPCM_FIU_UMA_CTS_EXEC_DONE BIT(0)
  84. #define NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT 8
  85. /* FIU UMA Command Register */
  86. #define NPCM_FIU_UMA_CMD_DUM3 GENMASK(31, 24)
  87. #define NPCM_FIU_UMA_CMD_DUM2 GENMASK(23, 16)
  88. #define NPCM_FIU_UMA_CMD_DUM1 GENMASK(15, 8)
  89. #define NPCM_FIU_UMA_CMD_CMD GENMASK(7, 0)
  90. /* FIU UMA Address Register */
  91. #define NPCM_FIU_UMA_ADDR_UMA_ADDR GENMASK(31, 0)
  92. #define NPCM_FIU_UMA_ADDR_AB3 GENMASK(31, 24)
  93. #define NPCM_FIU_UMA_ADDR_AB2 GENMASK(23, 16)
  94. #define NPCM_FIU_UMA_ADDR_AB1 GENMASK(15, 8)
  95. #define NPCM_FIU_UMA_ADDR_AB0 GENMASK(7, 0)
  96. /* FIU UMA Write Data Bytes 0-3 Register */
  97. #define NPCM_FIU_UMA_DW0_WB3 GENMASK(31, 24)
  98. #define NPCM_FIU_UMA_DW0_WB2 GENMASK(23, 16)
  99. #define NPCM_FIU_UMA_DW0_WB1 GENMASK(15, 8)
  100. #define NPCM_FIU_UMA_DW0_WB0 GENMASK(7, 0)
  101. /* FIU UMA Write Data Bytes 4-7 Register */
  102. #define NPCM_FIU_UMA_DW1_WB7 GENMASK(31, 24)
  103. #define NPCM_FIU_UMA_DW1_WB6 GENMASK(23, 16)
  104. #define NPCM_FIU_UMA_DW1_WB5 GENMASK(15, 8)
  105. #define NPCM_FIU_UMA_DW1_WB4 GENMASK(7, 0)
  106. /* FIU UMA Write Data Bytes 8-11 Register */
  107. #define NPCM_FIU_UMA_DW2_WB11 GENMASK(31, 24)
  108. #define NPCM_FIU_UMA_DW2_WB10 GENMASK(23, 16)
  109. #define NPCM_FIU_UMA_DW2_WB9 GENMASK(15, 8)
  110. #define NPCM_FIU_UMA_DW2_WB8 GENMASK(7, 0)
  111. /* FIU UMA Write Data Bytes 12-15 Register */
  112. #define NPCM_FIU_UMA_DW3_WB15 GENMASK(31, 24)
  113. #define NPCM_FIU_UMA_DW3_WB14 GENMASK(23, 16)
  114. #define NPCM_FIU_UMA_DW3_WB13 GENMASK(15, 8)
  115. #define NPCM_FIU_UMA_DW3_WB12 GENMASK(7, 0)
  116. /* FIU UMA Read Data Bytes 0-3 Register */
  117. #define NPCM_FIU_UMA_DR0_RB3 GENMASK(31, 24)
  118. #define NPCM_FIU_UMA_DR0_RB2 GENMASK(23, 16)
  119. #define NPCM_FIU_UMA_DR0_RB1 GENMASK(15, 8)
  120. #define NPCM_FIU_UMA_DR0_RB0 GENMASK(7, 0)
  121. /* FIU UMA Read Data Bytes 4-7 Register */
  122. #define NPCM_FIU_UMA_DR1_RB15 GENMASK(31, 24)
  123. #define NPCM_FIU_UMA_DR1_RB14 GENMASK(23, 16)
  124. #define NPCM_FIU_UMA_DR1_RB13 GENMASK(15, 8)
  125. #define NPCM_FIU_UMA_DR1_RB12 GENMASK(7, 0)
  126. /* FIU UMA Read Data Bytes 8-11 Register */
  127. #define NPCM_FIU_UMA_DR2_RB15 GENMASK(31, 24)
  128. #define NPCM_FIU_UMA_DR2_RB14 GENMASK(23, 16)
  129. #define NPCM_FIU_UMA_DR2_RB13 GENMASK(15, 8)
  130. #define NPCM_FIU_UMA_DR2_RB12 GENMASK(7, 0)
  131. /* FIU UMA Read Data Bytes 12-15 Register */
  132. #define NPCM_FIU_UMA_DR3_RB15 GENMASK(31, 24)
  133. #define NPCM_FIU_UMA_DR3_RB14 GENMASK(23, 16)
  134. #define NPCM_FIU_UMA_DR3_RB13 GENMASK(15, 8)
  135. #define NPCM_FIU_UMA_DR3_RB12 GENMASK(7, 0)
  136. /* FIU Read Mode */
  137. enum {
  138. DRD_SINGLE_WIRE_MODE = 0,
  139. DRD_DUAL_IO_MODE = 1,
  140. DRD_QUAD_IO_MODE = 2,
  141. DRD_SPI_X_MODE = 3,
  142. };
  143. enum {
  144. DWR_ABPCK_BIT_PER_CLK = 0,
  145. DWR_ABPCK_2_BIT_PER_CLK = 1,
  146. DWR_ABPCK_4_BIT_PER_CLK = 2,
  147. };
  148. enum {
  149. DWR_DBPCK_BIT_PER_CLK = 0,
  150. DWR_DBPCK_2_BIT_PER_CLK = 1,
  151. DWR_DBPCK_4_BIT_PER_CLK = 2,
  152. };
  153. #define NPCM_FIU_DRD_16_BYTE_BURST 0x3000000
  154. #define NPCM_FIU_DWR_16_BYTE_BURST 0x3000000
  155. #define MAP_SIZE_128MB 0x8000000
  156. #define MAP_SIZE_16MB 0x1000000
  157. #define MAP_SIZE_8MB 0x800000
  158. #define FIU_DRD_MAX_DUMMY_NUMBER 3
  159. #define NPCM_MAX_CHIP_NUM 4
  160. #define CHUNK_SIZE 16
  161. #define UMA_MICRO_SEC_TIMEOUT 150
  162. enum {
  163. FIU0 = 0,
  164. FIU3,
  165. FIUX,
  166. };
  167. struct npcm_fiu_info {
  168. char *name;
  169. u32 fiu_id;
  170. u32 max_map_size;
  171. u32 max_cs;
  172. };
  173. struct fiu_data {
  174. const struct npcm_fiu_info *npcm_fiu_data_info;
  175. int fiu_max;
  176. };
  177. static const struct npcm_fiu_info npxm7xx_fiu_info[] = {
  178. {.name = "FIU0", .fiu_id = FIU0,
  179. .max_map_size = MAP_SIZE_128MB, .max_cs = 2},
  180. {.name = "FIU3", .fiu_id = FIU3,
  181. .max_map_size = MAP_SIZE_128MB, .max_cs = 4},
  182. {.name = "FIUX", .fiu_id = FIUX,
  183. .max_map_size = MAP_SIZE_16MB, .max_cs = 2} };
  184. static const struct fiu_data npxm7xx_fiu_data = {
  185. .npcm_fiu_data_info = npxm7xx_fiu_info,
  186. .fiu_max = 3,
  187. };
  188. struct npcm_fiu_spi;
  189. struct npcm_fiu_chip {
  190. void __iomem *flash_region_mapped_ptr;
  191. struct npcm_fiu_spi *fiu;
  192. unsigned long clkrate;
  193. u32 chipselect;
  194. };
  195. struct npcm_fiu_spi {
  196. struct npcm_fiu_chip chip[NPCM_MAX_CHIP_NUM];
  197. const struct npcm_fiu_info *info;
  198. struct spi_mem_op drd_op;
  199. struct resource *res_mem;
  200. struct regmap *regmap;
  201. unsigned long clkrate;
  202. struct device *dev;
  203. struct clk *clk;
  204. bool spix_mode;
  205. };
  206. static const struct regmap_config npcm_mtd_regmap_config = {
  207. .reg_bits = 32,
  208. .val_bits = 32,
  209. .reg_stride = 4,
  210. .max_register = NPCM_FIU_MAX_REG_LIMIT,
  211. };
  212. static void npcm_fiu_set_drd(struct npcm_fiu_spi *fiu,
  213. const struct spi_mem_op *op)
  214. {
  215. regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
  216. NPCM_FIU_DRD_CFG_ACCTYPE,
  217. ilog2(op->addr.buswidth) <<
  218. NPCM_FIU_DRD_ACCTYPE_SHIFT);
  219. fiu->drd_op.addr.buswidth = op->addr.buswidth;
  220. regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
  221. NPCM_FIU_DRD_CFG_DBW,
  222. ((op->dummy.nbytes * ilog2(op->addr.buswidth)) / BITS_PER_BYTE)
  223. << NPCM_FIU_DRD_DBW_SHIFT);
  224. fiu->drd_op.dummy.nbytes = op->dummy.nbytes;
  225. regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
  226. NPCM_FIU_DRD_CFG_RDCMD, op->cmd.opcode);
  227. fiu->drd_op.cmd.opcode = op->cmd.opcode;
  228. regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
  229. NPCM_FIU_DRD_CFG_ADDSIZ,
  230. (op->addr.nbytes - 3) << NPCM_FIU_DRD_ADDSIZ_SHIFT);
  231. fiu->drd_op.addr.nbytes = op->addr.nbytes;
  232. }
  233. static ssize_t npcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc,
  234. u64 offs, size_t len, void *buf)
  235. {
  236. struct npcm_fiu_spi *fiu =
  237. spi_controller_get_devdata(desc->mem->spi->master);
  238. struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select];
  239. void __iomem *src = (void __iomem *)(chip->flash_region_mapped_ptr +
  240. offs);
  241. u8 *buf_rx = buf;
  242. u32 i;
  243. if (fiu->spix_mode) {
  244. for (i = 0 ; i < len ; i++)
  245. *(buf_rx + i) = ioread8(src + i);
  246. } else {
  247. if (desc->info.op_tmpl.addr.buswidth != fiu->drd_op.addr.buswidth ||
  248. desc->info.op_tmpl.dummy.nbytes != fiu->drd_op.dummy.nbytes ||
  249. desc->info.op_tmpl.cmd.opcode != fiu->drd_op.cmd.opcode ||
  250. desc->info.op_tmpl.addr.nbytes != fiu->drd_op.addr.nbytes)
  251. npcm_fiu_set_drd(fiu, &desc->info.op_tmpl);
  252. memcpy_fromio(buf_rx, src, len);
  253. }
  254. return len;
  255. }
  256. static ssize_t npcm_fiu_direct_write(struct spi_mem_dirmap_desc *desc,
  257. u64 offs, size_t len, const void *buf)
  258. {
  259. struct npcm_fiu_spi *fiu =
  260. spi_controller_get_devdata(desc->mem->spi->master);
  261. struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select];
  262. void __iomem *dst = (void __iomem *)(chip->flash_region_mapped_ptr +
  263. offs);
  264. const u8 *buf_tx = buf;
  265. u32 i;
  266. if (fiu->spix_mode)
  267. for (i = 0 ; i < len ; i++)
  268. iowrite8(*(buf_tx + i), dst + i);
  269. else
  270. memcpy_toio(dst, buf_tx, len);
  271. return len;
  272. }
  273. static int npcm_fiu_uma_read(struct spi_mem *mem,
  274. const struct spi_mem_op *op, u32 addr,
  275. bool is_address_size, u8 *data, u32 data_size)
  276. {
  277. struct npcm_fiu_spi *fiu =
  278. spi_controller_get_devdata(mem->spi->master);
  279. u32 uma_cfg = BIT(10);
  280. u32 data_reg[4];
  281. int ret;
  282. u32 val;
  283. u32 i;
  284. regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
  285. NPCM_FIU_UMA_CTS_DEV_NUM,
  286. (mem->spi->chip_select <<
  287. NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT));
  288. regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD,
  289. NPCM_FIU_UMA_CMD_CMD, op->cmd.opcode);
  290. if (is_address_size) {
  291. uma_cfg |= ilog2(op->cmd.buswidth);
  292. uma_cfg |= ilog2(op->addr.buswidth)
  293. << NPCM_FIU_UMA_CFG_ADBPCK_SHIFT;
  294. uma_cfg |= ilog2(op->dummy.buswidth)
  295. << NPCM_FIU_UMA_CFG_DBPCK_SHIFT;
  296. uma_cfg |= ilog2(op->data.buswidth)
  297. << NPCM_FIU_UMA_CFG_RDBPCK_SHIFT;
  298. uma_cfg |= op->dummy.nbytes << NPCM_FIU_UMA_CFG_DBSIZ_SHIFT;
  299. uma_cfg |= op->addr.nbytes << NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT;
  300. regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, addr);
  301. } else {
  302. regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0);
  303. }
  304. uma_cfg |= data_size << NPCM_FIU_UMA_CFG_RDATSIZ_SHIFT;
  305. regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg);
  306. regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
  307. NPCM_FIU_UMA_CTS_EXEC_DONE,
  308. NPCM_FIU_UMA_CTS_EXEC_DONE);
  309. ret = regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val,
  310. (!(val & NPCM_FIU_UMA_CTS_EXEC_DONE)), 0,
  311. UMA_MICRO_SEC_TIMEOUT);
  312. if (ret)
  313. return ret;
  314. if (data_size) {
  315. for (i = 0; i < DIV_ROUND_UP(data_size, 4); i++)
  316. regmap_read(fiu->regmap, NPCM_FIU_UMA_DR0 + (i * 4),
  317. &data_reg[i]);
  318. memcpy(data, data_reg, data_size);
  319. }
  320. return 0;
  321. }
  322. static int npcm_fiu_uma_write(struct spi_mem *mem,
  323. const struct spi_mem_op *op, u8 cmd,
  324. bool is_address_size, u8 *data, u32 data_size)
  325. {
  326. struct npcm_fiu_spi *fiu =
  327. spi_controller_get_devdata(mem->spi->master);
  328. u32 uma_cfg = BIT(10);
  329. u32 data_reg[4] = {0};
  330. u32 val;
  331. u32 i;
  332. regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
  333. NPCM_FIU_UMA_CTS_DEV_NUM,
  334. (mem->spi->chip_select <<
  335. NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT));
  336. regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD,
  337. NPCM_FIU_UMA_CMD_CMD, cmd);
  338. if (data_size) {
  339. memcpy(data_reg, data, data_size);
  340. for (i = 0; i < DIV_ROUND_UP(data_size, 4); i++)
  341. regmap_write(fiu->regmap, NPCM_FIU_UMA_DW0 + (i * 4),
  342. data_reg[i]);
  343. }
  344. if (is_address_size) {
  345. uma_cfg |= ilog2(op->cmd.buswidth);
  346. uma_cfg |= ilog2(op->addr.buswidth) <<
  347. NPCM_FIU_UMA_CFG_ADBPCK_SHIFT;
  348. uma_cfg |= ilog2(op->data.buswidth) <<
  349. NPCM_FIU_UMA_CFG_WDBPCK_SHIFT;
  350. uma_cfg |= op->addr.nbytes << NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT;
  351. regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, op->addr.val);
  352. } else {
  353. regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0);
  354. }
  355. uma_cfg |= (data_size << NPCM_FIU_UMA_CFG_WDATSIZ_SHIFT);
  356. regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg);
  357. regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
  358. NPCM_FIU_UMA_CTS_EXEC_DONE,
  359. NPCM_FIU_UMA_CTS_EXEC_DONE);
  360. return regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val,
  361. (!(val & NPCM_FIU_UMA_CTS_EXEC_DONE)), 0,
  362. UMA_MICRO_SEC_TIMEOUT);
  363. }
  364. static int npcm_fiu_manualwrite(struct spi_mem *mem,
  365. const struct spi_mem_op *op)
  366. {
  367. struct npcm_fiu_spi *fiu =
  368. spi_controller_get_devdata(mem->spi->master);
  369. u8 *data = (u8 *)op->data.buf.out;
  370. u32 num_data_chunks;
  371. u32 remain_data;
  372. u32 idx = 0;
  373. int ret;
  374. num_data_chunks = op->data.nbytes / CHUNK_SIZE;
  375. remain_data = op->data.nbytes % CHUNK_SIZE;
  376. regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
  377. NPCM_FIU_UMA_CTS_DEV_NUM,
  378. (mem->spi->chip_select <<
  379. NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT));
  380. regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
  381. NPCM_FIU_UMA_CTS_SW_CS, 0);
  382. ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, true, NULL, 0);
  383. if (ret)
  384. return ret;
  385. /* Starting the data writing loop in multiples of 8 */
  386. for (idx = 0; idx < num_data_chunks; ++idx) {
  387. ret = npcm_fiu_uma_write(mem, op, data[0], false,
  388. &data[1], CHUNK_SIZE - 1);
  389. if (ret)
  390. return ret;
  391. data += CHUNK_SIZE;
  392. }
  393. /* Handling chunk remains */
  394. if (remain_data > 0) {
  395. ret = npcm_fiu_uma_write(mem, op, data[0], false,
  396. &data[1], remain_data - 1);
  397. if (ret)
  398. return ret;
  399. }
  400. regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
  401. NPCM_FIU_UMA_CTS_SW_CS, NPCM_FIU_UMA_CTS_SW_CS);
  402. return 0;
  403. }
  404. static int npcm_fiu_read(struct spi_mem *mem, const struct spi_mem_op *op)
  405. {
  406. u8 *data = op->data.buf.in;
  407. int i, readlen, currlen;
  408. u8 *buf_ptr;
  409. u32 addr;
  410. int ret;
  411. i = 0;
  412. currlen = op->data.nbytes;
  413. do {
  414. addr = ((u32)op->addr.val + i);
  415. if (currlen < 16)
  416. readlen = currlen;
  417. else
  418. readlen = 16;
  419. buf_ptr = data + i;
  420. ret = npcm_fiu_uma_read(mem, op, addr, true, buf_ptr,
  421. readlen);
  422. if (ret)
  423. return ret;
  424. i += readlen;
  425. currlen -= 16;
  426. } while (currlen > 0);
  427. return 0;
  428. }
  429. static void npcm_fiux_set_direct_wr(struct npcm_fiu_spi *fiu)
  430. {
  431. regmap_write(fiu->regmap, NPCM_FIU_DWR_CFG,
  432. NPCM_FIU_DWR_16_BYTE_BURST);
  433. regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG,
  434. NPCM_FIU_DWR_CFG_ABPCK,
  435. DWR_ABPCK_4_BIT_PER_CLK << NPCM_FIU_DWR_ABPCK_SHIFT);
  436. regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG,
  437. NPCM_FIU_DWR_CFG_DBPCK,
  438. DWR_DBPCK_4_BIT_PER_CLK << NPCM_FIU_DWR_DBPCK_SHIFT);
  439. }
  440. static void npcm_fiux_set_direct_rd(struct npcm_fiu_spi *fiu)
  441. {
  442. u32 rx_dummy = 0;
  443. regmap_write(fiu->regmap, NPCM_FIU_DRD_CFG,
  444. NPCM_FIU_DRD_16_BYTE_BURST);
  445. regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
  446. NPCM_FIU_DRD_CFG_ACCTYPE,
  447. DRD_SPI_X_MODE << NPCM_FIU_DRD_ACCTYPE_SHIFT);
  448. regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
  449. NPCM_FIU_DRD_CFG_DBW,
  450. rx_dummy << NPCM_FIU_DRD_DBW_SHIFT);
  451. }
  452. static int npcm_fiu_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
  453. {
  454. struct npcm_fiu_spi *fiu =
  455. spi_controller_get_devdata(mem->spi->master);
  456. struct npcm_fiu_chip *chip = &fiu->chip[mem->spi->chip_select];
  457. int ret = 0;
  458. u8 *buf;
  459. dev_dbg(fiu->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
  460. op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
  461. op->dummy.buswidth, op->data.buswidth, op->addr.val,
  462. op->data.nbytes);
  463. if (fiu->spix_mode || op->addr.nbytes > 4)
  464. return -ENOTSUPP;
  465. if (fiu->clkrate != chip->clkrate) {
  466. ret = clk_set_rate(fiu->clk, chip->clkrate);
  467. if (ret < 0)
  468. dev_warn(fiu->dev, "Failed setting %lu frequency, stay at %lu frequency\n",
  469. chip->clkrate, fiu->clkrate);
  470. else
  471. fiu->clkrate = chip->clkrate;
  472. }
  473. if (op->data.dir == SPI_MEM_DATA_IN) {
  474. if (!op->addr.nbytes) {
  475. buf = op->data.buf.in;
  476. ret = npcm_fiu_uma_read(mem, op, op->addr.val, false,
  477. buf, op->data.nbytes);
  478. } else {
  479. ret = npcm_fiu_read(mem, op);
  480. }
  481. } else {
  482. if (!op->addr.nbytes && !op->data.nbytes)
  483. ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false,
  484. NULL, 0);
  485. if (op->addr.nbytes && !op->data.nbytes) {
  486. int i;
  487. u8 buf_addr[4];
  488. u32 addr = op->addr.val;
  489. for (i = op->addr.nbytes - 1; i >= 0; i--) {
  490. buf_addr[i] = addr & 0xff;
  491. addr >>= 8;
  492. }
  493. ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false,
  494. buf_addr, op->addr.nbytes);
  495. }
  496. if (!op->addr.nbytes && op->data.nbytes)
  497. ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false,
  498. (u8 *)op->data.buf.out,
  499. op->data.nbytes);
  500. if (op->addr.nbytes && op->data.nbytes)
  501. ret = npcm_fiu_manualwrite(mem, op);
  502. }
  503. return ret;
  504. }
  505. static int npcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc)
  506. {
  507. struct npcm_fiu_spi *fiu =
  508. spi_controller_get_devdata(desc->mem->spi->master);
  509. struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select];
  510. struct regmap *gcr_regmap;
  511. if (!fiu->res_mem) {
  512. dev_warn(fiu->dev, "Reserved memory not defined, direct read disabled\n");
  513. desc->nodirmap = true;
  514. return 0;
  515. }
  516. if (!fiu->spix_mode &&
  517. desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) {
  518. desc->nodirmap = true;
  519. return 0;
  520. }
  521. if (!chip->flash_region_mapped_ptr) {
  522. chip->flash_region_mapped_ptr =
  523. devm_ioremap(fiu->dev, (fiu->res_mem->start +
  524. (fiu->info->max_map_size *
  525. desc->mem->spi->chip_select)),
  526. (u32)desc->info.length);
  527. if (!chip->flash_region_mapped_ptr) {
  528. dev_warn(fiu->dev, "Error mapping memory region, direct read disabled\n");
  529. desc->nodirmap = true;
  530. return 0;
  531. }
  532. }
  533. if (of_device_is_compatible(fiu->dev->of_node, "nuvoton,npcm750-fiu")) {
  534. gcr_regmap =
  535. syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
  536. if (IS_ERR(gcr_regmap)) {
  537. dev_warn(fiu->dev, "Didn't find nuvoton,npcm750-gcr, direct read disabled\n");
  538. desc->nodirmap = true;
  539. return 0;
  540. }
  541. regmap_update_bits(gcr_regmap, NPCM7XX_INTCR3_OFFSET,
  542. NPCM7XX_INTCR3_FIU_FIX,
  543. NPCM7XX_INTCR3_FIU_FIX);
  544. }
  545. if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) {
  546. if (!fiu->spix_mode)
  547. npcm_fiu_set_drd(fiu, &desc->info.op_tmpl);
  548. else
  549. npcm_fiux_set_direct_rd(fiu);
  550. } else {
  551. npcm_fiux_set_direct_wr(fiu);
  552. }
  553. return 0;
  554. }
  555. static int npcm_fiu_setup(struct spi_device *spi)
  556. {
  557. struct spi_controller *ctrl = spi->master;
  558. struct npcm_fiu_spi *fiu = spi_controller_get_devdata(ctrl);
  559. struct npcm_fiu_chip *chip;
  560. chip = &fiu->chip[spi->chip_select];
  561. chip->fiu = fiu;
  562. chip->chipselect = spi->chip_select;
  563. chip->clkrate = spi->max_speed_hz;
  564. fiu->clkrate = clk_get_rate(fiu->clk);
  565. return 0;
  566. }
  567. static const struct spi_controller_mem_ops npcm_fiu_mem_ops = {
  568. .exec_op = npcm_fiu_exec_op,
  569. .dirmap_create = npcm_fiu_dirmap_create,
  570. .dirmap_read = npcm_fiu_direct_read,
  571. .dirmap_write = npcm_fiu_direct_write,
  572. };
  573. static const struct of_device_id npcm_fiu_dt_ids[] = {
  574. { .compatible = "nuvoton,npcm750-fiu", .data = &npxm7xx_fiu_data },
  575. { /* sentinel */ }
  576. };
  577. static int npcm_fiu_probe(struct platform_device *pdev)
  578. {
  579. const struct fiu_data *fiu_data_match;
  580. const struct of_device_id *match;
  581. struct device *dev = &pdev->dev;
  582. struct spi_controller *ctrl;
  583. struct npcm_fiu_spi *fiu;
  584. void __iomem *regbase;
  585. struct resource *res;
  586. int id, ret;
  587. ctrl = devm_spi_alloc_master(dev, sizeof(*fiu));
  588. if (!ctrl)
  589. return -ENOMEM;
  590. fiu = spi_controller_get_devdata(ctrl);
  591. match = of_match_device(npcm_fiu_dt_ids, dev);
  592. if (!match || !match->data) {
  593. dev_err(dev, "No compatible OF match\n");
  594. return -ENODEV;
  595. }
  596. fiu_data_match = match->data;
  597. id = of_alias_get_id(dev->of_node, "fiu");
  598. if (id < 0 || id >= fiu_data_match->fiu_max) {
  599. dev_err(dev, "Invalid platform device id: %d\n", id);
  600. return -EINVAL;
  601. }
  602. fiu->info = &fiu_data_match->npcm_fiu_data_info[id];
  603. platform_set_drvdata(pdev, fiu);
  604. fiu->dev = dev;
  605. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control");
  606. regbase = devm_ioremap_resource(dev, res);
  607. if (IS_ERR(regbase))
  608. return PTR_ERR(regbase);
  609. fiu->regmap = devm_regmap_init_mmio(dev, regbase,
  610. &npcm_mtd_regmap_config);
  611. if (IS_ERR(fiu->regmap)) {
  612. dev_err(dev, "Failed to create regmap\n");
  613. return PTR_ERR(fiu->regmap);
  614. }
  615. fiu->res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  616. "memory");
  617. fiu->clk = devm_clk_get(dev, NULL);
  618. if (IS_ERR(fiu->clk))
  619. return PTR_ERR(fiu->clk);
  620. fiu->spix_mode = of_property_read_bool(dev->of_node,
  621. "nuvoton,spix-mode");
  622. platform_set_drvdata(pdev, fiu);
  623. clk_prepare_enable(fiu->clk);
  624. ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD
  625. | SPI_TX_DUAL | SPI_TX_QUAD;
  626. ctrl->setup = npcm_fiu_setup;
  627. ctrl->bus_num = -1;
  628. ctrl->mem_ops = &npcm_fiu_mem_ops;
  629. ctrl->num_chipselect = fiu->info->max_cs;
  630. ctrl->dev.of_node = dev->of_node;
  631. ret = devm_spi_register_master(dev, ctrl);
  632. if (ret)
  633. clk_disable_unprepare(fiu->clk);
  634. return ret;
  635. }
  636. static int npcm_fiu_remove(struct platform_device *pdev)
  637. {
  638. struct npcm_fiu_spi *fiu = platform_get_drvdata(pdev);
  639. clk_disable_unprepare(fiu->clk);
  640. return 0;
  641. }
  642. MODULE_DEVICE_TABLE(of, npcm_fiu_dt_ids);
  643. static struct platform_driver npcm_fiu_driver = {
  644. .driver = {
  645. .name = "NPCM-FIU",
  646. .bus = &platform_bus_type,
  647. .of_match_table = npcm_fiu_dt_ids,
  648. },
  649. .probe = npcm_fiu_probe,
  650. .remove = npcm_fiu_remove,
  651. };
  652. module_platform_driver(npcm_fiu_driver);
  653. MODULE_DESCRIPTION("Nuvoton FLASH Interface Unit SPI Controller Driver");
  654. MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
  655. MODULE_LICENSE("GPL v2");