spi-mxs.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Freescale MXS SPI master driver
  4. //
  5. // Copyright 2012 DENX Software Engineering, GmbH.
  6. // Copyright 2012 Freescale Semiconductor, Inc.
  7. // Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  8. //
  9. // Rework and transition to new API by:
  10. // Marek Vasut <marex@denx.de>
  11. //
  12. // Based on previous attempt by:
  13. // Fabio Estevam <fabio.estevam@freescale.com>
  14. //
  15. // Based on code from U-Boot bootloader by:
  16. // Marek Vasut <marex@denx.de>
  17. //
  18. // Based on spi-stmp.c, which is:
  19. // Author: Dmitry Pervushin <dimka@embeddedalley.com>
  20. #include <linux/kernel.h>
  21. #include <linux/ioport.h>
  22. #include <linux/of.h>
  23. #include <linux/of_device.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/delay.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/dma-mapping.h>
  28. #include <linux/dmaengine.h>
  29. #include <linux/highmem.h>
  30. #include <linux/clk.h>
  31. #include <linux/err.h>
  32. #include <linux/completion.h>
  33. #include <linux/pinctrl/consumer.h>
  34. #include <linux/regulator/consumer.h>
  35. #include <linux/pm_runtime.h>
  36. #include <linux/module.h>
  37. #include <linux/stmp_device.h>
  38. #include <linux/spi/spi.h>
  39. #include <linux/spi/mxs-spi.h>
  40. #include <trace/events/spi.h>
  41. #define DRIVER_NAME "mxs-spi"
  42. /* Use 10S timeout for very long transfers, it should suffice. */
  43. #define SSP_TIMEOUT 10000
  44. #define SG_MAXLEN 0xff00
  45. /*
  46. * Flags for txrx functions. More efficient that using an argument register for
  47. * each one.
  48. */
  49. #define TXRX_WRITE (1<<0) /* This is a write */
  50. #define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
  51. struct mxs_spi {
  52. struct mxs_ssp ssp;
  53. struct completion c;
  54. unsigned int sck; /* Rate requested (vs actual) */
  55. };
  56. static int mxs_spi_setup_transfer(struct spi_device *dev,
  57. const struct spi_transfer *t)
  58. {
  59. struct mxs_spi *spi = spi_master_get_devdata(dev->master);
  60. struct mxs_ssp *ssp = &spi->ssp;
  61. const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
  62. if (hz == 0) {
  63. dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
  64. return -EINVAL;
  65. }
  66. if (hz != spi->sck) {
  67. mxs_ssp_set_clk_rate(ssp, hz);
  68. /*
  69. * Save requested rate, hz, rather than the actual rate,
  70. * ssp->clk_rate. Otherwise we would set the rate every transfer
  71. * when the actual rate is not quite the same as requested rate.
  72. */
  73. spi->sck = hz;
  74. /*
  75. * Perhaps we should return an error if the actual clock is
  76. * nowhere close to what was requested?
  77. */
  78. }
  79. writel(BM_SSP_CTRL0_LOCK_CS,
  80. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
  81. writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
  82. BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
  83. ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
  84. ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
  85. ssp->base + HW_SSP_CTRL1(ssp));
  86. writel(0x0, ssp->base + HW_SSP_CMD0);
  87. writel(0x0, ssp->base + HW_SSP_CMD1);
  88. return 0;
  89. }
  90. static u32 mxs_spi_cs_to_reg(unsigned cs)
  91. {
  92. u32 select = 0;
  93. /*
  94. * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
  95. *
  96. * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
  97. * in HW_SSP_CTRL0 register do have multiple usage, please refer to
  98. * the datasheet for further details. In SPI mode, they are used to
  99. * toggle the chip-select lines (nCS pins).
  100. */
  101. if (cs & 1)
  102. select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
  103. if (cs & 2)
  104. select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
  105. return select;
  106. }
  107. static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
  108. {
  109. const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
  110. struct mxs_ssp *ssp = &spi->ssp;
  111. u32 reg;
  112. do {
  113. reg = readl_relaxed(ssp->base + offset);
  114. if (!set)
  115. reg = ~reg;
  116. reg &= mask;
  117. if (reg == mask)
  118. return 0;
  119. } while (time_before(jiffies, timeout));
  120. return -ETIMEDOUT;
  121. }
  122. static void mxs_ssp_dma_irq_callback(void *param)
  123. {
  124. struct mxs_spi *spi = param;
  125. complete(&spi->c);
  126. }
  127. static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
  128. {
  129. struct mxs_ssp *ssp = dev_id;
  130. dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
  131. __func__, __LINE__,
  132. readl(ssp->base + HW_SSP_CTRL1(ssp)),
  133. readl(ssp->base + HW_SSP_STATUS(ssp)));
  134. return IRQ_HANDLED;
  135. }
  136. static int mxs_spi_txrx_dma(struct mxs_spi *spi,
  137. unsigned char *buf, int len,
  138. unsigned int flags)
  139. {
  140. struct mxs_ssp *ssp = &spi->ssp;
  141. struct dma_async_tx_descriptor *desc = NULL;
  142. const bool vmalloced_buf = is_vmalloc_addr(buf);
  143. const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
  144. const int sgs = DIV_ROUND_UP(len, desc_len);
  145. int sg_count;
  146. int min, ret;
  147. u32 ctrl0;
  148. struct page *vm_page;
  149. struct {
  150. u32 pio[4];
  151. struct scatterlist sg;
  152. } *dma_xfer;
  153. if (!len)
  154. return -EINVAL;
  155. dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL);
  156. if (!dma_xfer)
  157. return -ENOMEM;
  158. reinit_completion(&spi->c);
  159. /* Chip select was already programmed into CTRL0 */
  160. ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
  161. ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
  162. BM_SSP_CTRL0_READ);
  163. ctrl0 |= BM_SSP_CTRL0_DATA_XFER;
  164. if (!(flags & TXRX_WRITE))
  165. ctrl0 |= BM_SSP_CTRL0_READ;
  166. /* Queue the DMA data transfer. */
  167. for (sg_count = 0; sg_count < sgs; sg_count++) {
  168. /* Prepare the transfer descriptor. */
  169. min = min(len, desc_len);
  170. /*
  171. * De-assert CS on last segment if flag is set (i.e., no more
  172. * transfers will follow)
  173. */
  174. if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
  175. ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;
  176. if (ssp->devid == IMX23_SSP) {
  177. ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
  178. ctrl0 |= min;
  179. }
  180. dma_xfer[sg_count].pio[0] = ctrl0;
  181. dma_xfer[sg_count].pio[3] = min;
  182. if (vmalloced_buf) {
  183. vm_page = vmalloc_to_page(buf);
  184. if (!vm_page) {
  185. ret = -ENOMEM;
  186. goto err_vmalloc;
  187. }
  188. sg_init_table(&dma_xfer[sg_count].sg, 1);
  189. sg_set_page(&dma_xfer[sg_count].sg, vm_page,
  190. min, offset_in_page(buf));
  191. } else {
  192. sg_init_one(&dma_xfer[sg_count].sg, buf, min);
  193. }
  194. ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
  195. (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  196. len -= min;
  197. buf += min;
  198. /* Queue the PIO register write transfer. */
  199. desc = dmaengine_prep_slave_sg(ssp->dmach,
  200. (struct scatterlist *)dma_xfer[sg_count].pio,
  201. (ssp->devid == IMX23_SSP) ? 1 : 4,
  202. DMA_TRANS_NONE,
  203. sg_count ? DMA_PREP_INTERRUPT : 0);
  204. if (!desc) {
  205. dev_err(ssp->dev,
  206. "Failed to get PIO reg. write descriptor.\n");
  207. ret = -EINVAL;
  208. goto err_mapped;
  209. }
  210. desc = dmaengine_prep_slave_sg(ssp->dmach,
  211. &dma_xfer[sg_count].sg, 1,
  212. (flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
  213. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  214. if (!desc) {
  215. dev_err(ssp->dev,
  216. "Failed to get DMA data write descriptor.\n");
  217. ret = -EINVAL;
  218. goto err_mapped;
  219. }
  220. }
  221. /*
  222. * The last descriptor must have this callback,
  223. * to finish the DMA transaction.
  224. */
  225. desc->callback = mxs_ssp_dma_irq_callback;
  226. desc->callback_param = spi;
  227. /* Start the transfer. */
  228. dmaengine_submit(desc);
  229. dma_async_issue_pending(ssp->dmach);
  230. if (!wait_for_completion_timeout(&spi->c,
  231. msecs_to_jiffies(SSP_TIMEOUT))) {
  232. dev_err(ssp->dev, "DMA transfer timeout\n");
  233. ret = -ETIMEDOUT;
  234. dmaengine_terminate_all(ssp->dmach);
  235. goto err_vmalloc;
  236. }
  237. ret = 0;
  238. err_vmalloc:
  239. while (--sg_count >= 0) {
  240. err_mapped:
  241. dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
  242. (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  243. }
  244. kfree(dma_xfer);
  245. return ret;
  246. }
  247. static int mxs_spi_txrx_pio(struct mxs_spi *spi,
  248. unsigned char *buf, int len,
  249. unsigned int flags)
  250. {
  251. struct mxs_ssp *ssp = &spi->ssp;
  252. writel(BM_SSP_CTRL0_IGNORE_CRC,
  253. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
  254. while (len--) {
  255. if (len == 0 && (flags & TXRX_DEASSERT_CS))
  256. writel(BM_SSP_CTRL0_IGNORE_CRC,
  257. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
  258. if (ssp->devid == IMX23_SSP) {
  259. writel(BM_SSP_CTRL0_XFER_COUNT,
  260. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
  261. writel(1,
  262. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
  263. } else {
  264. writel(1, ssp->base + HW_SSP_XFER_SIZE);
  265. }
  266. if (flags & TXRX_WRITE)
  267. writel(BM_SSP_CTRL0_READ,
  268. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
  269. else
  270. writel(BM_SSP_CTRL0_READ,
  271. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
  272. writel(BM_SSP_CTRL0_RUN,
  273. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
  274. if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
  275. return -ETIMEDOUT;
  276. if (flags & TXRX_WRITE)
  277. writel(*buf, ssp->base + HW_SSP_DATA(ssp));
  278. writel(BM_SSP_CTRL0_DATA_XFER,
  279. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
  280. if (!(flags & TXRX_WRITE)) {
  281. if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
  282. BM_SSP_STATUS_FIFO_EMPTY, 0))
  283. return -ETIMEDOUT;
  284. *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
  285. }
  286. if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
  287. return -ETIMEDOUT;
  288. buf++;
  289. }
  290. if (len <= 0)
  291. return 0;
  292. return -ETIMEDOUT;
  293. }
  294. static int mxs_spi_transfer_one(struct spi_master *master,
  295. struct spi_message *m)
  296. {
  297. struct mxs_spi *spi = spi_master_get_devdata(master);
  298. struct mxs_ssp *ssp = &spi->ssp;
  299. struct spi_transfer *t;
  300. unsigned int flag;
  301. int status = 0;
  302. /* Program CS register bits here, it will be used for all transfers. */
  303. writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
  304. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
  305. writel(mxs_spi_cs_to_reg(m->spi->chip_select),
  306. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
  307. list_for_each_entry(t, &m->transfers, transfer_list) {
  308. trace_spi_transfer_start(m, t);
  309. status = mxs_spi_setup_transfer(m->spi, t);
  310. if (status)
  311. break;
  312. /* De-assert on last transfer, inverted by cs_change flag */
  313. flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
  314. TXRX_DEASSERT_CS : 0;
  315. /*
  316. * Small blocks can be transfered via PIO.
  317. * Measured by empiric means:
  318. *
  319. * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
  320. *
  321. * DMA only: 2.164808 seconds, 473.0KB/s
  322. * Combined: 1.676276 seconds, 610.9KB/s
  323. */
  324. if (t->len < 32) {
  325. writel(BM_SSP_CTRL1_DMA_ENABLE,
  326. ssp->base + HW_SSP_CTRL1(ssp) +
  327. STMP_OFFSET_REG_CLR);
  328. if (t->tx_buf)
  329. status = mxs_spi_txrx_pio(spi,
  330. (void *)t->tx_buf,
  331. t->len, flag | TXRX_WRITE);
  332. if (t->rx_buf)
  333. status = mxs_spi_txrx_pio(spi,
  334. t->rx_buf, t->len,
  335. flag);
  336. } else {
  337. writel(BM_SSP_CTRL1_DMA_ENABLE,
  338. ssp->base + HW_SSP_CTRL1(ssp) +
  339. STMP_OFFSET_REG_SET);
  340. if (t->tx_buf)
  341. status = mxs_spi_txrx_dma(spi,
  342. (void *)t->tx_buf, t->len,
  343. flag | TXRX_WRITE);
  344. if (t->rx_buf)
  345. status = mxs_spi_txrx_dma(spi,
  346. t->rx_buf, t->len,
  347. flag);
  348. }
  349. trace_spi_transfer_stop(m, t);
  350. if (status) {
  351. stmp_reset_block(ssp->base);
  352. break;
  353. }
  354. m->actual_length += t->len;
  355. }
  356. m->status = status;
  357. spi_finalize_current_message(master);
  358. return status;
  359. }
  360. static int mxs_spi_runtime_suspend(struct device *dev)
  361. {
  362. struct spi_master *master = dev_get_drvdata(dev);
  363. struct mxs_spi *spi = spi_master_get_devdata(master);
  364. struct mxs_ssp *ssp = &spi->ssp;
  365. int ret;
  366. clk_disable_unprepare(ssp->clk);
  367. ret = pinctrl_pm_select_idle_state(dev);
  368. if (ret) {
  369. int ret2 = clk_prepare_enable(ssp->clk);
  370. if (ret2)
  371. dev_warn(dev, "Failed to reenable clock after failing pinctrl request (pinctrl: %d, clk: %d)\n",
  372. ret, ret2);
  373. }
  374. return ret;
  375. }
  376. static int mxs_spi_runtime_resume(struct device *dev)
  377. {
  378. struct spi_master *master = dev_get_drvdata(dev);
  379. struct mxs_spi *spi = spi_master_get_devdata(master);
  380. struct mxs_ssp *ssp = &spi->ssp;
  381. int ret;
  382. ret = pinctrl_pm_select_default_state(dev);
  383. if (ret)
  384. return ret;
  385. ret = clk_prepare_enable(ssp->clk);
  386. if (ret)
  387. pinctrl_pm_select_idle_state(dev);
  388. return ret;
  389. }
  390. static int __maybe_unused mxs_spi_suspend(struct device *dev)
  391. {
  392. struct spi_master *master = dev_get_drvdata(dev);
  393. int ret;
  394. ret = spi_master_suspend(master);
  395. if (ret)
  396. return ret;
  397. if (!pm_runtime_suspended(dev))
  398. return mxs_spi_runtime_suspend(dev);
  399. else
  400. return 0;
  401. }
  402. static int __maybe_unused mxs_spi_resume(struct device *dev)
  403. {
  404. struct spi_master *master = dev_get_drvdata(dev);
  405. int ret;
  406. if (!pm_runtime_suspended(dev))
  407. ret = mxs_spi_runtime_resume(dev);
  408. else
  409. ret = 0;
  410. if (ret)
  411. return ret;
  412. ret = spi_master_resume(master);
  413. if (ret < 0 && !pm_runtime_suspended(dev))
  414. mxs_spi_runtime_suspend(dev);
  415. return ret;
  416. }
  417. static const struct dev_pm_ops mxs_spi_pm = {
  418. SET_RUNTIME_PM_OPS(mxs_spi_runtime_suspend,
  419. mxs_spi_runtime_resume, NULL)
  420. SET_SYSTEM_SLEEP_PM_OPS(mxs_spi_suspend, mxs_spi_resume)
  421. };
  422. static const struct of_device_id mxs_spi_dt_ids[] = {
  423. { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
  424. { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
  425. { /* sentinel */ }
  426. };
  427. MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
  428. static int mxs_spi_probe(struct platform_device *pdev)
  429. {
  430. const struct of_device_id *of_id =
  431. of_match_device(mxs_spi_dt_ids, &pdev->dev);
  432. struct device_node *np = pdev->dev.of_node;
  433. struct spi_master *master;
  434. struct mxs_spi *spi;
  435. struct mxs_ssp *ssp;
  436. struct clk *clk;
  437. void __iomem *base;
  438. int devid, clk_freq;
  439. int ret = 0, irq_err;
  440. /*
  441. * Default clock speed for the SPI core. 160MHz seems to
  442. * work reasonably well with most SPI flashes, so use this
  443. * as a default. Override with "clock-frequency" DT prop.
  444. */
  445. const int clk_freq_default = 160000000;
  446. irq_err = platform_get_irq(pdev, 0);
  447. if (irq_err < 0)
  448. return irq_err;
  449. base = devm_platform_ioremap_resource(pdev, 0);
  450. if (IS_ERR(base))
  451. return PTR_ERR(base);
  452. clk = devm_clk_get(&pdev->dev, NULL);
  453. if (IS_ERR(clk))
  454. return PTR_ERR(clk);
  455. devid = (enum mxs_ssp_id) of_id->data;
  456. ret = of_property_read_u32(np, "clock-frequency",
  457. &clk_freq);
  458. if (ret)
  459. clk_freq = clk_freq_default;
  460. master = spi_alloc_master(&pdev->dev, sizeof(*spi));
  461. if (!master)
  462. return -ENOMEM;
  463. platform_set_drvdata(pdev, master);
  464. master->transfer_one_message = mxs_spi_transfer_one;
  465. master->bits_per_word_mask = SPI_BPW_MASK(8);
  466. master->mode_bits = SPI_CPOL | SPI_CPHA;
  467. master->num_chipselect = 3;
  468. master->dev.of_node = np;
  469. master->flags = SPI_MASTER_HALF_DUPLEX;
  470. master->auto_runtime_pm = true;
  471. spi = spi_master_get_devdata(master);
  472. ssp = &spi->ssp;
  473. ssp->dev = &pdev->dev;
  474. ssp->clk = clk;
  475. ssp->base = base;
  476. ssp->devid = devid;
  477. init_completion(&spi->c);
  478. ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
  479. dev_name(&pdev->dev), ssp);
  480. if (ret)
  481. goto out_master_free;
  482. ssp->dmach = dma_request_chan(&pdev->dev, "rx-tx");
  483. if (IS_ERR(ssp->dmach)) {
  484. dev_err(ssp->dev, "Failed to request DMA\n");
  485. ret = PTR_ERR(ssp->dmach);
  486. goto out_master_free;
  487. }
  488. pm_runtime_enable(ssp->dev);
  489. if (!pm_runtime_enabled(ssp->dev)) {
  490. ret = mxs_spi_runtime_resume(ssp->dev);
  491. if (ret < 0) {
  492. dev_err(ssp->dev, "runtime resume failed\n");
  493. goto out_dma_release;
  494. }
  495. }
  496. ret = pm_runtime_get_sync(ssp->dev);
  497. if (ret < 0) {
  498. pm_runtime_put_noidle(ssp->dev);
  499. dev_err(ssp->dev, "runtime_get_sync failed\n");
  500. goto out_pm_runtime_disable;
  501. }
  502. clk_set_rate(ssp->clk, clk_freq);
  503. ret = stmp_reset_block(ssp->base);
  504. if (ret)
  505. goto out_pm_runtime_put;
  506. ret = devm_spi_register_master(&pdev->dev, master);
  507. if (ret) {
  508. dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
  509. goto out_pm_runtime_put;
  510. }
  511. pm_runtime_put(ssp->dev);
  512. return 0;
  513. out_pm_runtime_put:
  514. pm_runtime_put(ssp->dev);
  515. out_pm_runtime_disable:
  516. pm_runtime_disable(ssp->dev);
  517. out_dma_release:
  518. dma_release_channel(ssp->dmach);
  519. out_master_free:
  520. spi_master_put(master);
  521. return ret;
  522. }
  523. static int mxs_spi_remove(struct platform_device *pdev)
  524. {
  525. struct spi_master *master;
  526. struct mxs_spi *spi;
  527. struct mxs_ssp *ssp;
  528. master = platform_get_drvdata(pdev);
  529. spi = spi_master_get_devdata(master);
  530. ssp = &spi->ssp;
  531. pm_runtime_disable(&pdev->dev);
  532. if (!pm_runtime_status_suspended(&pdev->dev))
  533. mxs_spi_runtime_suspend(&pdev->dev);
  534. dma_release_channel(ssp->dmach);
  535. return 0;
  536. }
  537. static struct platform_driver mxs_spi_driver = {
  538. .probe = mxs_spi_probe,
  539. .remove = mxs_spi_remove,
  540. .driver = {
  541. .name = DRIVER_NAME,
  542. .of_match_table = mxs_spi_dt_ids,
  543. .pm = &mxs_spi_pm,
  544. },
  545. };
  546. module_platform_driver(mxs_spi_driver);
  547. MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
  548. MODULE_DESCRIPTION("MXS SPI master driver");
  549. MODULE_LICENSE("GPL");
  550. MODULE_ALIAS("platform:mxs-spi");