spi-mxic.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (C) 2018 Macronix International Co., Ltd.
  4. //
  5. // Authors:
  6. // Mason Yang <masonccyang@mxic.com.tw>
  7. // zhengxunli <zhengxunli@mxic.com.tw>
  8. // Boris Brezillon <boris.brezillon@bootlin.com>
  9. //
  10. #include <linux/clk.h>
  11. #include <linux/io.h>
  12. #include <linux/iopoll.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/spi/spi.h>
  17. #include <linux/spi/spi-mem.h>
  18. #define HC_CFG 0x0
  19. #define HC_CFG_IF_CFG(x) ((x) << 27)
  20. #define HC_CFG_DUAL_SLAVE BIT(31)
  21. #define HC_CFG_INDIVIDUAL BIT(30)
  22. #define HC_CFG_NIO(x) (((x) / 4) << 27)
  23. #define HC_CFG_TYPE(s, t) ((t) << (23 + ((s) * 2)))
  24. #define HC_CFG_TYPE_SPI_NOR 0
  25. #define HC_CFG_TYPE_SPI_NAND 1
  26. #define HC_CFG_TYPE_SPI_RAM 2
  27. #define HC_CFG_TYPE_RAW_NAND 3
  28. #define HC_CFG_SLV_ACT(x) ((x) << 21)
  29. #define HC_CFG_CLK_PH_EN BIT(20)
  30. #define HC_CFG_CLK_POL_INV BIT(19)
  31. #define HC_CFG_BIG_ENDIAN BIT(18)
  32. #define HC_CFG_DATA_PASS BIT(17)
  33. #define HC_CFG_IDLE_SIO_LVL(x) ((x) << 16)
  34. #define HC_CFG_MAN_START_EN BIT(3)
  35. #define HC_CFG_MAN_START BIT(2)
  36. #define HC_CFG_MAN_CS_EN BIT(1)
  37. #define HC_CFG_MAN_CS_ASSERT BIT(0)
  38. #define INT_STS 0x4
  39. #define INT_STS_EN 0x8
  40. #define INT_SIG_EN 0xc
  41. #define INT_STS_ALL GENMASK(31, 0)
  42. #define INT_RDY_PIN BIT(26)
  43. #define INT_RDY_SR BIT(25)
  44. #define INT_LNR_SUSP BIT(24)
  45. #define INT_ECC_ERR BIT(17)
  46. #define INT_CRC_ERR BIT(16)
  47. #define INT_LWR_DIS BIT(12)
  48. #define INT_LRD_DIS BIT(11)
  49. #define INT_SDMA_INT BIT(10)
  50. #define INT_DMA_FINISH BIT(9)
  51. #define INT_RX_NOT_FULL BIT(3)
  52. #define INT_RX_NOT_EMPTY BIT(2)
  53. #define INT_TX_NOT_FULL BIT(1)
  54. #define INT_TX_EMPTY BIT(0)
  55. #define HC_EN 0x10
  56. #define HC_EN_BIT BIT(0)
  57. #define TXD(x) (0x14 + ((x) * 4))
  58. #define RXD 0x24
  59. #define SS_CTRL(s) (0x30 + ((s) * 4))
  60. #define LRD_CFG 0x44
  61. #define LWR_CFG 0x80
  62. #define RWW_CFG 0x70
  63. #define OP_READ BIT(23)
  64. #define OP_DUMMY_CYC(x) ((x) << 17)
  65. #define OP_ADDR_BYTES(x) ((x) << 14)
  66. #define OP_CMD_BYTES(x) (((x) - 1) << 13)
  67. #define OP_OCTA_CRC_EN BIT(12)
  68. #define OP_DQS_EN BIT(11)
  69. #define OP_ENHC_EN BIT(10)
  70. #define OP_PREAMBLE_EN BIT(9)
  71. #define OP_DATA_DDR BIT(8)
  72. #define OP_DATA_BUSW(x) ((x) << 6)
  73. #define OP_ADDR_DDR BIT(5)
  74. #define OP_ADDR_BUSW(x) ((x) << 3)
  75. #define OP_CMD_DDR BIT(2)
  76. #define OP_CMD_BUSW(x) (x)
  77. #define OP_BUSW_1 0
  78. #define OP_BUSW_2 1
  79. #define OP_BUSW_4 2
  80. #define OP_BUSW_8 3
  81. #define OCTA_CRC 0x38
  82. #define OCTA_CRC_IN_EN(s) BIT(3 + ((s) * 16))
  83. #define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16)))
  84. #define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16))
  85. #define ONFI_DIN_CNT(s) (0x3c + (s))
  86. #define LRD_CTRL 0x48
  87. #define RWW_CTRL 0x74
  88. #define LWR_CTRL 0x84
  89. #define LMODE_EN BIT(31)
  90. #define LMODE_SLV_ACT(x) ((x) << 21)
  91. #define LMODE_CMD1(x) ((x) << 8)
  92. #define LMODE_CMD0(x) (x)
  93. #define LRD_ADDR 0x4c
  94. #define LWR_ADDR 0x88
  95. #define LRD_RANGE 0x50
  96. #define LWR_RANGE 0x8c
  97. #define AXI_SLV_ADDR 0x54
  98. #define DMAC_RD_CFG 0x58
  99. #define DMAC_WR_CFG 0x94
  100. #define DMAC_CFG_PERIPH_EN BIT(31)
  101. #define DMAC_CFG_ALLFLUSH_EN BIT(30)
  102. #define DMAC_CFG_LASTFLUSH_EN BIT(29)
  103. #define DMAC_CFG_QE(x) (((x) + 1) << 16)
  104. #define DMAC_CFG_BURST_LEN(x) (((x) + 1) << 12)
  105. #define DMAC_CFG_BURST_SZ(x) ((x) << 8)
  106. #define DMAC_CFG_DIR_READ BIT(1)
  107. #define DMAC_CFG_START BIT(0)
  108. #define DMAC_RD_CNT 0x5c
  109. #define DMAC_WR_CNT 0x98
  110. #define SDMA_ADDR 0x60
  111. #define DMAM_CFG 0x64
  112. #define DMAM_CFG_START BIT(31)
  113. #define DMAM_CFG_CONT BIT(30)
  114. #define DMAM_CFG_SDMA_GAP(x) (fls((x) / 8192) << 2)
  115. #define DMAM_CFG_DIR_READ BIT(1)
  116. #define DMAM_CFG_EN BIT(0)
  117. #define DMAM_CNT 0x68
  118. #define LNR_TIMER_TH 0x6c
  119. #define RDM_CFG0 0x78
  120. #define RDM_CFG0_POLY(x) (x)
  121. #define RDM_CFG1 0x7c
  122. #define RDM_CFG1_RDM_EN BIT(31)
  123. #define RDM_CFG1_SEED(x) (x)
  124. #define LWR_SUSP_CTRL 0x90
  125. #define LWR_SUSP_CTRL_EN BIT(31)
  126. #define DMAS_CTRL 0x9c
  127. #define DMAS_CTRL_EN BIT(31)
  128. #define DMAS_CTRL_DIR_READ BIT(30)
  129. #define DATA_STROB 0xa0
  130. #define DATA_STROB_EDO_EN BIT(2)
  131. #define DATA_STROB_INV_POL BIT(1)
  132. #define DATA_STROB_DELAY_2CYC BIT(0)
  133. #define IDLY_CODE(x) (0xa4 + ((x) * 4))
  134. #define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8))
  135. #define GPIO 0xc4
  136. #define GPIO_PT(x) BIT(3 + ((x) * 16))
  137. #define GPIO_RESET(x) BIT(2 + ((x) * 16))
  138. #define GPIO_HOLDB(x) BIT(1 + ((x) * 16))
  139. #define GPIO_WPB(x) BIT((x) * 16)
  140. #define HC_VER 0xd0
  141. #define HW_TEST(x) (0xe0 + ((x) * 4))
  142. struct mxic_spi {
  143. struct clk *ps_clk;
  144. struct clk *send_clk;
  145. struct clk *send_dly_clk;
  146. void __iomem *regs;
  147. u32 cur_speed_hz;
  148. };
  149. static int mxic_spi_clk_enable(struct mxic_spi *mxic)
  150. {
  151. int ret;
  152. ret = clk_prepare_enable(mxic->send_clk);
  153. if (ret)
  154. return ret;
  155. ret = clk_prepare_enable(mxic->send_dly_clk);
  156. if (ret)
  157. goto err_send_dly_clk;
  158. return ret;
  159. err_send_dly_clk:
  160. clk_disable_unprepare(mxic->send_clk);
  161. return ret;
  162. }
  163. static void mxic_spi_clk_disable(struct mxic_spi *mxic)
  164. {
  165. clk_disable_unprepare(mxic->send_clk);
  166. clk_disable_unprepare(mxic->send_dly_clk);
  167. }
  168. static void mxic_spi_set_input_delay_dqs(struct mxic_spi *mxic, u8 idly_code)
  169. {
  170. writel(IDLY_CODE_VAL(0, idly_code) |
  171. IDLY_CODE_VAL(1, idly_code) |
  172. IDLY_CODE_VAL(2, idly_code) |
  173. IDLY_CODE_VAL(3, idly_code),
  174. mxic->regs + IDLY_CODE(0));
  175. writel(IDLY_CODE_VAL(4, idly_code) |
  176. IDLY_CODE_VAL(5, idly_code) |
  177. IDLY_CODE_VAL(6, idly_code) |
  178. IDLY_CODE_VAL(7, idly_code),
  179. mxic->regs + IDLY_CODE(1));
  180. }
  181. static int mxic_spi_clk_setup(struct mxic_spi *mxic, unsigned long freq)
  182. {
  183. int ret;
  184. ret = clk_set_rate(mxic->send_clk, freq);
  185. if (ret)
  186. return ret;
  187. ret = clk_set_rate(mxic->send_dly_clk, freq);
  188. if (ret)
  189. return ret;
  190. /*
  191. * A constant delay range from 0x0 ~ 0x1F for input delay,
  192. * the unit is 78 ps, the max input delay is 2.418 ns.
  193. */
  194. mxic_spi_set_input_delay_dqs(mxic, 0xf);
  195. /*
  196. * Phase degree = 360 * freq * output-delay
  197. * where output-delay is a constant value 1 ns in FPGA.
  198. *
  199. * Get Phase degree = 360 * freq * 1 ns
  200. * = 360 * freq * 1 sec / 1000000000
  201. * = 9 * freq / 25000000
  202. */
  203. ret = clk_set_phase(mxic->send_dly_clk, 9 * freq / 25000000);
  204. if (ret)
  205. return ret;
  206. return 0;
  207. }
  208. static int mxic_spi_set_freq(struct mxic_spi *mxic, unsigned long freq)
  209. {
  210. int ret;
  211. if (mxic->cur_speed_hz == freq)
  212. return 0;
  213. mxic_spi_clk_disable(mxic);
  214. ret = mxic_spi_clk_setup(mxic, freq);
  215. if (ret)
  216. return ret;
  217. ret = mxic_spi_clk_enable(mxic);
  218. if (ret)
  219. return ret;
  220. mxic->cur_speed_hz = freq;
  221. return 0;
  222. }
  223. static void mxic_spi_hw_init(struct mxic_spi *mxic)
  224. {
  225. writel(0, mxic->regs + DATA_STROB);
  226. writel(INT_STS_ALL, mxic->regs + INT_STS_EN);
  227. writel(0, mxic->regs + HC_EN);
  228. writel(0, mxic->regs + LRD_CFG);
  229. writel(0, mxic->regs + LRD_CTRL);
  230. writel(HC_CFG_NIO(1) | HC_CFG_TYPE(0, HC_CFG_TYPE_SPI_NOR) |
  231. HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN | HC_CFG_IDLE_SIO_LVL(1),
  232. mxic->regs + HC_CFG);
  233. }
  234. static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
  235. void *rxbuf, unsigned int len)
  236. {
  237. unsigned int pos = 0;
  238. while (pos < len) {
  239. unsigned int nbytes = len - pos;
  240. u32 data = 0xffffffff;
  241. u32 sts;
  242. int ret;
  243. if (nbytes > 4)
  244. nbytes = 4;
  245. if (txbuf)
  246. memcpy(&data, txbuf + pos, nbytes);
  247. ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
  248. sts & INT_TX_EMPTY, 0, USEC_PER_SEC);
  249. if (ret)
  250. return ret;
  251. writel(data, mxic->regs + TXD(nbytes % 4));
  252. ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
  253. sts & INT_TX_EMPTY, 0, USEC_PER_SEC);
  254. if (ret)
  255. return ret;
  256. ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
  257. sts & INT_RX_NOT_EMPTY, 0,
  258. USEC_PER_SEC);
  259. if (ret)
  260. return ret;
  261. data = readl(mxic->regs + RXD);
  262. if (rxbuf) {
  263. data >>= (8 * (4 - nbytes));
  264. memcpy(rxbuf + pos, &data, nbytes);
  265. }
  266. WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
  267. pos += nbytes;
  268. }
  269. return 0;
  270. }
  271. static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
  272. const struct spi_mem_op *op)
  273. {
  274. if (op->data.buswidth > 4 || op->addr.buswidth > 4 ||
  275. op->dummy.buswidth > 4 || op->cmd.buswidth > 4)
  276. return false;
  277. if (op->data.nbytes && op->dummy.nbytes &&
  278. op->data.buswidth != op->dummy.buswidth)
  279. return false;
  280. if (op->addr.nbytes > 7)
  281. return false;
  282. return spi_mem_default_supports_op(mem, op);
  283. }
  284. static int mxic_spi_mem_exec_op(struct spi_mem *mem,
  285. const struct spi_mem_op *op)
  286. {
  287. struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master);
  288. int nio = 1, i, ret;
  289. u32 ss_ctrl;
  290. u8 addr[8];
  291. u8 opcode = op->cmd.opcode;
  292. ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz);
  293. if (ret)
  294. return ret;
  295. if (mem->spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
  296. nio = 4;
  297. else if (mem->spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
  298. nio = 2;
  299. writel(HC_CFG_NIO(nio) |
  300. HC_CFG_TYPE(mem->spi->chip_select, HC_CFG_TYPE_SPI_NOR) |
  301. HC_CFG_SLV_ACT(mem->spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1) |
  302. HC_CFG_MAN_CS_EN,
  303. mxic->regs + HC_CFG);
  304. writel(HC_EN_BIT, mxic->regs + HC_EN);
  305. ss_ctrl = OP_CMD_BYTES(1) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1);
  306. if (op->addr.nbytes)
  307. ss_ctrl |= OP_ADDR_BYTES(op->addr.nbytes) |
  308. OP_ADDR_BUSW(fls(op->addr.buswidth) - 1);
  309. if (op->dummy.nbytes)
  310. ss_ctrl |= OP_DUMMY_CYC(op->dummy.nbytes);
  311. if (op->data.nbytes) {
  312. ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1);
  313. if (op->data.dir == SPI_MEM_DATA_IN)
  314. ss_ctrl |= OP_READ;
  315. }
  316. writel(ss_ctrl, mxic->regs + SS_CTRL(mem->spi->chip_select));
  317. writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
  318. mxic->regs + HC_CFG);
  319. ret = mxic_spi_data_xfer(mxic, &opcode, NULL, 1);
  320. if (ret)
  321. goto out;
  322. for (i = 0; i < op->addr.nbytes; i++)
  323. addr[i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
  324. ret = mxic_spi_data_xfer(mxic, addr, NULL, op->addr.nbytes);
  325. if (ret)
  326. goto out;
  327. ret = mxic_spi_data_xfer(mxic, NULL, NULL, op->dummy.nbytes);
  328. if (ret)
  329. goto out;
  330. ret = mxic_spi_data_xfer(mxic,
  331. op->data.dir == SPI_MEM_DATA_OUT ?
  332. op->data.buf.out : NULL,
  333. op->data.dir == SPI_MEM_DATA_IN ?
  334. op->data.buf.in : NULL,
  335. op->data.nbytes);
  336. out:
  337. writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
  338. mxic->regs + HC_CFG);
  339. writel(0, mxic->regs + HC_EN);
  340. return ret;
  341. }
  342. static const struct spi_controller_mem_ops mxic_spi_mem_ops = {
  343. .supports_op = mxic_spi_mem_supports_op,
  344. .exec_op = mxic_spi_mem_exec_op,
  345. };
  346. static void mxic_spi_set_cs(struct spi_device *spi, bool lvl)
  347. {
  348. struct mxic_spi *mxic = spi_master_get_devdata(spi->master);
  349. if (!lvl) {
  350. writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_EN,
  351. mxic->regs + HC_CFG);
  352. writel(HC_EN_BIT, mxic->regs + HC_EN);
  353. writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
  354. mxic->regs + HC_CFG);
  355. } else {
  356. writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
  357. mxic->regs + HC_CFG);
  358. writel(0, mxic->regs + HC_EN);
  359. }
  360. }
  361. static int mxic_spi_transfer_one(struct spi_master *master,
  362. struct spi_device *spi,
  363. struct spi_transfer *t)
  364. {
  365. struct mxic_spi *mxic = spi_master_get_devdata(master);
  366. unsigned int busw = OP_BUSW_1;
  367. int ret;
  368. if (t->rx_buf && t->tx_buf) {
  369. if (((spi->mode & SPI_TX_QUAD) &&
  370. !(spi->mode & SPI_RX_QUAD)) ||
  371. ((spi->mode & SPI_TX_DUAL) &&
  372. !(spi->mode & SPI_RX_DUAL)))
  373. return -ENOTSUPP;
  374. }
  375. ret = mxic_spi_set_freq(mxic, t->speed_hz);
  376. if (ret)
  377. return ret;
  378. if (t->tx_buf) {
  379. if (spi->mode & SPI_TX_QUAD)
  380. busw = OP_BUSW_4;
  381. else if (spi->mode & SPI_TX_DUAL)
  382. busw = OP_BUSW_2;
  383. } else if (t->rx_buf) {
  384. if (spi->mode & SPI_RX_QUAD)
  385. busw = OP_BUSW_4;
  386. else if (spi->mode & SPI_RX_DUAL)
  387. busw = OP_BUSW_2;
  388. }
  389. writel(OP_CMD_BYTES(1) | OP_CMD_BUSW(busw) |
  390. OP_DATA_BUSW(busw) | (t->rx_buf ? OP_READ : 0),
  391. mxic->regs + SS_CTRL(0));
  392. ret = mxic_spi_data_xfer(mxic, t->tx_buf, t->rx_buf, t->len);
  393. if (ret)
  394. return ret;
  395. spi_finalize_current_transfer(master);
  396. return 0;
  397. }
  398. static int __maybe_unused mxic_spi_runtime_suspend(struct device *dev)
  399. {
  400. struct spi_master *master = dev_get_drvdata(dev);
  401. struct mxic_spi *mxic = spi_master_get_devdata(master);
  402. mxic_spi_clk_disable(mxic);
  403. clk_disable_unprepare(mxic->ps_clk);
  404. return 0;
  405. }
  406. static int __maybe_unused mxic_spi_runtime_resume(struct device *dev)
  407. {
  408. struct spi_master *master = dev_get_drvdata(dev);
  409. struct mxic_spi *mxic = spi_master_get_devdata(master);
  410. int ret;
  411. ret = clk_prepare_enable(mxic->ps_clk);
  412. if (ret) {
  413. dev_err(dev, "Cannot enable ps_clock.\n");
  414. return ret;
  415. }
  416. return mxic_spi_clk_enable(mxic);
  417. }
  418. static const struct dev_pm_ops mxic_spi_dev_pm_ops = {
  419. SET_RUNTIME_PM_OPS(mxic_spi_runtime_suspend,
  420. mxic_spi_runtime_resume, NULL)
  421. };
  422. static int mxic_spi_probe(struct platform_device *pdev)
  423. {
  424. struct spi_master *master;
  425. struct resource *res;
  426. struct mxic_spi *mxic;
  427. int ret;
  428. master = devm_spi_alloc_master(&pdev->dev, sizeof(struct mxic_spi));
  429. if (!master)
  430. return -ENOMEM;
  431. platform_set_drvdata(pdev, master);
  432. mxic = spi_master_get_devdata(master);
  433. master->dev.of_node = pdev->dev.of_node;
  434. mxic->ps_clk = devm_clk_get(&pdev->dev, "ps_clk");
  435. if (IS_ERR(mxic->ps_clk))
  436. return PTR_ERR(mxic->ps_clk);
  437. mxic->send_clk = devm_clk_get(&pdev->dev, "send_clk");
  438. if (IS_ERR(mxic->send_clk))
  439. return PTR_ERR(mxic->send_clk);
  440. mxic->send_dly_clk = devm_clk_get(&pdev->dev, "send_dly_clk");
  441. if (IS_ERR(mxic->send_dly_clk))
  442. return PTR_ERR(mxic->send_dly_clk);
  443. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
  444. mxic->regs = devm_ioremap_resource(&pdev->dev, res);
  445. if (IS_ERR(mxic->regs))
  446. return PTR_ERR(mxic->regs);
  447. pm_runtime_enable(&pdev->dev);
  448. master->auto_runtime_pm = true;
  449. master->num_chipselect = 1;
  450. master->mem_ops = &mxic_spi_mem_ops;
  451. master->set_cs = mxic_spi_set_cs;
  452. master->transfer_one = mxic_spi_transfer_one;
  453. master->bits_per_word_mask = SPI_BPW_MASK(8);
  454. master->mode_bits = SPI_CPOL | SPI_CPHA |
  455. SPI_RX_DUAL | SPI_TX_DUAL |
  456. SPI_RX_QUAD | SPI_TX_QUAD;
  457. mxic_spi_hw_init(mxic);
  458. ret = spi_register_master(master);
  459. if (ret) {
  460. dev_err(&pdev->dev, "spi_register_master failed\n");
  461. pm_runtime_disable(&pdev->dev);
  462. }
  463. return ret;
  464. }
  465. static int mxic_spi_remove(struct platform_device *pdev)
  466. {
  467. struct spi_master *master = platform_get_drvdata(pdev);
  468. pm_runtime_disable(&pdev->dev);
  469. spi_unregister_master(master);
  470. return 0;
  471. }
  472. static const struct of_device_id mxic_spi_of_ids[] = {
  473. { .compatible = "mxicy,mx25f0a-spi", },
  474. { /* sentinel */ }
  475. };
  476. MODULE_DEVICE_TABLE(of, mxic_spi_of_ids);
  477. static struct platform_driver mxic_spi_driver = {
  478. .probe = mxic_spi_probe,
  479. .remove = mxic_spi_remove,
  480. .driver = {
  481. .name = "mxic-spi",
  482. .of_match_table = mxic_spi_of_ids,
  483. .pm = &mxic_spi_dev_pm_ops,
  484. },
  485. };
  486. module_platform_driver(mxic_spi_driver);
  487. MODULE_AUTHOR("Mason Yang <masonccyang@mxic.com.tw>");
  488. MODULE_DESCRIPTION("MX25F0A SPI controller driver");
  489. MODULE_LICENSE("GPL v2");