spi-mt7621.c 9.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // spi-mt7621.c -- MediaTek MT7621 SPI controller driver
  4. //
  5. // Copyright (C) 2011 Sergiy <piratfm@gmail.com>
  6. // Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  7. // Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
  8. //
  9. // Some parts are based on spi-orion.c:
  10. // Author: Shadi Ammouri <shadi@marvell.com>
  11. // Copyright (C) 2007-2008 Marvell Ltd.
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/io.h>
  15. #include <linux/module.h>
  16. #include <linux/of_device.h>
  17. #include <linux/reset.h>
  18. #include <linux/spi/spi.h>
  19. #define DRIVER_NAME "spi-mt7621"
  20. /* in usec */
  21. #define RALINK_SPI_WAIT_MAX_LOOP 2000
  22. /* SPISTAT register bit field */
  23. #define SPISTAT_BUSY BIT(0)
  24. #define MT7621_SPI_TRANS 0x00
  25. #define SPITRANS_BUSY BIT(16)
  26. #define MT7621_SPI_OPCODE 0x04
  27. #define MT7621_SPI_DATA0 0x08
  28. #define MT7621_SPI_DATA4 0x18
  29. #define SPI_CTL_TX_RX_CNT_MASK 0xff
  30. #define SPI_CTL_START BIT(8)
  31. #define MT7621_SPI_MASTER 0x28
  32. #define MASTER_MORE_BUFMODE BIT(2)
  33. #define MASTER_FULL_DUPLEX BIT(10)
  34. #define MASTER_RS_CLK_SEL GENMASK(27, 16)
  35. #define MASTER_RS_CLK_SEL_SHIFT 16
  36. #define MASTER_RS_SLAVE_SEL GENMASK(31, 29)
  37. #define MT7621_SPI_MOREBUF 0x2c
  38. #define MT7621_SPI_POLAR 0x38
  39. #define MT7621_SPI_SPACE 0x3c
  40. #define MT7621_CPHA BIT(5)
  41. #define MT7621_CPOL BIT(4)
  42. #define MT7621_LSB_FIRST BIT(3)
  43. struct mt7621_spi {
  44. struct spi_controller *master;
  45. void __iomem *base;
  46. unsigned int sys_freq;
  47. unsigned int speed;
  48. struct clk *clk;
  49. int pending_write;
  50. };
  51. static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
  52. {
  53. return spi_controller_get_devdata(spi->master);
  54. }
  55. static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
  56. {
  57. return ioread32(rs->base + reg);
  58. }
  59. static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
  60. {
  61. iowrite32(val, rs->base + reg);
  62. }
  63. static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
  64. {
  65. struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
  66. int cs = spi->chip_select;
  67. u32 polar = 0;
  68. u32 master;
  69. /*
  70. * Select SPI device 7, enable "more buffer mode" and disable
  71. * full-duplex (only half-duplex really works on this chip
  72. * reliably)
  73. */
  74. master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
  75. master |= MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE;
  76. master &= ~MASTER_FULL_DUPLEX;
  77. mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
  78. rs->pending_write = 0;
  79. if (enable)
  80. polar = BIT(cs);
  81. mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
  82. }
  83. static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
  84. {
  85. struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
  86. u32 rate;
  87. u32 reg;
  88. dev_dbg(&spi->dev, "speed:%u\n", speed);
  89. rate = DIV_ROUND_UP(rs->sys_freq, speed);
  90. dev_dbg(&spi->dev, "rate-1:%u\n", rate);
  91. if (rate > 4097)
  92. return -EINVAL;
  93. if (rate < 2)
  94. rate = 2;
  95. reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
  96. reg &= ~MASTER_RS_CLK_SEL;
  97. reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
  98. rs->speed = speed;
  99. reg &= ~MT7621_LSB_FIRST;
  100. if (spi->mode & SPI_LSB_FIRST)
  101. reg |= MT7621_LSB_FIRST;
  102. /*
  103. * This SPI controller seems to be tested on SPI flash only and some
  104. * bits are swizzled under other SPI modes probably due to incorrect
  105. * wiring inside the silicon. Only mode 0 works correctly.
  106. */
  107. reg &= ~(MT7621_CPHA | MT7621_CPOL);
  108. mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
  109. return 0;
  110. }
  111. static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
  112. {
  113. int i;
  114. for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
  115. u32 status;
  116. status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
  117. if ((status & SPITRANS_BUSY) == 0)
  118. return 0;
  119. cpu_relax();
  120. udelay(1);
  121. }
  122. return -ETIMEDOUT;
  123. }
  124. static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs,
  125. int rx_len, u8 *buf)
  126. {
  127. int tx_len;
  128. /*
  129. * Combine with any pending write, and perform one or more half-duplex
  130. * transactions reading 'len' bytes. Data to be written is already in
  131. * MT7621_SPI_DATA.
  132. */
  133. tx_len = rs->pending_write;
  134. rs->pending_write = 0;
  135. while (rx_len || tx_len) {
  136. int i;
  137. u32 val = (min(tx_len, 4) * 8) << 24;
  138. int rx = min(rx_len, 32);
  139. if (tx_len > 4)
  140. val |= (tx_len - 4) * 8;
  141. val |= (rx * 8) << 12;
  142. mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
  143. tx_len = 0;
  144. val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
  145. val |= SPI_CTL_START;
  146. mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
  147. mt7621_spi_wait_till_ready(rs);
  148. for (i = 0; i < rx; i++) {
  149. if ((i % 4) == 0)
  150. val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
  151. *buf++ = val & 0xff;
  152. val >>= 8;
  153. }
  154. rx_len -= i;
  155. }
  156. }
  157. static inline void mt7621_spi_flush(struct mt7621_spi *rs)
  158. {
  159. mt7621_spi_read_half_duplex(rs, 0, NULL);
  160. }
  161. static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs,
  162. int tx_len, const u8 *buf)
  163. {
  164. int len = rs->pending_write;
  165. int val = 0;
  166. if (len & 3) {
  167. val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3));
  168. if (len < 4) {
  169. val <<= (4 - len) * 8;
  170. val = swab32(val);
  171. }
  172. }
  173. while (tx_len > 0) {
  174. if (len >= 36) {
  175. rs->pending_write = len;
  176. mt7621_spi_flush(rs);
  177. len = 0;
  178. }
  179. val |= *buf++ << (8 * (len & 3));
  180. len++;
  181. if ((len & 3) == 0) {
  182. if (len == 4)
  183. /* The byte-order of the opcode is weird! */
  184. val = swab32(val);
  185. mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val);
  186. val = 0;
  187. }
  188. tx_len -= 1;
  189. }
  190. if (len & 3) {
  191. if (len < 4) {
  192. val = swab32(val);
  193. val >>= (4 - len) * 8;
  194. }
  195. mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val);
  196. }
  197. rs->pending_write = len;
  198. }
  199. static int mt7621_spi_transfer_one_message(struct spi_controller *master,
  200. struct spi_message *m)
  201. {
  202. struct mt7621_spi *rs = spi_controller_get_devdata(master);
  203. struct spi_device *spi = m->spi;
  204. unsigned int speed = spi->max_speed_hz;
  205. struct spi_transfer *t = NULL;
  206. int status = 0;
  207. mt7621_spi_wait_till_ready(rs);
  208. list_for_each_entry(t, &m->transfers, transfer_list)
  209. if (t->speed_hz < speed)
  210. speed = t->speed_hz;
  211. if (mt7621_spi_prepare(spi, speed)) {
  212. status = -EIO;
  213. goto msg_done;
  214. }
  215. /* Assert CS */
  216. mt7621_spi_set_cs(spi, 1);
  217. m->actual_length = 0;
  218. list_for_each_entry(t, &m->transfers, transfer_list) {
  219. if ((t->rx_buf) && (t->tx_buf)) {
  220. /*
  221. * This controller will shift some extra data out
  222. * of spi_opcode if (mosi_bit_cnt > 0) &&
  223. * (cmd_bit_cnt == 0). So the claimed full-duplex
  224. * support is broken since we have no way to read
  225. * the MISO value during that bit.
  226. */
  227. status = -EIO;
  228. goto msg_done;
  229. } else if (t->rx_buf) {
  230. mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf);
  231. } else if (t->tx_buf) {
  232. mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf);
  233. }
  234. m->actual_length += t->len;
  235. }
  236. /* Flush data and deassert CS */
  237. mt7621_spi_flush(rs);
  238. mt7621_spi_set_cs(spi, 0);
  239. msg_done:
  240. m->status = status;
  241. spi_finalize_current_message(master);
  242. return 0;
  243. }
  244. static int mt7621_spi_setup(struct spi_device *spi)
  245. {
  246. struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
  247. if ((spi->max_speed_hz == 0) ||
  248. (spi->max_speed_hz > (rs->sys_freq / 2)))
  249. spi->max_speed_hz = rs->sys_freq / 2;
  250. if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
  251. dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
  252. spi->max_speed_hz);
  253. return -EINVAL;
  254. }
  255. return 0;
  256. }
  257. static const struct of_device_id mt7621_spi_match[] = {
  258. { .compatible = "ralink,mt7621-spi" },
  259. {},
  260. };
  261. MODULE_DEVICE_TABLE(of, mt7621_spi_match);
  262. static int mt7621_spi_probe(struct platform_device *pdev)
  263. {
  264. const struct of_device_id *match;
  265. struct spi_controller *master;
  266. struct mt7621_spi *rs;
  267. void __iomem *base;
  268. int status = 0;
  269. struct clk *clk;
  270. int ret;
  271. match = of_match_device(mt7621_spi_match, &pdev->dev);
  272. if (!match)
  273. return -EINVAL;
  274. base = devm_platform_ioremap_resource(pdev, 0);
  275. if (IS_ERR(base))
  276. return PTR_ERR(base);
  277. clk = devm_clk_get(&pdev->dev, NULL);
  278. if (IS_ERR(clk)) {
  279. dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
  280. status);
  281. return PTR_ERR(clk);
  282. }
  283. status = clk_prepare_enable(clk);
  284. if (status)
  285. return status;
  286. master = devm_spi_alloc_master(&pdev->dev, sizeof(*rs));
  287. if (!master) {
  288. dev_info(&pdev->dev, "master allocation failed\n");
  289. clk_disable_unprepare(clk);
  290. return -ENOMEM;
  291. }
  292. master->mode_bits = SPI_LSB_FIRST;
  293. master->flags = SPI_CONTROLLER_HALF_DUPLEX;
  294. master->setup = mt7621_spi_setup;
  295. master->transfer_one_message = mt7621_spi_transfer_one_message;
  296. master->bits_per_word_mask = SPI_BPW_MASK(8);
  297. master->dev.of_node = pdev->dev.of_node;
  298. master->num_chipselect = 2;
  299. dev_set_drvdata(&pdev->dev, master);
  300. rs = spi_controller_get_devdata(master);
  301. rs->base = base;
  302. rs->clk = clk;
  303. rs->master = master;
  304. rs->sys_freq = clk_get_rate(rs->clk);
  305. rs->pending_write = 0;
  306. dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
  307. ret = device_reset(&pdev->dev);
  308. if (ret) {
  309. dev_err(&pdev->dev, "SPI reset failed!\n");
  310. clk_disable_unprepare(clk);
  311. return ret;
  312. }
  313. ret = spi_register_controller(master);
  314. if (ret)
  315. clk_disable_unprepare(clk);
  316. return ret;
  317. }
  318. static int mt7621_spi_remove(struct platform_device *pdev)
  319. {
  320. struct spi_controller *master;
  321. struct mt7621_spi *rs;
  322. master = dev_get_drvdata(&pdev->dev);
  323. rs = spi_controller_get_devdata(master);
  324. spi_unregister_controller(master);
  325. clk_disable_unprepare(rs->clk);
  326. return 0;
  327. }
  328. MODULE_ALIAS("platform:" DRIVER_NAME);
  329. static struct platform_driver mt7621_spi_driver = {
  330. .driver = {
  331. .name = DRIVER_NAME,
  332. .of_match_table = mt7621_spi_match,
  333. },
  334. .probe = mt7621_spi_probe,
  335. .remove = mt7621_spi_remove,
  336. };
  337. module_platform_driver(mt7621_spi_driver);
  338. MODULE_DESCRIPTION("MT7621 SPI driver");
  339. MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
  340. MODULE_LICENSE("GPL");