spi-mpc52xx-psc.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * MPC52xx PSC in SPI mode driver.
  4. *
  5. * Maintainer: Dragos Carp
  6. *
  7. * Copyright (C) 2006 TOPTICA Photonics AG.
  8. */
  9. #include <linux/module.h>
  10. #include <linux/types.h>
  11. #include <linux/errno.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/of_address.h>
  14. #include <linux/of_platform.h>
  15. #include <linux/workqueue.h>
  16. #include <linux/completion.h>
  17. #include <linux/io.h>
  18. #include <linux/delay.h>
  19. #include <linux/spi/spi.h>
  20. #include <linux/fsl_devices.h>
  21. #include <linux/slab.h>
  22. #include <asm/mpc52xx.h>
  23. #include <asm/mpc52xx_psc.h>
  24. #define MCLK 20000000 /* PSC port MClk in hz */
  25. struct mpc52xx_psc_spi {
  26. /* fsl_spi_platform data */
  27. void (*cs_control)(struct spi_device *spi, bool on);
  28. u32 sysclk;
  29. /* driver internal data */
  30. struct mpc52xx_psc __iomem *psc;
  31. struct mpc52xx_psc_fifo __iomem *fifo;
  32. unsigned int irq;
  33. u8 bits_per_word;
  34. u8 busy;
  35. struct work_struct work;
  36. struct list_head queue;
  37. spinlock_t lock;
  38. struct completion done;
  39. };
  40. /* controller state */
  41. struct mpc52xx_psc_spi_cs {
  42. int bits_per_word;
  43. int speed_hz;
  44. };
  45. /* set clock freq, clock ramp, bits per work
  46. * if t is NULL then reset the values to the default values
  47. */
  48. static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi,
  49. struct spi_transfer *t)
  50. {
  51. struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
  52. cs->speed_hz = (t && t->speed_hz)
  53. ? t->speed_hz : spi->max_speed_hz;
  54. cs->bits_per_word = (t && t->bits_per_word)
  55. ? t->bits_per_word : spi->bits_per_word;
  56. cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
  57. return 0;
  58. }
  59. static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
  60. {
  61. struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
  62. struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
  63. struct mpc52xx_psc __iomem *psc = mps->psc;
  64. u32 sicr;
  65. u16 ccr;
  66. sicr = in_be32(&psc->sicr);
  67. /* Set clock phase and polarity */
  68. if (spi->mode & SPI_CPHA)
  69. sicr |= 0x00001000;
  70. else
  71. sicr &= ~0x00001000;
  72. if (spi->mode & SPI_CPOL)
  73. sicr |= 0x00002000;
  74. else
  75. sicr &= ~0x00002000;
  76. if (spi->mode & SPI_LSB_FIRST)
  77. sicr |= 0x10000000;
  78. else
  79. sicr &= ~0x10000000;
  80. out_be32(&psc->sicr, sicr);
  81. /* Set clock frequency and bits per word
  82. * Because psc->ccr is defined as 16bit register instead of 32bit
  83. * just set the lower byte of BitClkDiv
  84. */
  85. ccr = in_be16((u16 __iomem *)&psc->ccr);
  86. ccr &= 0xFF00;
  87. if (cs->speed_hz)
  88. ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
  89. else /* by default SPI Clk 1MHz */
  90. ccr |= (MCLK / 1000000 - 1) & 0xFF;
  91. out_be16((u16 __iomem *)&psc->ccr, ccr);
  92. mps->bits_per_word = cs->bits_per_word;
  93. if (mps->cs_control)
  94. mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
  95. }
  96. static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi)
  97. {
  98. struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
  99. if (mps->cs_control)
  100. mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
  101. }
  102. #define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1)
  103. /* wake up when 80% fifo full */
  104. #define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100)
  105. static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
  106. struct spi_transfer *t)
  107. {
  108. struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
  109. struct mpc52xx_psc __iomem *psc = mps->psc;
  110. struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
  111. unsigned rb = 0; /* number of bytes receieved */
  112. unsigned sb = 0; /* number of bytes sent */
  113. unsigned char *rx_buf = (unsigned char *)t->rx_buf;
  114. unsigned char *tx_buf = (unsigned char *)t->tx_buf;
  115. unsigned rfalarm;
  116. unsigned send_at_once = MPC52xx_PSC_BUFSIZE;
  117. unsigned recv_at_once;
  118. int last_block = 0;
  119. if (!t->tx_buf && !t->rx_buf && t->len)
  120. return -EINVAL;
  121. /* enable transmiter/receiver */
  122. out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
  123. while (rb < t->len) {
  124. if (t->len - rb > MPC52xx_PSC_BUFSIZE) {
  125. rfalarm = MPC52xx_PSC_RFALARM;
  126. last_block = 0;
  127. } else {
  128. send_at_once = t->len - sb;
  129. rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb);
  130. last_block = 1;
  131. }
  132. dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once);
  133. for (; send_at_once; sb++, send_at_once--) {
  134. /* set EOF flag before the last word is sent */
  135. if (send_at_once == 1 && last_block)
  136. out_8(&psc->ircr2, 0x01);
  137. if (tx_buf)
  138. out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);
  139. else
  140. out_8(&psc->mpc52xx_psc_buffer_8, 0);
  141. }
  142. /* enable interrupts and wait for wake up
  143. * if just one byte is expected the Rx FIFO genererates no
  144. * FFULL interrupt, so activate the RxRDY interrupt
  145. */
  146. out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
  147. if (t->len - rb == 1) {
  148. out_8(&psc->mode, 0);
  149. } else {
  150. out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
  151. out_be16(&fifo->rfalarm, rfalarm);
  152. }
  153. out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);
  154. wait_for_completion(&mps->done);
  155. recv_at_once = in_be16(&fifo->rfnum);
  156. dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once);
  157. send_at_once = recv_at_once;
  158. if (rx_buf) {
  159. for (; recv_at_once; rb++, recv_at_once--)
  160. rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);
  161. } else {
  162. for (; recv_at_once; rb++, recv_at_once--)
  163. in_8(&psc->mpc52xx_psc_buffer_8);
  164. }
  165. }
  166. /* disable transmiter/receiver */
  167. out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
  168. return 0;
  169. }
  170. static void mpc52xx_psc_spi_work(struct work_struct *work)
  171. {
  172. struct mpc52xx_psc_spi *mps =
  173. container_of(work, struct mpc52xx_psc_spi, work);
  174. spin_lock_irq(&mps->lock);
  175. mps->busy = 1;
  176. while (!list_empty(&mps->queue)) {
  177. struct spi_message *m;
  178. struct spi_device *spi;
  179. struct spi_transfer *t = NULL;
  180. unsigned cs_change;
  181. int status;
  182. m = container_of(mps->queue.next, struct spi_message, queue);
  183. list_del_init(&m->queue);
  184. spin_unlock_irq(&mps->lock);
  185. spi = m->spi;
  186. cs_change = 1;
  187. status = 0;
  188. list_for_each_entry (t, &m->transfers, transfer_list) {
  189. if (t->bits_per_word || t->speed_hz) {
  190. status = mpc52xx_psc_spi_transfer_setup(spi, t);
  191. if (status < 0)
  192. break;
  193. }
  194. if (cs_change)
  195. mpc52xx_psc_spi_activate_cs(spi);
  196. cs_change = t->cs_change;
  197. status = mpc52xx_psc_spi_transfer_rxtx(spi, t);
  198. if (status)
  199. break;
  200. m->actual_length += t->len;
  201. spi_transfer_delay_exec(t);
  202. if (cs_change)
  203. mpc52xx_psc_spi_deactivate_cs(spi);
  204. }
  205. m->status = status;
  206. if (m->complete)
  207. m->complete(m->context);
  208. if (status || !cs_change)
  209. mpc52xx_psc_spi_deactivate_cs(spi);
  210. mpc52xx_psc_spi_transfer_setup(spi, NULL);
  211. spin_lock_irq(&mps->lock);
  212. }
  213. mps->busy = 0;
  214. spin_unlock_irq(&mps->lock);
  215. }
  216. static int mpc52xx_psc_spi_setup(struct spi_device *spi)
  217. {
  218. struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
  219. struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
  220. unsigned long flags;
  221. if (spi->bits_per_word%8)
  222. return -EINVAL;
  223. if (!cs) {
  224. cs = kzalloc(sizeof *cs, GFP_KERNEL);
  225. if (!cs)
  226. return -ENOMEM;
  227. spi->controller_state = cs;
  228. }
  229. cs->bits_per_word = spi->bits_per_word;
  230. cs->speed_hz = spi->max_speed_hz;
  231. spin_lock_irqsave(&mps->lock, flags);
  232. if (!mps->busy)
  233. mpc52xx_psc_spi_deactivate_cs(spi);
  234. spin_unlock_irqrestore(&mps->lock, flags);
  235. return 0;
  236. }
  237. static int mpc52xx_psc_spi_transfer(struct spi_device *spi,
  238. struct spi_message *m)
  239. {
  240. struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
  241. unsigned long flags;
  242. m->actual_length = 0;
  243. m->status = -EINPROGRESS;
  244. spin_lock_irqsave(&mps->lock, flags);
  245. list_add_tail(&m->queue, &mps->queue);
  246. schedule_work(&mps->work);
  247. spin_unlock_irqrestore(&mps->lock, flags);
  248. return 0;
  249. }
  250. static void mpc52xx_psc_spi_cleanup(struct spi_device *spi)
  251. {
  252. kfree(spi->controller_state);
  253. }
  254. static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
  255. {
  256. struct mpc52xx_psc __iomem *psc = mps->psc;
  257. struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
  258. u32 mclken_div;
  259. int ret;
  260. /* default sysclk is 512MHz */
  261. mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK;
  262. ret = mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
  263. if (ret)
  264. return ret;
  265. /* Reset the PSC into a known state */
  266. out_8(&psc->command, MPC52xx_PSC_RST_RX);
  267. out_8(&psc->command, MPC52xx_PSC_RST_TX);
  268. out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
  269. /* Disable interrupts, interrupts are based on alarm level */
  270. out_be16(&psc->mpc52xx_psc_imr, 0);
  271. out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
  272. out_8(&fifo->rfcntl, 0);
  273. out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
  274. /* Configure 8bit codec mode as a SPI master and use EOF flags */
  275. /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
  276. out_be32(&psc->sicr, 0x0180C800);
  277. out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
  278. /* Set 2ms DTL delay */
  279. out_8(&psc->ctur, 0x00);
  280. out_8(&psc->ctlr, 0x84);
  281. mps->bits_per_word = 8;
  282. return 0;
  283. }
  284. static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
  285. {
  286. struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id;
  287. struct mpc52xx_psc __iomem *psc = mps->psc;
  288. /* disable interrupt and wake up the work queue */
  289. if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {
  290. out_be16(&psc->mpc52xx_psc_imr, 0);
  291. complete(&mps->done);
  292. return IRQ_HANDLED;
  293. }
  294. return IRQ_NONE;
  295. }
  296. /* bus_num is used only for the case dev->platform_data == NULL */
  297. static int mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr,
  298. u32 size, unsigned int irq, s16 bus_num)
  299. {
  300. struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
  301. struct mpc52xx_psc_spi *mps;
  302. struct spi_master *master;
  303. int ret;
  304. master = spi_alloc_master(dev, sizeof *mps);
  305. if (master == NULL)
  306. return -ENOMEM;
  307. dev_set_drvdata(dev, master);
  308. mps = spi_master_get_devdata(master);
  309. /* the spi->mode bits understood by this driver: */
  310. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
  311. mps->irq = irq;
  312. if (pdata == NULL) {
  313. dev_warn(dev,
  314. "probe called without platform data, no cs_control function will be called\n");
  315. mps->cs_control = NULL;
  316. mps->sysclk = 0;
  317. master->bus_num = bus_num;
  318. master->num_chipselect = 255;
  319. } else {
  320. mps->cs_control = pdata->cs_control;
  321. mps->sysclk = pdata->sysclk;
  322. master->bus_num = pdata->bus_num;
  323. master->num_chipselect = pdata->max_chipselect;
  324. }
  325. master->setup = mpc52xx_psc_spi_setup;
  326. master->transfer = mpc52xx_psc_spi_transfer;
  327. master->cleanup = mpc52xx_psc_spi_cleanup;
  328. master->dev.of_node = dev->of_node;
  329. mps->psc = ioremap(regaddr, size);
  330. if (!mps->psc) {
  331. dev_err(dev, "could not ioremap I/O port range\n");
  332. ret = -EFAULT;
  333. goto free_master;
  334. }
  335. /* On the 5200, fifo regs are immediately ajacent to the psc regs */
  336. mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);
  337. ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi",
  338. mps);
  339. if (ret)
  340. goto free_master;
  341. ret = mpc52xx_psc_spi_port_config(master->bus_num, mps);
  342. if (ret < 0) {
  343. dev_err(dev, "can't configure PSC! Is it capable of SPI?\n");
  344. goto free_irq;
  345. }
  346. spin_lock_init(&mps->lock);
  347. init_completion(&mps->done);
  348. INIT_WORK(&mps->work, mpc52xx_psc_spi_work);
  349. INIT_LIST_HEAD(&mps->queue);
  350. ret = spi_register_master(master);
  351. if (ret < 0)
  352. goto free_irq;
  353. return ret;
  354. free_irq:
  355. free_irq(mps->irq, mps);
  356. free_master:
  357. if (mps->psc)
  358. iounmap(mps->psc);
  359. spi_master_put(master);
  360. return ret;
  361. }
  362. static int mpc52xx_psc_spi_of_probe(struct platform_device *op)
  363. {
  364. const u32 *regaddr_p;
  365. u64 regaddr64, size64;
  366. s16 id = -1;
  367. regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
  368. if (!regaddr_p) {
  369. dev_err(&op->dev, "Invalid PSC address\n");
  370. return -EINVAL;
  371. }
  372. regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
  373. /* get PSC id (1..6, used by port_config) */
  374. if (op->dev.platform_data == NULL) {
  375. const u32 *psc_nump;
  376. psc_nump = of_get_property(op->dev.of_node, "cell-index", NULL);
  377. if (!psc_nump || *psc_nump > 5) {
  378. dev_err(&op->dev, "Invalid cell-index property\n");
  379. return -EINVAL;
  380. }
  381. id = *psc_nump + 1;
  382. }
  383. return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64,
  384. irq_of_parse_and_map(op->dev.of_node, 0), id);
  385. }
  386. static int mpc52xx_psc_spi_of_remove(struct platform_device *op)
  387. {
  388. struct spi_master *master = spi_master_get(platform_get_drvdata(op));
  389. struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master);
  390. flush_work(&mps->work);
  391. spi_unregister_master(master);
  392. free_irq(mps->irq, mps);
  393. if (mps->psc)
  394. iounmap(mps->psc);
  395. spi_master_put(master);
  396. return 0;
  397. }
  398. static const struct of_device_id mpc52xx_psc_spi_of_match[] = {
  399. { .compatible = "fsl,mpc5200-psc-spi", },
  400. { .compatible = "mpc5200-psc-spi", }, /* old */
  401. {}
  402. };
  403. MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match);
  404. static struct platform_driver mpc52xx_psc_spi_of_driver = {
  405. .probe = mpc52xx_psc_spi_of_probe,
  406. .remove = mpc52xx_psc_spi_of_remove,
  407. .driver = {
  408. .name = "mpc52xx-psc-spi",
  409. .of_match_table = mpc52xx_psc_spi_of_match,
  410. },
  411. };
  412. module_platform_driver(mpc52xx_psc_spi_of_driver);
  413. MODULE_AUTHOR("Dragos Carp");
  414. MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");
  415. MODULE_LICENSE("GPL");