spi-mpc512x-psc.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * MPC512x PSC in SPI mode driver.
  4. *
  5. * Copyright (C) 2007,2008 Freescale Semiconductor Inc.
  6. * Original port from 52xx driver:
  7. * Hongjun Chen <hong-jun.chen@freescale.com>
  8. *
  9. * Fork of mpc52xx_psc_spi.c:
  10. * Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/errno.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/of_address.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/of_platform.h>
  19. #include <linux/completion.h>
  20. #include <linux/io.h>
  21. #include <linux/delay.h>
  22. #include <linux/clk.h>
  23. #include <linux/spi/spi.h>
  24. #include <linux/fsl_devices.h>
  25. #include <linux/gpio.h>
  26. #include <asm/mpc52xx_psc.h>
  27. enum {
  28. TYPE_MPC5121,
  29. TYPE_MPC5125,
  30. };
  31. /*
  32. * This macro abstracts the differences in the PSC register layout between
  33. * MPC5121 (which uses a struct mpc52xx_psc) and MPC5125 (using mpc5125_psc).
  34. */
  35. #define psc_addr(mps, regname) ({ \
  36. void *__ret = NULL; \
  37. switch (mps->type) { \
  38. case TYPE_MPC5121: { \
  39. struct mpc52xx_psc __iomem *psc = mps->psc; \
  40. __ret = &psc->regname; \
  41. }; \
  42. break; \
  43. case TYPE_MPC5125: { \
  44. struct mpc5125_psc __iomem *psc = mps->psc; \
  45. __ret = &psc->regname; \
  46. }; \
  47. break; \
  48. } \
  49. __ret; })
  50. struct mpc512x_psc_spi {
  51. void (*cs_control)(struct spi_device *spi, bool on);
  52. /* driver internal data */
  53. int type;
  54. void __iomem *psc;
  55. struct mpc512x_psc_fifo __iomem *fifo;
  56. unsigned int irq;
  57. u8 bits_per_word;
  58. struct clk *clk_mclk;
  59. struct clk *clk_ipg;
  60. u32 mclk_rate;
  61. struct completion txisrdone;
  62. };
  63. /* controller state */
  64. struct mpc512x_psc_spi_cs {
  65. int bits_per_word;
  66. int speed_hz;
  67. };
  68. /* set clock freq, clock ramp, bits per work
  69. * if t is NULL then reset the values to the default values
  70. */
  71. static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi,
  72. struct spi_transfer *t)
  73. {
  74. struct mpc512x_psc_spi_cs *cs = spi->controller_state;
  75. cs->speed_hz = (t && t->speed_hz)
  76. ? t->speed_hz : spi->max_speed_hz;
  77. cs->bits_per_word = (t && t->bits_per_word)
  78. ? t->bits_per_word : spi->bits_per_word;
  79. cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
  80. return 0;
  81. }
  82. static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
  83. {
  84. struct mpc512x_psc_spi_cs *cs = spi->controller_state;
  85. struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
  86. u32 sicr;
  87. u32 ccr;
  88. int speed;
  89. u16 bclkdiv;
  90. sicr = in_be32(psc_addr(mps, sicr));
  91. /* Set clock phase and polarity */
  92. if (spi->mode & SPI_CPHA)
  93. sicr |= 0x00001000;
  94. else
  95. sicr &= ~0x00001000;
  96. if (spi->mode & SPI_CPOL)
  97. sicr |= 0x00002000;
  98. else
  99. sicr &= ~0x00002000;
  100. if (spi->mode & SPI_LSB_FIRST)
  101. sicr |= 0x10000000;
  102. else
  103. sicr &= ~0x10000000;
  104. out_be32(psc_addr(mps, sicr), sicr);
  105. ccr = in_be32(psc_addr(mps, ccr));
  106. ccr &= 0xFF000000;
  107. speed = cs->speed_hz;
  108. if (!speed)
  109. speed = 1000000; /* default 1MHz */
  110. bclkdiv = (mps->mclk_rate / speed) - 1;
  111. ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
  112. out_be32(psc_addr(mps, ccr), ccr);
  113. mps->bits_per_word = cs->bits_per_word;
  114. if (mps->cs_control && gpio_is_valid(spi->cs_gpio))
  115. mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
  116. }
  117. static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi)
  118. {
  119. struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
  120. if (mps->cs_control && gpio_is_valid(spi->cs_gpio))
  121. mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
  122. }
  123. /* extract and scale size field in txsz or rxsz */
  124. #define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2);
  125. #define EOFBYTE 1
  126. static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi,
  127. struct spi_transfer *t)
  128. {
  129. struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
  130. struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
  131. size_t tx_len = t->len;
  132. size_t rx_len = t->len;
  133. u8 *tx_buf = (u8 *)t->tx_buf;
  134. u8 *rx_buf = (u8 *)t->rx_buf;
  135. if (!tx_buf && !rx_buf && t->len)
  136. return -EINVAL;
  137. while (rx_len || tx_len) {
  138. size_t txcount;
  139. u8 data;
  140. size_t fifosz;
  141. size_t rxcount;
  142. int rxtries;
  143. /*
  144. * send the TX bytes in as large a chunk as possible
  145. * but neither exceed the TX nor the RX FIFOs
  146. */
  147. fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz));
  148. txcount = min(fifosz, tx_len);
  149. fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz));
  150. fifosz -= in_be32(&fifo->rxcnt) + 1;
  151. txcount = min(fifosz, txcount);
  152. if (txcount) {
  153. /* fill the TX FIFO */
  154. while (txcount-- > 0) {
  155. data = tx_buf ? *tx_buf++ : 0;
  156. if (tx_len == EOFBYTE && t->cs_change)
  157. setbits32(&fifo->txcmd,
  158. MPC512x_PSC_FIFO_EOF);
  159. out_8(&fifo->txdata_8, data);
  160. tx_len--;
  161. }
  162. /* have the ISR trigger when the TX FIFO is empty */
  163. reinit_completion(&mps->txisrdone);
  164. out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
  165. out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY);
  166. wait_for_completion(&mps->txisrdone);
  167. }
  168. /*
  169. * consume as much RX data as the FIFO holds, while we
  170. * iterate over the transfer's TX data length
  171. *
  172. * only insist in draining all the remaining RX bytes
  173. * when the TX bytes were exhausted (that's at the very
  174. * end of this transfer, not when still iterating over
  175. * the transfer's chunks)
  176. */
  177. rxtries = 50;
  178. do {
  179. /*
  180. * grab whatever was in the FIFO when we started
  181. * looking, don't bother fetching what was added to
  182. * the FIFO while we read from it -- we'll return
  183. * here eventually and prefer sending out remaining
  184. * TX data
  185. */
  186. fifosz = in_be32(&fifo->rxcnt);
  187. rxcount = min(fifosz, rx_len);
  188. while (rxcount-- > 0) {
  189. data = in_8(&fifo->rxdata_8);
  190. if (rx_buf)
  191. *rx_buf++ = data;
  192. rx_len--;
  193. }
  194. /*
  195. * come back later if there still is TX data to send,
  196. * bail out of the RX drain loop if all of the TX data
  197. * was sent and all of the RX data was received (i.e.
  198. * when the transmission has completed)
  199. */
  200. if (tx_len)
  201. break;
  202. if (!rx_len)
  203. break;
  204. /*
  205. * TX data transmission has completed while RX data
  206. * is still pending -- that's a transient situation
  207. * which depends on wire speed and specific
  208. * hardware implementation details (buffering) yet
  209. * should resolve very quickly
  210. *
  211. * just yield for a moment to not hog the CPU for
  212. * too long when running SPI at low speed
  213. *
  214. * the timeout range is rather arbitrary and tries
  215. * to balance throughput against system load; the
  216. * chosen values result in a minimal timeout of 50
  217. * times 10us and thus work at speeds as low as
  218. * some 20kbps, while the maximum timeout at the
  219. * transfer's end could be 5ms _if_ nothing else
  220. * ticks in the system _and_ RX data still wasn't
  221. * received, which only occurs in situations that
  222. * are exceptional; removing the unpredictability
  223. * of the timeout either decreases throughput
  224. * (longer timeouts), or puts more load on the
  225. * system (fixed short timeouts) or requires the
  226. * use of a timeout API instead of a counter and an
  227. * unknown inner delay
  228. */
  229. usleep_range(10, 100);
  230. } while (--rxtries > 0);
  231. if (!tx_len && rx_len && !rxtries) {
  232. /*
  233. * not enough RX bytes even after several retries
  234. * and the resulting rather long timeout?
  235. */
  236. rxcount = in_be32(&fifo->rxcnt);
  237. dev_warn(&spi->dev,
  238. "short xfer, missing %zd RX bytes, FIFO level %zd\n",
  239. rx_len, rxcount);
  240. }
  241. /*
  242. * drain and drop RX data which "should not be there" in
  243. * the first place, for undisturbed transmission this turns
  244. * into a NOP (except for the FIFO level fetch)
  245. */
  246. if (!tx_len && !rx_len) {
  247. while (in_be32(&fifo->rxcnt))
  248. in_8(&fifo->rxdata_8);
  249. }
  250. }
  251. return 0;
  252. }
  253. static int mpc512x_psc_spi_msg_xfer(struct spi_master *master,
  254. struct spi_message *m)
  255. {
  256. struct spi_device *spi;
  257. unsigned cs_change;
  258. int status;
  259. struct spi_transfer *t;
  260. spi = m->spi;
  261. cs_change = 1;
  262. status = 0;
  263. list_for_each_entry(t, &m->transfers, transfer_list) {
  264. status = mpc512x_psc_spi_transfer_setup(spi, t);
  265. if (status < 0)
  266. break;
  267. if (cs_change)
  268. mpc512x_psc_spi_activate_cs(spi);
  269. cs_change = t->cs_change;
  270. status = mpc512x_psc_spi_transfer_rxtx(spi, t);
  271. if (status)
  272. break;
  273. m->actual_length += t->len;
  274. spi_transfer_delay_exec(t);
  275. if (cs_change)
  276. mpc512x_psc_spi_deactivate_cs(spi);
  277. }
  278. m->status = status;
  279. if (m->complete)
  280. m->complete(m->context);
  281. if (status || !cs_change)
  282. mpc512x_psc_spi_deactivate_cs(spi);
  283. mpc512x_psc_spi_transfer_setup(spi, NULL);
  284. spi_finalize_current_message(master);
  285. return status;
  286. }
  287. static int mpc512x_psc_spi_prep_xfer_hw(struct spi_master *master)
  288. {
  289. struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
  290. dev_dbg(&master->dev, "%s()\n", __func__);
  291. /* Zero MR2 */
  292. in_8(psc_addr(mps, mr2));
  293. out_8(psc_addr(mps, mr2), 0x0);
  294. /* enable transmitter/receiver */
  295. out_8(psc_addr(mps, command), MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
  296. return 0;
  297. }
  298. static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_master *master)
  299. {
  300. struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
  301. struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
  302. dev_dbg(&master->dev, "%s()\n", __func__);
  303. /* disable transmitter/receiver and fifo interrupt */
  304. out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
  305. out_be32(&fifo->tximr, 0);
  306. return 0;
  307. }
  308. static int mpc512x_psc_spi_setup(struct spi_device *spi)
  309. {
  310. struct mpc512x_psc_spi_cs *cs = spi->controller_state;
  311. int ret;
  312. if (spi->bits_per_word % 8)
  313. return -EINVAL;
  314. if (!cs) {
  315. cs = kzalloc(sizeof *cs, GFP_KERNEL);
  316. if (!cs)
  317. return -ENOMEM;
  318. if (gpio_is_valid(spi->cs_gpio)) {
  319. ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
  320. if (ret) {
  321. dev_err(&spi->dev, "can't get CS gpio: %d\n",
  322. ret);
  323. kfree(cs);
  324. return ret;
  325. }
  326. gpio_direction_output(spi->cs_gpio,
  327. spi->mode & SPI_CS_HIGH ? 0 : 1);
  328. }
  329. spi->controller_state = cs;
  330. }
  331. cs->bits_per_word = spi->bits_per_word;
  332. cs->speed_hz = spi->max_speed_hz;
  333. return 0;
  334. }
  335. static void mpc512x_psc_spi_cleanup(struct spi_device *spi)
  336. {
  337. if (gpio_is_valid(spi->cs_gpio))
  338. gpio_free(spi->cs_gpio);
  339. kfree(spi->controller_state);
  340. }
  341. static int mpc512x_psc_spi_port_config(struct spi_master *master,
  342. struct mpc512x_psc_spi *mps)
  343. {
  344. struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
  345. u32 sicr;
  346. u32 ccr;
  347. int speed;
  348. u16 bclkdiv;
  349. /* Reset the PSC into a known state */
  350. out_8(psc_addr(mps, command), MPC52xx_PSC_RST_RX);
  351. out_8(psc_addr(mps, command), MPC52xx_PSC_RST_TX);
  352. out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
  353. /* Disable psc interrupts all useful interrupts are in fifo */
  354. out_be16(psc_addr(mps, isr_imr.imr), 0);
  355. /* Disable fifo interrupts, will be enabled later */
  356. out_be32(&fifo->tximr, 0);
  357. out_be32(&fifo->rximr, 0);
  358. /* Setup fifo slice address and size */
  359. /*out_be32(&fifo->txsz, 0x0fe00004);*/
  360. /*out_be32(&fifo->rxsz, 0x0ff00004);*/
  361. sicr = 0x01000000 | /* SIM = 0001 -- 8 bit */
  362. 0x00800000 | /* GenClk = 1 -- internal clk */
  363. 0x00008000 | /* SPI = 1 */
  364. 0x00004000 | /* MSTR = 1 -- SPI master */
  365. 0x00000800; /* UseEOF = 1 -- SS low until EOF */
  366. out_be32(psc_addr(mps, sicr), sicr);
  367. ccr = in_be32(psc_addr(mps, ccr));
  368. ccr &= 0xFF000000;
  369. speed = 1000000; /* default 1MHz */
  370. bclkdiv = (mps->mclk_rate / speed) - 1;
  371. ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
  372. out_be32(psc_addr(mps, ccr), ccr);
  373. /* Set 2ms DTL delay */
  374. out_8(psc_addr(mps, ctur), 0x00);
  375. out_8(psc_addr(mps, ctlr), 0x82);
  376. /* we don't use the alarms */
  377. out_be32(&fifo->rxalarm, 0xfff);
  378. out_be32(&fifo->txalarm, 0);
  379. /* Enable FIFO slices for Rx/Tx */
  380. out_be32(&fifo->rxcmd,
  381. MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
  382. out_be32(&fifo->txcmd,
  383. MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
  384. mps->bits_per_word = 8;
  385. return 0;
  386. }
  387. static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
  388. {
  389. struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id;
  390. struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
  391. /* clear interrupt and wake up the rx/tx routine */
  392. if (in_be32(&fifo->txisr) &
  393. in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) {
  394. out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
  395. out_be32(&fifo->tximr, 0);
  396. complete(&mps->txisrdone);
  397. return IRQ_HANDLED;
  398. }
  399. return IRQ_NONE;
  400. }
  401. static void mpc512x_spi_cs_control(struct spi_device *spi, bool onoff)
  402. {
  403. gpio_set_value(spi->cs_gpio, onoff);
  404. }
  405. static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
  406. u32 size, unsigned int irq)
  407. {
  408. struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
  409. struct mpc512x_psc_spi *mps;
  410. struct spi_master *master;
  411. int ret;
  412. void *tempp;
  413. struct clk *clk;
  414. master = spi_alloc_master(dev, sizeof *mps);
  415. if (master == NULL)
  416. return -ENOMEM;
  417. dev_set_drvdata(dev, master);
  418. mps = spi_master_get_devdata(master);
  419. mps->type = (int)of_device_get_match_data(dev);
  420. mps->irq = irq;
  421. if (pdata == NULL) {
  422. mps->cs_control = mpc512x_spi_cs_control;
  423. } else {
  424. mps->cs_control = pdata->cs_control;
  425. master->bus_num = pdata->bus_num;
  426. master->num_chipselect = pdata->max_chipselect;
  427. }
  428. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
  429. master->setup = mpc512x_psc_spi_setup;
  430. master->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw;
  431. master->transfer_one_message = mpc512x_psc_spi_msg_xfer;
  432. master->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw;
  433. master->cleanup = mpc512x_psc_spi_cleanup;
  434. master->dev.of_node = dev->of_node;
  435. tempp = devm_ioremap(dev, regaddr, size);
  436. if (!tempp) {
  437. dev_err(dev, "could not ioremap I/O port range\n");
  438. ret = -EFAULT;
  439. goto free_master;
  440. }
  441. mps->psc = tempp;
  442. mps->fifo =
  443. (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));
  444. ret = devm_request_irq(dev, mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
  445. "mpc512x-psc-spi", mps);
  446. if (ret)
  447. goto free_master;
  448. init_completion(&mps->txisrdone);
  449. clk = devm_clk_get(dev, "mclk");
  450. if (IS_ERR(clk)) {
  451. ret = PTR_ERR(clk);
  452. goto free_master;
  453. }
  454. ret = clk_prepare_enable(clk);
  455. if (ret)
  456. goto free_master;
  457. mps->clk_mclk = clk;
  458. mps->mclk_rate = clk_get_rate(clk);
  459. clk = devm_clk_get(dev, "ipg");
  460. if (IS_ERR(clk)) {
  461. ret = PTR_ERR(clk);
  462. goto free_mclk_clock;
  463. }
  464. ret = clk_prepare_enable(clk);
  465. if (ret)
  466. goto free_mclk_clock;
  467. mps->clk_ipg = clk;
  468. ret = mpc512x_psc_spi_port_config(master, mps);
  469. if (ret < 0)
  470. goto free_ipg_clock;
  471. ret = devm_spi_register_master(dev, master);
  472. if (ret < 0)
  473. goto free_ipg_clock;
  474. return ret;
  475. free_ipg_clock:
  476. clk_disable_unprepare(mps->clk_ipg);
  477. free_mclk_clock:
  478. clk_disable_unprepare(mps->clk_mclk);
  479. free_master:
  480. spi_master_put(master);
  481. return ret;
  482. }
  483. static int mpc512x_psc_spi_do_remove(struct device *dev)
  484. {
  485. struct spi_master *master = dev_get_drvdata(dev);
  486. struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
  487. clk_disable_unprepare(mps->clk_mclk);
  488. clk_disable_unprepare(mps->clk_ipg);
  489. return 0;
  490. }
  491. static int mpc512x_psc_spi_of_probe(struct platform_device *op)
  492. {
  493. const u32 *regaddr_p;
  494. u64 regaddr64, size64;
  495. regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
  496. if (!regaddr_p) {
  497. dev_err(&op->dev, "Invalid PSC address\n");
  498. return -EINVAL;
  499. }
  500. regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
  501. return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64,
  502. irq_of_parse_and_map(op->dev.of_node, 0));
  503. }
  504. static int mpc512x_psc_spi_of_remove(struct platform_device *op)
  505. {
  506. return mpc512x_psc_spi_do_remove(&op->dev);
  507. }
  508. static const struct of_device_id mpc512x_psc_spi_of_match[] = {
  509. { .compatible = "fsl,mpc5121-psc-spi", .data = (void *)TYPE_MPC5121 },
  510. { .compatible = "fsl,mpc5125-psc-spi", .data = (void *)TYPE_MPC5125 },
  511. {},
  512. };
  513. MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match);
  514. static struct platform_driver mpc512x_psc_spi_of_driver = {
  515. .probe = mpc512x_psc_spi_of_probe,
  516. .remove = mpc512x_psc_spi_of_remove,
  517. .driver = {
  518. .name = "mpc512x-psc-spi",
  519. .of_match_table = mpc512x_psc_spi_of_match,
  520. },
  521. };
  522. module_platform_driver(mpc512x_psc_spi_of_driver);
  523. MODULE_AUTHOR("John Rigby");
  524. MODULE_DESCRIPTION("MPC512x PSC SPI Driver");
  525. MODULE_LICENSE("GPL");