spi-meson-spifc.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Driver for Amlogic Meson SPI flash controller (SPIFC)
  4. //
  5. // Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
  6. //
  7. #include <linux/clk.h>
  8. #include <linux/delay.h>
  9. #include <linux/device.h>
  10. #include <linux/io.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/regmap.h>
  17. #include <linux/spi/spi.h>
  18. #include <linux/types.h>
  19. /* register map */
  20. #define REG_CMD 0x00
  21. #define REG_ADDR 0x04
  22. #define REG_CTRL 0x08
  23. #define REG_CTRL1 0x0c
  24. #define REG_STATUS 0x10
  25. #define REG_CTRL2 0x14
  26. #define REG_CLOCK 0x18
  27. #define REG_USER 0x1c
  28. #define REG_USER1 0x20
  29. #define REG_USER2 0x24
  30. #define REG_USER3 0x28
  31. #define REG_USER4 0x2c
  32. #define REG_SLAVE 0x30
  33. #define REG_SLAVE1 0x34
  34. #define REG_SLAVE2 0x38
  35. #define REG_SLAVE3 0x3c
  36. #define REG_C0 0x40
  37. #define REG_B8 0x60
  38. #define REG_MAX 0x7c
  39. /* register fields */
  40. #define CMD_USER BIT(18)
  41. #define CTRL_ENABLE_AHB BIT(17)
  42. #define CLOCK_SOURCE BIT(31)
  43. #define CLOCK_DIV_SHIFT 12
  44. #define CLOCK_DIV_MASK (0x3f << CLOCK_DIV_SHIFT)
  45. #define CLOCK_CNT_HIGH_SHIFT 6
  46. #define CLOCK_CNT_HIGH_MASK (0x3f << CLOCK_CNT_HIGH_SHIFT)
  47. #define CLOCK_CNT_LOW_SHIFT 0
  48. #define CLOCK_CNT_LOW_MASK (0x3f << CLOCK_CNT_LOW_SHIFT)
  49. #define USER_DIN_EN_MS BIT(0)
  50. #define USER_CMP_MODE BIT(2)
  51. #define USER_UC_DOUT_SEL BIT(27)
  52. #define USER_UC_DIN_SEL BIT(28)
  53. #define USER_UC_MASK ((BIT(5) - 1) << 27)
  54. #define USER1_BN_UC_DOUT_SHIFT 17
  55. #define USER1_BN_UC_DOUT_MASK (0xff << 16)
  56. #define USER1_BN_UC_DIN_SHIFT 8
  57. #define USER1_BN_UC_DIN_MASK (0xff << 8)
  58. #define USER4_CS_ACT BIT(30)
  59. #define SLAVE_TRST_DONE BIT(4)
  60. #define SLAVE_OP_MODE BIT(30)
  61. #define SLAVE_SW_RST BIT(31)
  62. #define SPIFC_BUFFER_SIZE 64
  63. /**
  64. * struct meson_spifc
  65. * @master: the SPI master
  66. * @regmap: regmap for device registers
  67. * @clk: input clock of the built-in baud rate generator
  68. * @dev: the device structure
  69. */
  70. struct meson_spifc {
  71. struct spi_master *master;
  72. struct regmap *regmap;
  73. struct clk *clk;
  74. struct device *dev;
  75. };
  76. static const struct regmap_config spifc_regmap_config = {
  77. .reg_bits = 32,
  78. .val_bits = 32,
  79. .reg_stride = 4,
  80. .max_register = REG_MAX,
  81. };
  82. /**
  83. * meson_spifc_wait_ready() - wait for the current operation to terminate
  84. * @spifc: the Meson SPI device
  85. * Return: 0 on success, a negative value on error
  86. */
  87. static int meson_spifc_wait_ready(struct meson_spifc *spifc)
  88. {
  89. unsigned long deadline = jiffies + msecs_to_jiffies(5);
  90. u32 data;
  91. do {
  92. regmap_read(spifc->regmap, REG_SLAVE, &data);
  93. if (data & SLAVE_TRST_DONE)
  94. return 0;
  95. cond_resched();
  96. } while (!time_after(jiffies, deadline));
  97. return -ETIMEDOUT;
  98. }
  99. /**
  100. * meson_spifc_drain_buffer() - copy data from device buffer to memory
  101. * @spifc: the Meson SPI device
  102. * @buf: the destination buffer
  103. * @len: number of bytes to copy
  104. */
  105. static void meson_spifc_drain_buffer(struct meson_spifc *spifc, u8 *buf,
  106. int len)
  107. {
  108. u32 data;
  109. int i = 0;
  110. while (i < len) {
  111. regmap_read(spifc->regmap, REG_C0 + i, &data);
  112. if (len - i >= 4) {
  113. *((u32 *)buf) = data;
  114. buf += 4;
  115. } else {
  116. memcpy(buf, &data, len - i);
  117. break;
  118. }
  119. i += 4;
  120. }
  121. }
  122. /**
  123. * meson_spifc_fill_buffer() - copy data from memory to device buffer
  124. * @spifc: the Meson SPI device
  125. * @buf: the source buffer
  126. * @len: number of bytes to copy
  127. */
  128. static void meson_spifc_fill_buffer(struct meson_spifc *spifc, const u8 *buf,
  129. int len)
  130. {
  131. u32 data;
  132. int i = 0;
  133. while (i < len) {
  134. if (len - i >= 4)
  135. data = *(u32 *)buf;
  136. else
  137. memcpy(&data, buf, len - i);
  138. regmap_write(spifc->regmap, REG_C0 + i, data);
  139. buf += 4;
  140. i += 4;
  141. }
  142. }
  143. /**
  144. * meson_spifc_setup_speed() - program the clock divider
  145. * @spifc: the Meson SPI device
  146. * @speed: desired speed in Hz
  147. */
  148. static void meson_spifc_setup_speed(struct meson_spifc *spifc, u32 speed)
  149. {
  150. unsigned long parent, value;
  151. int n;
  152. parent = clk_get_rate(spifc->clk);
  153. n = max_t(int, parent / speed - 1, 1);
  154. dev_dbg(spifc->dev, "parent %lu, speed %u, n %d\n", parent,
  155. speed, n);
  156. value = (n << CLOCK_DIV_SHIFT) & CLOCK_DIV_MASK;
  157. value |= (n << CLOCK_CNT_LOW_SHIFT) & CLOCK_CNT_LOW_MASK;
  158. value |= (((n + 1) / 2 - 1) << CLOCK_CNT_HIGH_SHIFT) &
  159. CLOCK_CNT_HIGH_MASK;
  160. regmap_write(spifc->regmap, REG_CLOCK, value);
  161. }
  162. /**
  163. * meson_spifc_txrx() - transfer a chunk of data
  164. * @spifc: the Meson SPI device
  165. * @xfer: the current SPI transfer
  166. * @offset: offset of the data to transfer
  167. * @len: length of the data to transfer
  168. * @last_xfer: whether this is the last transfer of the message
  169. * @last_chunk: whether this is the last chunk of the transfer
  170. * Return: 0 on success, a negative value on error
  171. */
  172. static int meson_spifc_txrx(struct meson_spifc *spifc,
  173. struct spi_transfer *xfer,
  174. int offset, int len, bool last_xfer,
  175. bool last_chunk)
  176. {
  177. bool keep_cs = true;
  178. int ret;
  179. if (xfer->tx_buf)
  180. meson_spifc_fill_buffer(spifc, xfer->tx_buf + offset, len);
  181. /* enable DOUT stage */
  182. regmap_update_bits(spifc->regmap, REG_USER, USER_UC_MASK,
  183. USER_UC_DOUT_SEL);
  184. regmap_write(spifc->regmap, REG_USER1,
  185. (8 * len - 1) << USER1_BN_UC_DOUT_SHIFT);
  186. /* enable data input during DOUT */
  187. regmap_update_bits(spifc->regmap, REG_USER, USER_DIN_EN_MS,
  188. USER_DIN_EN_MS);
  189. if (last_chunk) {
  190. if (last_xfer)
  191. keep_cs = xfer->cs_change;
  192. else
  193. keep_cs = !xfer->cs_change;
  194. }
  195. regmap_update_bits(spifc->regmap, REG_USER4, USER4_CS_ACT,
  196. keep_cs ? USER4_CS_ACT : 0);
  197. /* clear transition done bit */
  198. regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_TRST_DONE, 0);
  199. /* start transfer */
  200. regmap_update_bits(spifc->regmap, REG_CMD, CMD_USER, CMD_USER);
  201. ret = meson_spifc_wait_ready(spifc);
  202. if (!ret && xfer->rx_buf)
  203. meson_spifc_drain_buffer(spifc, xfer->rx_buf + offset, len);
  204. return ret;
  205. }
  206. /**
  207. * meson_spifc_transfer_one() - perform a single transfer
  208. * @master: the SPI master
  209. * @spi: the SPI device
  210. * @xfer: the current SPI transfer
  211. * Return: 0 on success, a negative value on error
  212. */
  213. static int meson_spifc_transfer_one(struct spi_master *master,
  214. struct spi_device *spi,
  215. struct spi_transfer *xfer)
  216. {
  217. struct meson_spifc *spifc = spi_master_get_devdata(master);
  218. int len, done = 0, ret = 0;
  219. meson_spifc_setup_speed(spifc, xfer->speed_hz);
  220. regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB, 0);
  221. while (done < xfer->len && !ret) {
  222. len = min_t(int, xfer->len - done, SPIFC_BUFFER_SIZE);
  223. ret = meson_spifc_txrx(spifc, xfer, done, len,
  224. spi_transfer_is_last(master, xfer),
  225. done + len >= xfer->len);
  226. done += len;
  227. }
  228. regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB,
  229. CTRL_ENABLE_AHB);
  230. return ret;
  231. }
  232. /**
  233. * meson_spifc_hw_init() - reset and initialize the SPI controller
  234. * @spifc: the Meson SPI device
  235. */
  236. static void meson_spifc_hw_init(struct meson_spifc *spifc)
  237. {
  238. /* reset device */
  239. regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_SW_RST,
  240. SLAVE_SW_RST);
  241. /* disable compatible mode */
  242. regmap_update_bits(spifc->regmap, REG_USER, USER_CMP_MODE, 0);
  243. /* set master mode */
  244. regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_OP_MODE, 0);
  245. }
  246. static int meson_spifc_probe(struct platform_device *pdev)
  247. {
  248. struct spi_master *master;
  249. struct meson_spifc *spifc;
  250. void __iomem *base;
  251. unsigned int rate;
  252. int ret = 0;
  253. master = spi_alloc_master(&pdev->dev, sizeof(struct meson_spifc));
  254. if (!master)
  255. return -ENOMEM;
  256. platform_set_drvdata(pdev, master);
  257. spifc = spi_master_get_devdata(master);
  258. spifc->dev = &pdev->dev;
  259. base = devm_platform_ioremap_resource(pdev, 0);
  260. if (IS_ERR(base)) {
  261. ret = PTR_ERR(base);
  262. goto out_err;
  263. }
  264. spifc->regmap = devm_regmap_init_mmio(spifc->dev, base,
  265. &spifc_regmap_config);
  266. if (IS_ERR(spifc->regmap)) {
  267. ret = PTR_ERR(spifc->regmap);
  268. goto out_err;
  269. }
  270. spifc->clk = devm_clk_get(spifc->dev, NULL);
  271. if (IS_ERR(spifc->clk)) {
  272. dev_err(spifc->dev, "missing clock\n");
  273. ret = PTR_ERR(spifc->clk);
  274. goto out_err;
  275. }
  276. ret = clk_prepare_enable(spifc->clk);
  277. if (ret) {
  278. dev_err(spifc->dev, "can't prepare clock\n");
  279. goto out_err;
  280. }
  281. rate = clk_get_rate(spifc->clk);
  282. master->num_chipselect = 1;
  283. master->dev.of_node = pdev->dev.of_node;
  284. master->bits_per_word_mask = SPI_BPW_MASK(8);
  285. master->auto_runtime_pm = true;
  286. master->transfer_one = meson_spifc_transfer_one;
  287. master->min_speed_hz = rate >> 6;
  288. master->max_speed_hz = rate >> 1;
  289. meson_spifc_hw_init(spifc);
  290. pm_runtime_set_active(spifc->dev);
  291. pm_runtime_enable(spifc->dev);
  292. ret = devm_spi_register_master(spifc->dev, master);
  293. if (ret) {
  294. dev_err(spifc->dev, "failed to register spi master\n");
  295. goto out_clk;
  296. }
  297. return 0;
  298. out_clk:
  299. clk_disable_unprepare(spifc->clk);
  300. pm_runtime_disable(spifc->dev);
  301. out_err:
  302. spi_master_put(master);
  303. return ret;
  304. }
  305. static int meson_spifc_remove(struct platform_device *pdev)
  306. {
  307. struct spi_master *master = platform_get_drvdata(pdev);
  308. struct meson_spifc *spifc = spi_master_get_devdata(master);
  309. pm_runtime_get_sync(&pdev->dev);
  310. clk_disable_unprepare(spifc->clk);
  311. pm_runtime_disable(&pdev->dev);
  312. return 0;
  313. }
  314. #ifdef CONFIG_PM_SLEEP
  315. static int meson_spifc_suspend(struct device *dev)
  316. {
  317. struct spi_master *master = dev_get_drvdata(dev);
  318. struct meson_spifc *spifc = spi_master_get_devdata(master);
  319. int ret;
  320. ret = spi_master_suspend(master);
  321. if (ret)
  322. return ret;
  323. if (!pm_runtime_suspended(dev))
  324. clk_disable_unprepare(spifc->clk);
  325. return 0;
  326. }
  327. static int meson_spifc_resume(struct device *dev)
  328. {
  329. struct spi_master *master = dev_get_drvdata(dev);
  330. struct meson_spifc *spifc = spi_master_get_devdata(master);
  331. int ret;
  332. if (!pm_runtime_suspended(dev)) {
  333. ret = clk_prepare_enable(spifc->clk);
  334. if (ret)
  335. return ret;
  336. }
  337. meson_spifc_hw_init(spifc);
  338. ret = spi_master_resume(master);
  339. if (ret)
  340. clk_disable_unprepare(spifc->clk);
  341. return ret;
  342. }
  343. #endif /* CONFIG_PM_SLEEP */
  344. #ifdef CONFIG_PM
  345. static int meson_spifc_runtime_suspend(struct device *dev)
  346. {
  347. struct spi_master *master = dev_get_drvdata(dev);
  348. struct meson_spifc *spifc = spi_master_get_devdata(master);
  349. clk_disable_unprepare(spifc->clk);
  350. return 0;
  351. }
  352. static int meson_spifc_runtime_resume(struct device *dev)
  353. {
  354. struct spi_master *master = dev_get_drvdata(dev);
  355. struct meson_spifc *spifc = spi_master_get_devdata(master);
  356. return clk_prepare_enable(spifc->clk);
  357. }
  358. #endif /* CONFIG_PM */
  359. static const struct dev_pm_ops meson_spifc_pm_ops = {
  360. SET_SYSTEM_SLEEP_PM_OPS(meson_spifc_suspend, meson_spifc_resume)
  361. SET_RUNTIME_PM_OPS(meson_spifc_runtime_suspend,
  362. meson_spifc_runtime_resume,
  363. NULL)
  364. };
  365. static const struct of_device_id meson_spifc_dt_match[] = {
  366. { .compatible = "amlogic,meson6-spifc", },
  367. { .compatible = "amlogic,meson-gxbb-spifc", },
  368. { },
  369. };
  370. MODULE_DEVICE_TABLE(of, meson_spifc_dt_match);
  371. static struct platform_driver meson_spifc_driver = {
  372. .probe = meson_spifc_probe,
  373. .remove = meson_spifc_remove,
  374. .driver = {
  375. .name = "meson-spifc",
  376. .of_match_table = of_match_ptr(meson_spifc_dt_match),
  377. .pm = &meson_spifc_pm_ops,
  378. },
  379. };
  380. module_platform_driver(meson_spifc_driver);
  381. MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
  382. MODULE_DESCRIPTION("Amlogic Meson SPIFC driver");
  383. MODULE_LICENSE("GPL v2");