spi-meson-spicc.c 22 KB

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  1. /*
  2. * Driver for Amlogic Meson SPI communication controller (SPICC)
  3. *
  4. * Copyright (C) BayLibre, SAS
  5. * Author: Neil Armstrong <narmstrong@baylibre.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <linux/bitfield.h>
  10. #include <linux/clk.h>
  11. #include <linux/clk-provider.h>
  12. #include <linux/device.h>
  13. #include <linux/io.h>
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/of_device.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/spi/spi.h>
  20. #include <linux/types.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/reset.h>
  23. /*
  24. * The Meson SPICC controller could support DMA based transfers, but is not
  25. * implemented by the vendor code, and while having the registers documentation
  26. * it has never worked on the GXL Hardware.
  27. * The PIO mode is the only mode implemented, and due to badly designed HW :
  28. * - all transfers are cutted in 16 words burst because the FIFO hangs on
  29. * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
  30. * FIFO max size chunk only
  31. * - CS management is dumb, and goes UP between every burst, so is really a
  32. * "Data Valid" signal than a Chip Select, GPIO link should be used instead
  33. * to have a CS go down over the full transfer
  34. */
  35. #define SPICC_MAX_BURST 128
  36. /* Register Map */
  37. #define SPICC_RXDATA 0x00
  38. #define SPICC_TXDATA 0x04
  39. #define SPICC_CONREG 0x08
  40. #define SPICC_ENABLE BIT(0)
  41. #define SPICC_MODE_MASTER BIT(1)
  42. #define SPICC_XCH BIT(2)
  43. #define SPICC_SMC BIT(3)
  44. #define SPICC_POL BIT(4)
  45. #define SPICC_PHA BIT(5)
  46. #define SPICC_SSCTL BIT(6)
  47. #define SPICC_SSPOL BIT(7)
  48. #define SPICC_DRCTL_MASK GENMASK(9, 8)
  49. #define SPICC_DRCTL_IGNORE 0
  50. #define SPICC_DRCTL_FALLING 1
  51. #define SPICC_DRCTL_LOWLEVEL 2
  52. #define SPICC_CS_MASK GENMASK(13, 12)
  53. #define SPICC_DATARATE_MASK GENMASK(18, 16)
  54. #define SPICC_DATARATE_DIV4 0
  55. #define SPICC_DATARATE_DIV8 1
  56. #define SPICC_DATARATE_DIV16 2
  57. #define SPICC_DATARATE_DIV32 3
  58. #define SPICC_BITLENGTH_MASK GENMASK(24, 19)
  59. #define SPICC_BURSTLENGTH_MASK GENMASK(31, 25)
  60. #define SPICC_INTREG 0x0c
  61. #define SPICC_TE_EN BIT(0) /* TX FIFO Empty Interrupt */
  62. #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
  63. #define SPICC_TF_EN BIT(2) /* TX FIFO Full Interrupt */
  64. #define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */
  65. #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
  66. #define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */
  67. #define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */
  68. #define SPICC_TC_EN BIT(7) /* Transfert Complete Interrupt */
  69. #define SPICC_DMAREG 0x10
  70. #define SPICC_DMA_ENABLE BIT(0)
  71. #define SPICC_TXFIFO_THRESHOLD_MASK GENMASK(5, 1)
  72. #define SPICC_RXFIFO_THRESHOLD_MASK GENMASK(10, 6)
  73. #define SPICC_READ_BURST_MASK GENMASK(14, 11)
  74. #define SPICC_WRITE_BURST_MASK GENMASK(18, 15)
  75. #define SPICC_DMA_URGENT BIT(19)
  76. #define SPICC_DMA_THREADID_MASK GENMASK(25, 20)
  77. #define SPICC_DMA_BURSTNUM_MASK GENMASK(31, 26)
  78. #define SPICC_STATREG 0x14
  79. #define SPICC_TE BIT(0) /* TX FIFO Empty Interrupt */
  80. #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
  81. #define SPICC_TF BIT(2) /* TX FIFO Full Interrupt */
  82. #define SPICC_RR BIT(3) /* RX FIFO Ready Interrupt */
  83. #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */
  84. #define SPICC_RF BIT(5) /* RX FIFO Full Interrupt */
  85. #define SPICC_RO BIT(6) /* RX FIFO Overflow Interrupt */
  86. #define SPICC_TC BIT(7) /* Transfert Complete Interrupt */
  87. #define SPICC_PERIODREG 0x18
  88. #define SPICC_PERIOD GENMASK(14, 0) /* Wait cycles */
  89. #define SPICC_TESTREG 0x1c
  90. #define SPICC_TXCNT_MASK GENMASK(4, 0) /* TX FIFO Counter */
  91. #define SPICC_RXCNT_MASK GENMASK(9, 5) /* RX FIFO Counter */
  92. #define SPICC_SMSTATUS_MASK GENMASK(12, 10) /* State Machine Status */
  93. #define SPICC_LBC_RO BIT(13) /* Loop Back Control Read-Only */
  94. #define SPICC_LBC_W1 BIT(14) /* Loop Back Control Write-Only */
  95. #define SPICC_SWAP_RO BIT(14) /* RX FIFO Data Swap Read-Only */
  96. #define SPICC_SWAP_W1 BIT(15) /* RX FIFO Data Swap Write-Only */
  97. #define SPICC_DLYCTL_RO_MASK GENMASK(20, 15) /* Delay Control Read-Only */
  98. #define SPICC_MO_DELAY_MASK GENMASK(17, 16) /* Master Output Delay */
  99. #define SPICC_MO_NO_DELAY 0
  100. #define SPICC_MO_DELAY_1_CYCLE 1
  101. #define SPICC_MO_DELAY_2_CYCLE 2
  102. #define SPICC_MO_DELAY_3_CYCLE 3
  103. #define SPICC_MI_DELAY_MASK GENMASK(19, 18) /* Master Input Delay */
  104. #define SPICC_MI_NO_DELAY 0
  105. #define SPICC_MI_DELAY_1_CYCLE 1
  106. #define SPICC_MI_DELAY_2_CYCLE 2
  107. #define SPICC_MI_DELAY_3_CYCLE 3
  108. #define SPICC_MI_CAP_DELAY_MASK GENMASK(21, 20) /* Master Capture Delay */
  109. #define SPICC_CAP_AHEAD_2_CYCLE 0
  110. #define SPICC_CAP_AHEAD_1_CYCLE 1
  111. #define SPICC_CAP_NO_DELAY 2
  112. #define SPICC_CAP_DELAY_1_CYCLE 3
  113. #define SPICC_FIFORST_RO_MASK GENMASK(22, 21) /* FIFO Softreset Read-Only */
  114. #define SPICC_FIFORST_W1_MASK GENMASK(23, 22) /* FIFO Softreset Write-Only */
  115. #define SPICC_DRADDR 0x20 /* Read Address of DMA */
  116. #define SPICC_DWADDR 0x24 /* Write Address of DMA */
  117. #define SPICC_ENH_CTL0 0x38 /* Enhanced Feature */
  118. #define SPICC_ENH_CLK_CS_DELAY_MASK GENMASK(15, 0)
  119. #define SPICC_ENH_DATARATE_MASK GENMASK(23, 16)
  120. #define SPICC_ENH_DATARATE_EN BIT(24)
  121. #define SPICC_ENH_MOSI_OEN BIT(25)
  122. #define SPICC_ENH_CLK_OEN BIT(26)
  123. #define SPICC_ENH_CS_OEN BIT(27)
  124. #define SPICC_ENH_CLK_CS_DELAY_EN BIT(28)
  125. #define SPICC_ENH_MAIN_CLK_AO BIT(29)
  126. #define writel_bits_relaxed(mask, val, addr) \
  127. writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
  128. struct meson_spicc_data {
  129. unsigned int max_speed_hz;
  130. unsigned int min_speed_hz;
  131. unsigned int fifo_size;
  132. bool has_oen;
  133. bool has_enhance_clk_div;
  134. bool has_pclk;
  135. };
  136. struct meson_spicc_device {
  137. struct spi_master *master;
  138. struct platform_device *pdev;
  139. void __iomem *base;
  140. struct clk *core;
  141. struct clk *pclk;
  142. struct clk *clk;
  143. struct spi_message *message;
  144. struct spi_transfer *xfer;
  145. const struct meson_spicc_data *data;
  146. u8 *tx_buf;
  147. u8 *rx_buf;
  148. unsigned int bytes_per_word;
  149. unsigned long tx_remain;
  150. unsigned long rx_remain;
  151. unsigned long xfer_remain;
  152. };
  153. static void meson_spicc_oen_enable(struct meson_spicc_device *spicc)
  154. {
  155. u32 conf;
  156. if (!spicc->data->has_oen)
  157. return;
  158. conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) |
  159. SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN;
  160. writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0);
  161. }
  162. static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc)
  163. {
  164. return !!FIELD_GET(SPICC_TF,
  165. readl_relaxed(spicc->base + SPICC_STATREG));
  166. }
  167. static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc)
  168. {
  169. return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF,
  170. readl_relaxed(spicc->base + SPICC_STATREG));
  171. }
  172. static inline u32 meson_spicc_pull_data(struct meson_spicc_device *spicc)
  173. {
  174. unsigned int bytes = spicc->bytes_per_word;
  175. unsigned int byte_shift = 0;
  176. u32 data = 0;
  177. u8 byte;
  178. while (bytes--) {
  179. byte = *spicc->tx_buf++;
  180. data |= (byte & 0xff) << byte_shift;
  181. byte_shift += 8;
  182. }
  183. spicc->tx_remain--;
  184. return data;
  185. }
  186. static inline void meson_spicc_push_data(struct meson_spicc_device *spicc,
  187. u32 data)
  188. {
  189. unsigned int bytes = spicc->bytes_per_word;
  190. unsigned int byte_shift = 0;
  191. u8 byte;
  192. while (bytes--) {
  193. byte = (data >> byte_shift) & 0xff;
  194. *spicc->rx_buf++ = byte;
  195. byte_shift += 8;
  196. }
  197. spicc->rx_remain--;
  198. }
  199. static inline void meson_spicc_rx(struct meson_spicc_device *spicc)
  200. {
  201. /* Empty RX FIFO */
  202. while (spicc->rx_remain &&
  203. meson_spicc_rxready(spicc))
  204. meson_spicc_push_data(spicc,
  205. readl_relaxed(spicc->base + SPICC_RXDATA));
  206. }
  207. static inline void meson_spicc_tx(struct meson_spicc_device *spicc)
  208. {
  209. /* Fill Up TX FIFO */
  210. while (spicc->tx_remain &&
  211. !meson_spicc_txfull(spicc))
  212. writel_relaxed(meson_spicc_pull_data(spicc),
  213. spicc->base + SPICC_TXDATA);
  214. }
  215. static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc)
  216. {
  217. unsigned int burst_len = min_t(unsigned int,
  218. spicc->xfer_remain /
  219. spicc->bytes_per_word,
  220. spicc->data->fifo_size);
  221. /* Setup Xfer variables */
  222. spicc->tx_remain = burst_len;
  223. spicc->rx_remain = burst_len;
  224. spicc->xfer_remain -= burst_len * spicc->bytes_per_word;
  225. /* Setup burst length */
  226. writel_bits_relaxed(SPICC_BURSTLENGTH_MASK,
  227. FIELD_PREP(SPICC_BURSTLENGTH_MASK,
  228. burst_len - 1),
  229. spicc->base + SPICC_CONREG);
  230. /* Fill TX FIFO */
  231. meson_spicc_tx(spicc);
  232. }
  233. static irqreturn_t meson_spicc_irq(int irq, void *data)
  234. {
  235. struct meson_spicc_device *spicc = (void *) data;
  236. writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG);
  237. /* Empty RX FIFO */
  238. meson_spicc_rx(spicc);
  239. if (!spicc->xfer_remain) {
  240. /* Disable all IRQs */
  241. writel(0, spicc->base + SPICC_INTREG);
  242. spi_finalize_current_transfer(spicc->master);
  243. return IRQ_HANDLED;
  244. }
  245. /* Setup burst */
  246. meson_spicc_setup_burst(spicc);
  247. /* Start burst */
  248. writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
  249. return IRQ_HANDLED;
  250. }
  251. static void meson_spicc_auto_io_delay(struct meson_spicc_device *spicc)
  252. {
  253. u32 div, hz;
  254. u32 mi_delay, cap_delay;
  255. u32 conf;
  256. if (spicc->data->has_enhance_clk_div) {
  257. div = FIELD_GET(SPICC_ENH_DATARATE_MASK,
  258. readl_relaxed(spicc->base + SPICC_ENH_CTL0));
  259. div++;
  260. div <<= 1;
  261. } else {
  262. div = FIELD_GET(SPICC_DATARATE_MASK,
  263. readl_relaxed(spicc->base + SPICC_CONREG));
  264. div += 2;
  265. div = 1 << div;
  266. }
  267. mi_delay = SPICC_MI_NO_DELAY;
  268. cap_delay = SPICC_CAP_AHEAD_2_CYCLE;
  269. hz = clk_get_rate(spicc->clk);
  270. if (hz >= 100000000)
  271. cap_delay = SPICC_CAP_DELAY_1_CYCLE;
  272. else if (hz >= 80000000)
  273. cap_delay = SPICC_CAP_NO_DELAY;
  274. else if (hz >= 40000000)
  275. cap_delay = SPICC_CAP_AHEAD_1_CYCLE;
  276. else if (div >= 16)
  277. mi_delay = SPICC_MI_DELAY_3_CYCLE;
  278. else if (div >= 8)
  279. mi_delay = SPICC_MI_DELAY_2_CYCLE;
  280. else if (div >= 6)
  281. mi_delay = SPICC_MI_DELAY_1_CYCLE;
  282. conf = readl_relaxed(spicc->base + SPICC_TESTREG);
  283. conf &= ~(SPICC_MO_DELAY_MASK | SPICC_MI_DELAY_MASK
  284. | SPICC_MI_CAP_DELAY_MASK);
  285. conf |= FIELD_PREP(SPICC_MI_DELAY_MASK, mi_delay);
  286. conf |= FIELD_PREP(SPICC_MI_CAP_DELAY_MASK, cap_delay);
  287. writel_relaxed(conf, spicc->base + SPICC_TESTREG);
  288. }
  289. static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
  290. struct spi_transfer *xfer)
  291. {
  292. u32 conf, conf_orig;
  293. /* Read original configuration */
  294. conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);
  295. /* Setup word width */
  296. conf &= ~SPICC_BITLENGTH_MASK;
  297. conf |= FIELD_PREP(SPICC_BITLENGTH_MASK,
  298. (spicc->bytes_per_word << 3) - 1);
  299. /* Ignore if unchanged */
  300. if (conf != conf_orig)
  301. writel_relaxed(conf, spicc->base + SPICC_CONREG);
  302. clk_set_rate(spicc->clk, xfer->speed_hz);
  303. meson_spicc_auto_io_delay(spicc);
  304. writel_relaxed(0, spicc->base + SPICC_DMAREG);
  305. }
  306. static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc)
  307. {
  308. if (spicc->data->has_oen)
  309. writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO,
  310. SPICC_ENH_MAIN_CLK_AO,
  311. spicc->base + SPICC_ENH_CTL0);
  312. writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK,
  313. spicc->base + SPICC_TESTREG);
  314. while (meson_spicc_rxready(spicc))
  315. readl_relaxed(spicc->base + SPICC_RXDATA);
  316. if (spicc->data->has_oen)
  317. writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0,
  318. spicc->base + SPICC_ENH_CTL0);
  319. }
  320. static int meson_spicc_transfer_one(struct spi_master *master,
  321. struct spi_device *spi,
  322. struct spi_transfer *xfer)
  323. {
  324. struct meson_spicc_device *spicc = spi_master_get_devdata(master);
  325. /* Store current transfer */
  326. spicc->xfer = xfer;
  327. /* Setup transfer parameters */
  328. spicc->tx_buf = (u8 *)xfer->tx_buf;
  329. spicc->rx_buf = (u8 *)xfer->rx_buf;
  330. spicc->xfer_remain = xfer->len;
  331. /* Pre-calculate word size */
  332. spicc->bytes_per_word =
  333. DIV_ROUND_UP(spicc->xfer->bits_per_word, 8);
  334. if (xfer->len % spicc->bytes_per_word)
  335. return -EINVAL;
  336. /* Setup transfer parameters */
  337. meson_spicc_setup_xfer(spicc, xfer);
  338. meson_spicc_reset_fifo(spicc);
  339. /* Setup burst */
  340. meson_spicc_setup_burst(spicc);
  341. /* Start burst */
  342. writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
  343. /* Enable interrupts */
  344. writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG);
  345. return 1;
  346. }
  347. static int meson_spicc_prepare_message(struct spi_master *master,
  348. struct spi_message *message)
  349. {
  350. struct meson_spicc_device *spicc = spi_master_get_devdata(master);
  351. struct spi_device *spi = message->spi;
  352. u32 conf = 0;
  353. /* Store current message */
  354. spicc->message = message;
  355. /* Enable Master */
  356. conf |= SPICC_ENABLE;
  357. conf |= SPICC_MODE_MASTER;
  358. /* SMC = 0 */
  359. /* Setup transfer mode */
  360. if (spi->mode & SPI_CPOL)
  361. conf |= SPICC_POL;
  362. else
  363. conf &= ~SPICC_POL;
  364. if (spi->mode & SPI_CPHA)
  365. conf |= SPICC_PHA;
  366. else
  367. conf &= ~SPICC_PHA;
  368. /* SSCTL = 0 */
  369. if (spi->mode & SPI_CS_HIGH)
  370. conf |= SPICC_SSPOL;
  371. else
  372. conf &= ~SPICC_SSPOL;
  373. if (spi->mode & SPI_READY)
  374. conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_LOWLEVEL);
  375. else
  376. conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE);
  377. /* Select CS */
  378. conf |= FIELD_PREP(SPICC_CS_MASK, spi->chip_select);
  379. /* Default Clock rate core/4 */
  380. /* Default 8bit word */
  381. conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1);
  382. writel_relaxed(conf, spicc->base + SPICC_CONREG);
  383. /* Setup no wait cycles by default */
  384. writel_relaxed(0, spicc->base + SPICC_PERIODREG);
  385. writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG);
  386. return 0;
  387. }
  388. static int meson_spicc_unprepare_transfer(struct spi_master *master)
  389. {
  390. struct meson_spicc_device *spicc = spi_master_get_devdata(master);
  391. /* Disable all IRQs */
  392. writel(0, spicc->base + SPICC_INTREG);
  393. device_reset_optional(&spicc->pdev->dev);
  394. return 0;
  395. }
  396. static int meson_spicc_setup(struct spi_device *spi)
  397. {
  398. if (!spi->controller_state)
  399. spi->controller_state = spi_master_get_devdata(spi->master);
  400. return 0;
  401. }
  402. static void meson_spicc_cleanup(struct spi_device *spi)
  403. {
  404. spi->controller_state = NULL;
  405. }
  406. /*
  407. * The Clock Mux
  408. * x-----------------x x------------x x------\
  409. * |---| pow2 fixed div |---| pow2 div |----| |
  410. * | x-----------------x x------------x | |
  411. * src ---| | mux |-- out
  412. * | x-----------------x x------------x | |
  413. * |---| enh fixed div |---| enh div |0---| |
  414. * x-----------------x x------------x x------/
  415. *
  416. * Clk path for GX series:
  417. * src -> pow2 fixed div -> pow2 div -> out
  418. *
  419. * Clk path for AXG series:
  420. * src -> pow2 fixed div -> pow2 div -> mux -> out
  421. * src -> enh fixed div -> enh div -> mux -> out
  422. *
  423. * Clk path for G12A series:
  424. * pclk -> pow2 fixed div -> pow2 div -> mux -> out
  425. * pclk -> enh fixed div -> enh div -> mux -> out
  426. */
  427. static int meson_spicc_clk_init(struct meson_spicc_device *spicc)
  428. {
  429. struct device *dev = &spicc->pdev->dev;
  430. struct clk_fixed_factor *pow2_fixed_div, *enh_fixed_div;
  431. struct clk_divider *pow2_div, *enh_div;
  432. struct clk_mux *mux;
  433. struct clk_init_data init;
  434. struct clk *clk;
  435. struct clk_parent_data parent_data[2];
  436. char name[64];
  437. memset(&init, 0, sizeof(init));
  438. memset(&parent_data, 0, sizeof(parent_data));
  439. init.parent_data = parent_data;
  440. /* algorithm for pow2 div: rate = freq / 4 / (2 ^ N) */
  441. pow2_fixed_div = devm_kzalloc(dev, sizeof(*pow2_fixed_div), GFP_KERNEL);
  442. if (!pow2_fixed_div)
  443. return -ENOMEM;
  444. snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev));
  445. init.name = name;
  446. init.ops = &clk_fixed_factor_ops;
  447. init.flags = 0;
  448. if (spicc->data->has_pclk)
  449. parent_data[0].hw = __clk_get_hw(spicc->pclk);
  450. else
  451. parent_data[0].hw = __clk_get_hw(spicc->core);
  452. init.num_parents = 1;
  453. pow2_fixed_div->mult = 1,
  454. pow2_fixed_div->div = 4,
  455. pow2_fixed_div->hw.init = &init;
  456. clk = devm_clk_register(dev, &pow2_fixed_div->hw);
  457. if (WARN_ON(IS_ERR(clk)))
  458. return PTR_ERR(clk);
  459. pow2_div = devm_kzalloc(dev, sizeof(*pow2_div), GFP_KERNEL);
  460. if (!pow2_div)
  461. return -ENOMEM;
  462. snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev));
  463. init.name = name;
  464. init.ops = &clk_divider_ops;
  465. init.flags = CLK_SET_RATE_PARENT;
  466. parent_data[0].hw = &pow2_fixed_div->hw;
  467. init.num_parents = 1;
  468. pow2_div->shift = 16,
  469. pow2_div->width = 3,
  470. pow2_div->flags = CLK_DIVIDER_POWER_OF_TWO,
  471. pow2_div->reg = spicc->base + SPICC_CONREG;
  472. pow2_div->hw.init = &init;
  473. clk = devm_clk_register(dev, &pow2_div->hw);
  474. if (WARN_ON(IS_ERR(clk)))
  475. return PTR_ERR(clk);
  476. if (!spicc->data->has_enhance_clk_div) {
  477. spicc->clk = clk;
  478. return 0;
  479. }
  480. /* algorithm for enh div: rate = freq / 2 / (N + 1) */
  481. enh_fixed_div = devm_kzalloc(dev, sizeof(*enh_fixed_div), GFP_KERNEL);
  482. if (!enh_fixed_div)
  483. return -ENOMEM;
  484. snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev));
  485. init.name = name;
  486. init.ops = &clk_fixed_factor_ops;
  487. init.flags = 0;
  488. if (spicc->data->has_pclk)
  489. parent_data[0].hw = __clk_get_hw(spicc->pclk);
  490. else
  491. parent_data[0].hw = __clk_get_hw(spicc->core);
  492. init.num_parents = 1;
  493. enh_fixed_div->mult = 1,
  494. enh_fixed_div->div = 2,
  495. enh_fixed_div->hw.init = &init;
  496. clk = devm_clk_register(dev, &enh_fixed_div->hw);
  497. if (WARN_ON(IS_ERR(clk)))
  498. return PTR_ERR(clk);
  499. enh_div = devm_kzalloc(dev, sizeof(*enh_div), GFP_KERNEL);
  500. if (!enh_div)
  501. return -ENOMEM;
  502. snprintf(name, sizeof(name), "%s#enh_div", dev_name(dev));
  503. init.name = name;
  504. init.ops = &clk_divider_ops;
  505. init.flags = CLK_SET_RATE_PARENT;
  506. parent_data[0].hw = &enh_fixed_div->hw;
  507. init.num_parents = 1;
  508. enh_div->shift = 16,
  509. enh_div->width = 8,
  510. enh_div->reg = spicc->base + SPICC_ENH_CTL0;
  511. enh_div->hw.init = &init;
  512. clk = devm_clk_register(dev, &enh_div->hw);
  513. if (WARN_ON(IS_ERR(clk)))
  514. return PTR_ERR(clk);
  515. mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
  516. if (!mux)
  517. return -ENOMEM;
  518. snprintf(name, sizeof(name), "%s#sel", dev_name(dev));
  519. init.name = name;
  520. init.ops = &clk_mux_ops;
  521. parent_data[0].hw = &pow2_div->hw;
  522. parent_data[1].hw = &enh_div->hw;
  523. init.num_parents = 2;
  524. init.flags = CLK_SET_RATE_PARENT;
  525. mux->mask = 0x1,
  526. mux->shift = 24,
  527. mux->reg = spicc->base + SPICC_ENH_CTL0;
  528. mux->hw.init = &init;
  529. spicc->clk = devm_clk_register(dev, &mux->hw);
  530. if (WARN_ON(IS_ERR(spicc->clk)))
  531. return PTR_ERR(spicc->clk);
  532. return 0;
  533. }
  534. static int meson_spicc_probe(struct platform_device *pdev)
  535. {
  536. struct spi_master *master;
  537. struct meson_spicc_device *spicc;
  538. int ret, irq;
  539. master = spi_alloc_master(&pdev->dev, sizeof(*spicc));
  540. if (!master) {
  541. dev_err(&pdev->dev, "master allocation failed\n");
  542. return -ENOMEM;
  543. }
  544. spicc = spi_master_get_devdata(master);
  545. spicc->master = master;
  546. spicc->data = of_device_get_match_data(&pdev->dev);
  547. if (!spicc->data) {
  548. dev_err(&pdev->dev, "failed to get match data\n");
  549. ret = -EINVAL;
  550. goto out_master;
  551. }
  552. spicc->pdev = pdev;
  553. platform_set_drvdata(pdev, spicc);
  554. spicc->base = devm_platform_ioremap_resource(pdev, 0);
  555. if (IS_ERR(spicc->base)) {
  556. dev_err(&pdev->dev, "io resource mapping failed\n");
  557. ret = PTR_ERR(spicc->base);
  558. goto out_master;
  559. }
  560. /* Set master mode and enable controller */
  561. writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER,
  562. spicc->base + SPICC_CONREG);
  563. /* Disable all IRQs */
  564. writel_relaxed(0, spicc->base + SPICC_INTREG);
  565. irq = platform_get_irq(pdev, 0);
  566. if (irq < 0) {
  567. ret = irq;
  568. goto out_master;
  569. }
  570. ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq,
  571. 0, NULL, spicc);
  572. if (ret) {
  573. dev_err(&pdev->dev, "irq request failed\n");
  574. goto out_master;
  575. }
  576. spicc->core = devm_clk_get(&pdev->dev, "core");
  577. if (IS_ERR(spicc->core)) {
  578. dev_err(&pdev->dev, "core clock request failed\n");
  579. ret = PTR_ERR(spicc->core);
  580. goto out_master;
  581. }
  582. if (spicc->data->has_pclk) {
  583. spicc->pclk = devm_clk_get(&pdev->dev, "pclk");
  584. if (IS_ERR(spicc->pclk)) {
  585. dev_err(&pdev->dev, "pclk clock request failed\n");
  586. ret = PTR_ERR(spicc->pclk);
  587. goto out_master;
  588. }
  589. }
  590. ret = clk_prepare_enable(spicc->core);
  591. if (ret) {
  592. dev_err(&pdev->dev, "core clock enable failed\n");
  593. goto out_master;
  594. }
  595. ret = clk_prepare_enable(spicc->pclk);
  596. if (ret) {
  597. dev_err(&pdev->dev, "pclk clock enable failed\n");
  598. goto out_core_clk;
  599. }
  600. device_reset_optional(&pdev->dev);
  601. master->num_chipselect = 4;
  602. master->dev.of_node = pdev->dev.of_node;
  603. master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH;
  604. master->bits_per_word_mask = SPI_BPW_MASK(32) |
  605. SPI_BPW_MASK(24) |
  606. SPI_BPW_MASK(16) |
  607. SPI_BPW_MASK(8);
  608. master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
  609. master->min_speed_hz = spicc->data->min_speed_hz;
  610. master->max_speed_hz = spicc->data->max_speed_hz;
  611. master->setup = meson_spicc_setup;
  612. master->cleanup = meson_spicc_cleanup;
  613. master->prepare_message = meson_spicc_prepare_message;
  614. master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer;
  615. master->transfer_one = meson_spicc_transfer_one;
  616. master->use_gpio_descriptors = true;
  617. meson_spicc_oen_enable(spicc);
  618. ret = meson_spicc_clk_init(spicc);
  619. if (ret) {
  620. dev_err(&pdev->dev, "clock registration failed\n");
  621. goto out_clk;
  622. }
  623. ret = devm_spi_register_master(&pdev->dev, master);
  624. if (ret) {
  625. dev_err(&pdev->dev, "spi master registration failed\n");
  626. goto out_clk;
  627. }
  628. return 0;
  629. out_clk:
  630. clk_disable_unprepare(spicc->pclk);
  631. out_core_clk:
  632. clk_disable_unprepare(spicc->core);
  633. out_master:
  634. spi_master_put(master);
  635. return ret;
  636. }
  637. static int meson_spicc_remove(struct platform_device *pdev)
  638. {
  639. struct meson_spicc_device *spicc = platform_get_drvdata(pdev);
  640. /* Disable SPI */
  641. writel(0, spicc->base + SPICC_CONREG);
  642. clk_disable_unprepare(spicc->core);
  643. clk_disable_unprepare(spicc->pclk);
  644. spi_master_put(spicc->master);
  645. return 0;
  646. }
  647. static const struct meson_spicc_data meson_spicc_gx_data = {
  648. .max_speed_hz = 30000000,
  649. .min_speed_hz = 325000,
  650. .fifo_size = 16,
  651. };
  652. static const struct meson_spicc_data meson_spicc_axg_data = {
  653. .max_speed_hz = 80000000,
  654. .min_speed_hz = 325000,
  655. .fifo_size = 16,
  656. .has_oen = true,
  657. .has_enhance_clk_div = true,
  658. };
  659. static const struct meson_spicc_data meson_spicc_g12a_data = {
  660. .max_speed_hz = 166666666,
  661. .min_speed_hz = 50000,
  662. .fifo_size = 15,
  663. .has_oen = true,
  664. .has_enhance_clk_div = true,
  665. .has_pclk = true,
  666. };
  667. static const struct of_device_id meson_spicc_of_match[] = {
  668. {
  669. .compatible = "amlogic,meson-gx-spicc",
  670. .data = &meson_spicc_gx_data,
  671. },
  672. {
  673. .compatible = "amlogic,meson-axg-spicc",
  674. .data = &meson_spicc_axg_data,
  675. },
  676. {
  677. .compatible = "amlogic,meson-g12a-spicc",
  678. .data = &meson_spicc_g12a_data,
  679. },
  680. { /* sentinel */ }
  681. };
  682. MODULE_DEVICE_TABLE(of, meson_spicc_of_match);
  683. static struct platform_driver meson_spicc_driver = {
  684. .probe = meson_spicc_probe,
  685. .remove = meson_spicc_remove,
  686. .driver = {
  687. .name = "meson-spicc",
  688. .of_match_table = of_match_ptr(meson_spicc_of_match),
  689. },
  690. };
  691. module_platform_driver(meson_spicc_driver);
  692. MODULE_DESCRIPTION("Meson SPI Communication Controller driver");
  693. MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
  694. MODULE_LICENSE("GPL");