spi-lantiq-ssc.c 28 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
  4. * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
  5. */
  6. #include <linux/kernel.h>
  7. #include <linux/module.h>
  8. #include <linux/of_device.h>
  9. #include <linux/clk.h>
  10. #include <linux/io.h>
  11. #include <linux/delay.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/sched.h>
  14. #include <linux/completion.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/err.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/spi/spi.h>
  19. #ifdef CONFIG_LANTIQ
  20. #include <lantiq_soc.h>
  21. #endif
  22. #define LTQ_SPI_RX_IRQ_NAME "spi_rx"
  23. #define LTQ_SPI_TX_IRQ_NAME "spi_tx"
  24. #define LTQ_SPI_ERR_IRQ_NAME "spi_err"
  25. #define LTQ_SPI_FRM_IRQ_NAME "spi_frm"
  26. #define LTQ_SPI_CLC 0x00
  27. #define LTQ_SPI_PISEL 0x04
  28. #define LTQ_SPI_ID 0x08
  29. #define LTQ_SPI_CON 0x10
  30. #define LTQ_SPI_STAT 0x14
  31. #define LTQ_SPI_WHBSTATE 0x18
  32. #define LTQ_SPI_TB 0x20
  33. #define LTQ_SPI_RB 0x24
  34. #define LTQ_SPI_RXFCON 0x30
  35. #define LTQ_SPI_TXFCON 0x34
  36. #define LTQ_SPI_FSTAT 0x38
  37. #define LTQ_SPI_BRT 0x40
  38. #define LTQ_SPI_BRSTAT 0x44
  39. #define LTQ_SPI_SFCON 0x60
  40. #define LTQ_SPI_SFSTAT 0x64
  41. #define LTQ_SPI_GPOCON 0x70
  42. #define LTQ_SPI_GPOSTAT 0x74
  43. #define LTQ_SPI_FPGO 0x78
  44. #define LTQ_SPI_RXREQ 0x80
  45. #define LTQ_SPI_RXCNT 0x84
  46. #define LTQ_SPI_DMACON 0xec
  47. #define LTQ_SPI_IRNEN 0xf4
  48. #define LTQ_SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */
  49. #define LTQ_SPI_CLC_SMC_M (0xFF << LTQ_SPI_CLC_SMC_S)
  50. #define LTQ_SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */
  51. #define LTQ_SPI_CLC_RMC_M (0xFF << LTQ_SPI_CLC_RMC_S)
  52. #define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */
  53. #define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */
  54. #define LTQ_SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */
  55. #define LTQ_SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */
  56. #define LTQ_SPI_ID_MOD_S 8 /* Module ID */
  57. #define LTQ_SPI_ID_MOD_M (0xff << LTQ_SPI_ID_MOD_S)
  58. #define LTQ_SPI_ID_CFG_S 5 /* DMA interface support */
  59. #define LTQ_SPI_ID_CFG_M (1 << LTQ_SPI_ID_CFG_S)
  60. #define LTQ_SPI_ID_REV_M 0x1F /* Hardware revision number */
  61. #define LTQ_SPI_CON_BM_S 16 /* Data width selection */
  62. #define LTQ_SPI_CON_BM_M (0x1F << LTQ_SPI_CON_BM_S)
  63. #define LTQ_SPI_CON_EM BIT(24) /* Echo mode */
  64. #define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */
  65. #define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */
  66. #define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */
  67. #define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */
  68. #define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */
  69. #define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */
  70. #define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */
  71. #define LTQ_SPI_CON_LB BIT(7) /* Loopback control */
  72. #define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */
  73. #define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */
  74. #define LTQ_SPI_CON_HB BIT(4) /* Heading control */
  75. #define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */
  76. #define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */
  77. #define LTQ_SPI_STAT_RXBV_S 28
  78. #define LTQ_SPI_STAT_RXBV_M (0x7 << LTQ_SPI_STAT_RXBV_S)
  79. #define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */
  80. #define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */
  81. #define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */
  82. #define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */
  83. #define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */
  84. #define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */
  85. #define LTQ_SPI_STAT_ME BIT(7) /* Mode error flag */
  86. #define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */
  87. #define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */
  88. #define LTQ_SPI_STAT_ERRORS (LTQ_SPI_STAT_ME | LTQ_SPI_STAT_TE | \
  89. LTQ_SPI_STAT_RE | LTQ_SPI_STAT_AE | \
  90. LTQ_SPI_STAT_TUE | LTQ_SPI_STAT_RUE)
  91. #define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */
  92. #define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */
  93. #define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */
  94. #define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */
  95. #define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */
  96. #define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */
  97. #define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */
  98. #define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */
  99. #define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */
  100. #define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
  101. #define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */
  102. #define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */
  103. #define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */
  104. #define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */
  105. #define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */
  106. #define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */
  107. #define LTQ_SPI_WHBSTATE_CLR_ERRORS (LTQ_SPI_WHBSTATE_CLRRUE | \
  108. LTQ_SPI_WHBSTATE_CLRME | \
  109. LTQ_SPI_WHBSTATE_CLRTE | \
  110. LTQ_SPI_WHBSTATE_CLRRE | \
  111. LTQ_SPI_WHBSTATE_CLRAE | \
  112. LTQ_SPI_WHBSTATE_CLRTUE)
  113. #define LTQ_SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */
  114. #define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */
  115. #define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */
  116. #define LTQ_SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */
  117. #define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */
  118. #define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */
  119. #define LTQ_SPI_FSTAT_RXFFL_S 0
  120. #define LTQ_SPI_FSTAT_TXFFL_S 8
  121. #define LTQ_SPI_GPOCON_ISCSBN_S 8
  122. #define LTQ_SPI_GPOCON_INVOUTN_S 0
  123. #define LTQ_SPI_FGPO_SETOUTN_S 8
  124. #define LTQ_SPI_FGPO_CLROUTN_S 0
  125. #define LTQ_SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */
  126. #define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */
  127. #define LTQ_SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */
  128. #define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */
  129. #define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */
  130. #define LTQ_SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */
  131. #define LTQ_SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */
  132. #define LTQ_SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */
  133. #define LTQ_SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */
  134. #define LTQ_SPI_IRNEN_ALL 0x1F
  135. struct lantiq_ssc_spi;
  136. struct lantiq_ssc_hwcfg {
  137. int (*cfg_irq)(struct platform_device *pdev, struct lantiq_ssc_spi *spi);
  138. unsigned int irnen_r;
  139. unsigned int irnen_t;
  140. unsigned int irncr;
  141. unsigned int irnicr;
  142. bool irq_ack;
  143. u32 fifo_size_mask;
  144. };
  145. struct lantiq_ssc_spi {
  146. struct spi_master *master;
  147. struct device *dev;
  148. void __iomem *regbase;
  149. struct clk *spi_clk;
  150. struct clk *fpi_clk;
  151. const struct lantiq_ssc_hwcfg *hwcfg;
  152. spinlock_t lock;
  153. struct workqueue_struct *wq;
  154. struct work_struct work;
  155. const u8 *tx;
  156. u8 *rx;
  157. unsigned int tx_todo;
  158. unsigned int rx_todo;
  159. unsigned int bits_per_word;
  160. unsigned int speed_hz;
  161. unsigned int tx_fifo_size;
  162. unsigned int rx_fifo_size;
  163. unsigned int base_cs;
  164. unsigned int fdx_tx_level;
  165. };
  166. static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg)
  167. {
  168. return __raw_readl(spi->regbase + reg);
  169. }
  170. static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val,
  171. u32 reg)
  172. {
  173. __raw_writel(val, spi->regbase + reg);
  174. }
  175. static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr,
  176. u32 set, u32 reg)
  177. {
  178. u32 val = __raw_readl(spi->regbase + reg);
  179. val &= ~clr;
  180. val |= set;
  181. __raw_writel(val, spi->regbase + reg);
  182. }
  183. static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi)
  184. {
  185. const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
  186. u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
  187. return (fstat >> LTQ_SPI_FSTAT_TXFFL_S) & hwcfg->fifo_size_mask;
  188. }
  189. static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi)
  190. {
  191. const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
  192. u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
  193. return (fstat >> LTQ_SPI_FSTAT_RXFFL_S) & hwcfg->fifo_size_mask;
  194. }
  195. static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi)
  196. {
  197. return spi->tx_fifo_size - tx_fifo_level(spi);
  198. }
  199. static void rx_fifo_reset(const struct lantiq_ssc_spi *spi)
  200. {
  201. u32 val = spi->rx_fifo_size << LTQ_SPI_RXFCON_RXFITL_S;
  202. val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;
  203. lantiq_ssc_writel(spi, val, LTQ_SPI_RXFCON);
  204. }
  205. static void tx_fifo_reset(const struct lantiq_ssc_spi *spi)
  206. {
  207. u32 val = 1 << LTQ_SPI_TXFCON_TXFITL_S;
  208. val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;
  209. lantiq_ssc_writel(spi, val, LTQ_SPI_TXFCON);
  210. }
  211. static void rx_fifo_flush(const struct lantiq_ssc_spi *spi)
  212. {
  213. lantiq_ssc_maskl(spi, 0, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
  214. }
  215. static void tx_fifo_flush(const struct lantiq_ssc_spi *spi)
  216. {
  217. lantiq_ssc_maskl(spi, 0, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
  218. }
  219. static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi)
  220. {
  221. lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
  222. }
  223. static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi)
  224. {
  225. lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
  226. }
  227. static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi,
  228. unsigned int max_speed_hz)
  229. {
  230. u32 spi_clk, brt;
  231. /*
  232. * SPI module clock is derived from FPI bus clock dependent on
  233. * divider value in CLC.RMS which is always set to 1.
  234. *
  235. * f_SPI
  236. * baudrate = --------------
  237. * 2 * (BR + 1)
  238. */
  239. spi_clk = clk_get_rate(spi->fpi_clk) / 2;
  240. if (max_speed_hz > spi_clk)
  241. brt = 0;
  242. else
  243. brt = spi_clk / max_speed_hz - 1;
  244. if (brt > 0xFFFF)
  245. brt = 0xFFFF;
  246. dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n",
  247. spi_clk, max_speed_hz, brt);
  248. lantiq_ssc_writel(spi, brt, LTQ_SPI_BRT);
  249. }
  250. static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi,
  251. unsigned int bits_per_word)
  252. {
  253. u32 bm;
  254. /* CON.BM value = bits_per_word - 1 */
  255. bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_S;
  256. lantiq_ssc_maskl(spi, LTQ_SPI_CON_BM_M, bm, LTQ_SPI_CON);
  257. }
  258. static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi,
  259. unsigned int mode)
  260. {
  261. u32 con_set = 0, con_clr = 0;
  262. /*
  263. * SPI mode mapping in CON register:
  264. * Mode CPOL CPHA CON.PO CON.PH
  265. * 0 0 0 0 1
  266. * 1 0 1 0 0
  267. * 2 1 0 1 1
  268. * 3 1 1 1 0
  269. */
  270. if (mode & SPI_CPHA)
  271. con_clr |= LTQ_SPI_CON_PH;
  272. else
  273. con_set |= LTQ_SPI_CON_PH;
  274. if (mode & SPI_CPOL)
  275. con_set |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE;
  276. else
  277. con_clr |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE;
  278. /* Set heading control */
  279. if (mode & SPI_LSB_FIRST)
  280. con_clr |= LTQ_SPI_CON_HB;
  281. else
  282. con_set |= LTQ_SPI_CON_HB;
  283. /* Set loopback mode */
  284. if (mode & SPI_LOOP)
  285. con_set |= LTQ_SPI_CON_LB;
  286. else
  287. con_clr |= LTQ_SPI_CON_LB;
  288. lantiq_ssc_maskl(spi, con_clr, con_set, LTQ_SPI_CON);
  289. }
  290. static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi)
  291. {
  292. const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
  293. /*
  294. * Set clock divider for run mode to 1 to
  295. * run at same frequency as FPI bus
  296. */
  297. lantiq_ssc_writel(spi, 1 << LTQ_SPI_CLC_RMC_S, LTQ_SPI_CLC);
  298. /* Put controller into config mode */
  299. hw_enter_config_mode(spi);
  300. /* Clear error flags */
  301. lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
  302. /* Enable error checking, disable TX/RX */
  303. lantiq_ssc_writel(spi, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
  304. LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | LTQ_SPI_CON_TXOFF |
  305. LTQ_SPI_CON_RXOFF, LTQ_SPI_CON);
  306. /* Setup default SPI mode */
  307. hw_setup_bits_per_word(spi, spi->bits_per_word);
  308. hw_setup_clock_mode(spi, SPI_MODE_0);
  309. /* Enable master mode and clear error flags */
  310. lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETMS |
  311. LTQ_SPI_WHBSTATE_CLR_ERRORS,
  312. LTQ_SPI_WHBSTATE);
  313. /* Reset GPIO/CS registers */
  314. lantiq_ssc_writel(spi, 0, LTQ_SPI_GPOCON);
  315. lantiq_ssc_writel(spi, 0xFF00, LTQ_SPI_FPGO);
  316. /* Enable and flush FIFOs */
  317. rx_fifo_reset(spi);
  318. tx_fifo_reset(spi);
  319. /* Enable interrupts */
  320. lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r |
  321. LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN);
  322. }
  323. static int lantiq_ssc_setup(struct spi_device *spidev)
  324. {
  325. struct spi_master *master = spidev->master;
  326. struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
  327. unsigned int cs = spidev->chip_select;
  328. u32 gpocon;
  329. /* GPIOs are used for CS */
  330. if (spidev->cs_gpiod)
  331. return 0;
  332. dev_dbg(spi->dev, "using internal chipselect %u\n", cs);
  333. if (cs < spi->base_cs) {
  334. dev_err(spi->dev,
  335. "chipselect %i too small (min %i)\n", cs, spi->base_cs);
  336. return -EINVAL;
  337. }
  338. /* set GPO pin to CS mode */
  339. gpocon = 1 << ((cs - spi->base_cs) + LTQ_SPI_GPOCON_ISCSBN_S);
  340. /* invert GPO pin */
  341. if (spidev->mode & SPI_CS_HIGH)
  342. gpocon |= 1 << (cs - spi->base_cs);
  343. lantiq_ssc_maskl(spi, 0, gpocon, LTQ_SPI_GPOCON);
  344. return 0;
  345. }
  346. static int lantiq_ssc_prepare_message(struct spi_master *master,
  347. struct spi_message *message)
  348. {
  349. struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
  350. hw_enter_config_mode(spi);
  351. hw_setup_clock_mode(spi, message->spi->mode);
  352. hw_enter_active_mode(spi);
  353. return 0;
  354. }
  355. static void hw_setup_transfer(struct lantiq_ssc_spi *spi,
  356. struct spi_device *spidev, struct spi_transfer *t)
  357. {
  358. unsigned int speed_hz = t->speed_hz;
  359. unsigned int bits_per_word = t->bits_per_word;
  360. u32 con;
  361. if (bits_per_word != spi->bits_per_word ||
  362. speed_hz != spi->speed_hz) {
  363. hw_enter_config_mode(spi);
  364. hw_setup_speed_hz(spi, speed_hz);
  365. hw_setup_bits_per_word(spi, bits_per_word);
  366. hw_enter_active_mode(spi);
  367. spi->speed_hz = speed_hz;
  368. spi->bits_per_word = bits_per_word;
  369. }
  370. /* Configure transmitter and receiver */
  371. con = lantiq_ssc_readl(spi, LTQ_SPI_CON);
  372. if (t->tx_buf)
  373. con &= ~LTQ_SPI_CON_TXOFF;
  374. else
  375. con |= LTQ_SPI_CON_TXOFF;
  376. if (t->rx_buf)
  377. con &= ~LTQ_SPI_CON_RXOFF;
  378. else
  379. con |= LTQ_SPI_CON_RXOFF;
  380. lantiq_ssc_writel(spi, con, LTQ_SPI_CON);
  381. }
  382. static int lantiq_ssc_unprepare_message(struct spi_master *master,
  383. struct spi_message *message)
  384. {
  385. struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
  386. flush_workqueue(spi->wq);
  387. /* Disable transmitter and receiver while idle */
  388. lantiq_ssc_maskl(spi, 0, LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF,
  389. LTQ_SPI_CON);
  390. return 0;
  391. }
  392. static void tx_fifo_write(struct lantiq_ssc_spi *spi)
  393. {
  394. const u8 *tx8;
  395. const u16 *tx16;
  396. const u32 *tx32;
  397. u32 data;
  398. unsigned int tx_free = tx_fifo_free(spi);
  399. spi->fdx_tx_level = 0;
  400. while (spi->tx_todo && tx_free) {
  401. switch (spi->bits_per_word) {
  402. case 2 ... 8:
  403. tx8 = spi->tx;
  404. data = *tx8;
  405. spi->tx_todo--;
  406. spi->tx++;
  407. break;
  408. case 16:
  409. tx16 = (u16 *) spi->tx;
  410. data = *tx16;
  411. spi->tx_todo -= 2;
  412. spi->tx += 2;
  413. break;
  414. case 32:
  415. tx32 = (u32 *) spi->tx;
  416. data = *tx32;
  417. spi->tx_todo -= 4;
  418. spi->tx += 4;
  419. break;
  420. default:
  421. WARN_ON(1);
  422. data = 0;
  423. break;
  424. }
  425. lantiq_ssc_writel(spi, data, LTQ_SPI_TB);
  426. tx_free--;
  427. spi->fdx_tx_level++;
  428. }
  429. }
  430. static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi)
  431. {
  432. u8 *rx8;
  433. u16 *rx16;
  434. u32 *rx32;
  435. u32 data;
  436. unsigned int rx_fill = rx_fifo_level(spi);
  437. /*
  438. * Wait until all expected data to be shifted in.
  439. * Otherwise, rx overrun may occur.
  440. */
  441. while (rx_fill != spi->fdx_tx_level)
  442. rx_fill = rx_fifo_level(spi);
  443. while (rx_fill) {
  444. data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
  445. switch (spi->bits_per_word) {
  446. case 2 ... 8:
  447. rx8 = spi->rx;
  448. *rx8 = data;
  449. spi->rx_todo--;
  450. spi->rx++;
  451. break;
  452. case 16:
  453. rx16 = (u16 *) spi->rx;
  454. *rx16 = data;
  455. spi->rx_todo -= 2;
  456. spi->rx += 2;
  457. break;
  458. case 32:
  459. rx32 = (u32 *) spi->rx;
  460. *rx32 = data;
  461. spi->rx_todo -= 4;
  462. spi->rx += 4;
  463. break;
  464. default:
  465. WARN_ON(1);
  466. break;
  467. }
  468. rx_fill--;
  469. }
  470. }
  471. static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi)
  472. {
  473. u32 data, *rx32;
  474. u8 *rx8;
  475. unsigned int rxbv, shift;
  476. unsigned int rx_fill = rx_fifo_level(spi);
  477. /*
  478. * In RX-only mode the bits per word value is ignored by HW. A value
  479. * of 32 is used instead. Thus all 4 bytes per FIFO must be read.
  480. * If remaining RX bytes are less than 4, the FIFO must be read
  481. * differently. The amount of received and valid bytes is indicated
  482. * by STAT.RXBV register value.
  483. */
  484. while (rx_fill) {
  485. if (spi->rx_todo < 4) {
  486. rxbv = (lantiq_ssc_readl(spi, LTQ_SPI_STAT) &
  487. LTQ_SPI_STAT_RXBV_M) >> LTQ_SPI_STAT_RXBV_S;
  488. data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
  489. shift = (rxbv - 1) * 8;
  490. rx8 = spi->rx;
  491. while (rxbv) {
  492. *rx8++ = (data >> shift) & 0xFF;
  493. rxbv--;
  494. shift -= 8;
  495. spi->rx_todo--;
  496. spi->rx++;
  497. }
  498. } else {
  499. data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
  500. rx32 = (u32 *) spi->rx;
  501. *rx32++ = data;
  502. spi->rx_todo -= 4;
  503. spi->rx += 4;
  504. }
  505. rx_fill--;
  506. }
  507. }
  508. static void rx_request(struct lantiq_ssc_spi *spi)
  509. {
  510. unsigned int rxreq, rxreq_max;
  511. /*
  512. * To avoid receive overflows at high clocks it is better to request
  513. * only the amount of bytes that fits into all FIFOs. This value
  514. * depends on the FIFO size implemented in hardware.
  515. */
  516. rxreq = spi->rx_todo;
  517. rxreq_max = spi->rx_fifo_size * 4;
  518. if (rxreq > rxreq_max)
  519. rxreq = rxreq_max;
  520. lantiq_ssc_writel(spi, rxreq, LTQ_SPI_RXREQ);
  521. }
  522. static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data)
  523. {
  524. struct lantiq_ssc_spi *spi = data;
  525. const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
  526. u32 val = lantiq_ssc_readl(spi, hwcfg->irncr);
  527. spin_lock(&spi->lock);
  528. if (hwcfg->irq_ack)
  529. lantiq_ssc_writel(spi, val, hwcfg->irncr);
  530. if (spi->tx) {
  531. if (spi->rx && spi->rx_todo)
  532. rx_fifo_read_full_duplex(spi);
  533. if (spi->tx_todo)
  534. tx_fifo_write(spi);
  535. else if (!tx_fifo_level(spi))
  536. goto completed;
  537. } else if (spi->rx) {
  538. if (spi->rx_todo) {
  539. rx_fifo_read_half_duplex(spi);
  540. if (spi->rx_todo)
  541. rx_request(spi);
  542. else
  543. goto completed;
  544. } else {
  545. goto completed;
  546. }
  547. }
  548. spin_unlock(&spi->lock);
  549. return IRQ_HANDLED;
  550. completed:
  551. queue_work(spi->wq, &spi->work);
  552. spin_unlock(&spi->lock);
  553. return IRQ_HANDLED;
  554. }
  555. static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data)
  556. {
  557. struct lantiq_ssc_spi *spi = data;
  558. const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
  559. u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
  560. u32 val = lantiq_ssc_readl(spi, hwcfg->irncr);
  561. if (!(stat & LTQ_SPI_STAT_ERRORS))
  562. return IRQ_NONE;
  563. spin_lock(&spi->lock);
  564. if (hwcfg->irq_ack)
  565. lantiq_ssc_writel(spi, val, hwcfg->irncr);
  566. if (stat & LTQ_SPI_STAT_RUE)
  567. dev_err(spi->dev, "receive underflow error\n");
  568. if (stat & LTQ_SPI_STAT_TUE)
  569. dev_err(spi->dev, "transmit underflow error\n");
  570. if (stat & LTQ_SPI_STAT_AE)
  571. dev_err(spi->dev, "abort error\n");
  572. if (stat & LTQ_SPI_STAT_RE)
  573. dev_err(spi->dev, "receive overflow error\n");
  574. if (stat & LTQ_SPI_STAT_TE)
  575. dev_err(spi->dev, "transmit overflow error\n");
  576. if (stat & LTQ_SPI_STAT_ME)
  577. dev_err(spi->dev, "mode error\n");
  578. /* Clear error flags */
  579. lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
  580. /* set bad status so it can be retried */
  581. if (spi->master->cur_msg)
  582. spi->master->cur_msg->status = -EIO;
  583. queue_work(spi->wq, &spi->work);
  584. spin_unlock(&spi->lock);
  585. return IRQ_HANDLED;
  586. }
  587. static irqreturn_t intel_lgm_ssc_isr(int irq, void *data)
  588. {
  589. struct lantiq_ssc_spi *spi = data;
  590. const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
  591. u32 val = lantiq_ssc_readl(spi, hwcfg->irncr);
  592. if (!(val & LTQ_SPI_IRNEN_ALL))
  593. return IRQ_NONE;
  594. if (val & LTQ_SPI_IRNEN_E)
  595. return lantiq_ssc_err_interrupt(irq, data);
  596. if ((val & hwcfg->irnen_t) || (val & hwcfg->irnen_r))
  597. return lantiq_ssc_xmit_interrupt(irq, data);
  598. return IRQ_HANDLED;
  599. }
  600. static int transfer_start(struct lantiq_ssc_spi *spi, struct spi_device *spidev,
  601. struct spi_transfer *t)
  602. {
  603. unsigned long flags;
  604. spin_lock_irqsave(&spi->lock, flags);
  605. spi->tx = t->tx_buf;
  606. spi->rx = t->rx_buf;
  607. if (t->tx_buf) {
  608. spi->tx_todo = t->len;
  609. /* initially fill TX FIFO */
  610. tx_fifo_write(spi);
  611. }
  612. if (spi->rx) {
  613. spi->rx_todo = t->len;
  614. /* start shift clock in RX-only mode */
  615. if (!spi->tx)
  616. rx_request(spi);
  617. }
  618. spin_unlock_irqrestore(&spi->lock, flags);
  619. return t->len;
  620. }
  621. /*
  622. * The driver only gets an interrupt when the FIFO is empty, but there
  623. * is an additional shift register from which the data is written to
  624. * the wire. We get the last interrupt when the controller starts to
  625. * write the last word to the wire, not when it is finished. Do busy
  626. * waiting till it finishes.
  627. */
  628. static void lantiq_ssc_bussy_work(struct work_struct *work)
  629. {
  630. struct lantiq_ssc_spi *spi;
  631. unsigned long long timeout = 8LL * 1000LL;
  632. unsigned long end;
  633. spi = container_of(work, typeof(*spi), work);
  634. do_div(timeout, spi->speed_hz);
  635. timeout += timeout + 100; /* some tolerance */
  636. end = jiffies + msecs_to_jiffies(timeout);
  637. do {
  638. u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
  639. if (!(stat & LTQ_SPI_STAT_BSY)) {
  640. spi_finalize_current_transfer(spi->master);
  641. return;
  642. }
  643. cond_resched();
  644. } while (!time_after_eq(jiffies, end));
  645. if (spi->master->cur_msg)
  646. spi->master->cur_msg->status = -EIO;
  647. spi_finalize_current_transfer(spi->master);
  648. }
  649. static void lantiq_ssc_handle_err(struct spi_master *master,
  650. struct spi_message *message)
  651. {
  652. struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
  653. /* flush FIFOs on timeout */
  654. rx_fifo_flush(spi);
  655. tx_fifo_flush(spi);
  656. }
  657. static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable)
  658. {
  659. struct lantiq_ssc_spi *spi = spi_master_get_devdata(spidev->master);
  660. unsigned int cs = spidev->chip_select;
  661. u32 fgpo;
  662. if (!!(spidev->mode & SPI_CS_HIGH) == enable)
  663. fgpo = (1 << (cs - spi->base_cs));
  664. else
  665. fgpo = (1 << (cs - spi->base_cs + LTQ_SPI_FGPO_SETOUTN_S));
  666. lantiq_ssc_writel(spi, fgpo, LTQ_SPI_FPGO);
  667. }
  668. static int lantiq_ssc_transfer_one(struct spi_master *master,
  669. struct spi_device *spidev,
  670. struct spi_transfer *t)
  671. {
  672. struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
  673. hw_setup_transfer(spi, spidev, t);
  674. return transfer_start(spi, spidev, t);
  675. }
  676. static int intel_lgm_cfg_irq(struct platform_device *pdev, struct lantiq_ssc_spi *spi)
  677. {
  678. int irq;
  679. irq = platform_get_irq(pdev, 0);
  680. if (irq < 0)
  681. return irq;
  682. return devm_request_irq(&pdev->dev, irq, intel_lgm_ssc_isr, 0, "spi", spi);
  683. }
  684. static int lantiq_cfg_irq(struct platform_device *pdev, struct lantiq_ssc_spi *spi)
  685. {
  686. int irq, err;
  687. irq = platform_get_irq_byname(pdev, LTQ_SPI_RX_IRQ_NAME);
  688. if (irq < 0)
  689. return irq;
  690. err = devm_request_irq(&pdev->dev, irq, lantiq_ssc_xmit_interrupt,
  691. 0, LTQ_SPI_RX_IRQ_NAME, spi);
  692. if (err)
  693. return err;
  694. irq = platform_get_irq_byname(pdev, LTQ_SPI_TX_IRQ_NAME);
  695. if (irq < 0)
  696. return irq;
  697. err = devm_request_irq(&pdev->dev, irq, lantiq_ssc_xmit_interrupt,
  698. 0, LTQ_SPI_TX_IRQ_NAME, spi);
  699. if (err)
  700. return err;
  701. irq = platform_get_irq_byname(pdev, LTQ_SPI_ERR_IRQ_NAME);
  702. if (irq < 0)
  703. return irq;
  704. err = devm_request_irq(&pdev->dev, irq, lantiq_ssc_err_interrupt,
  705. 0, LTQ_SPI_ERR_IRQ_NAME, spi);
  706. return err;
  707. }
  708. static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
  709. .cfg_irq = lantiq_cfg_irq,
  710. .irnen_r = LTQ_SPI_IRNEN_R_XWAY,
  711. .irnen_t = LTQ_SPI_IRNEN_T_XWAY,
  712. .irnicr = 0xF8,
  713. .irncr = 0xFC,
  714. .fifo_size_mask = GENMASK(5, 0),
  715. .irq_ack = false,
  716. };
  717. static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
  718. .cfg_irq = lantiq_cfg_irq,
  719. .irnen_r = LTQ_SPI_IRNEN_R_XRX,
  720. .irnen_t = LTQ_SPI_IRNEN_T_XRX,
  721. .irnicr = 0xF8,
  722. .irncr = 0xFC,
  723. .fifo_size_mask = GENMASK(5, 0),
  724. .irq_ack = false,
  725. };
  726. static const struct lantiq_ssc_hwcfg intel_ssc_lgm = {
  727. .cfg_irq = intel_lgm_cfg_irq,
  728. .irnen_r = LTQ_SPI_IRNEN_R_XRX,
  729. .irnen_t = LTQ_SPI_IRNEN_T_XRX,
  730. .irnicr = 0xFC,
  731. .irncr = 0xF8,
  732. .fifo_size_mask = GENMASK(7, 0),
  733. .irq_ack = true,
  734. };
  735. static const struct of_device_id lantiq_ssc_match[] = {
  736. { .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, },
  737. { .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, },
  738. { .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, },
  739. { .compatible = "intel,lgm-spi", .data = &intel_ssc_lgm, },
  740. {},
  741. };
  742. MODULE_DEVICE_TABLE(of, lantiq_ssc_match);
  743. static int lantiq_ssc_probe(struct platform_device *pdev)
  744. {
  745. struct device *dev = &pdev->dev;
  746. struct spi_master *master;
  747. struct lantiq_ssc_spi *spi;
  748. const struct lantiq_ssc_hwcfg *hwcfg;
  749. const struct of_device_id *match;
  750. u32 id, supports_dma, revision;
  751. unsigned int num_cs;
  752. int err;
  753. match = of_match_device(lantiq_ssc_match, dev);
  754. if (!match) {
  755. dev_err(dev, "no device match\n");
  756. return -EINVAL;
  757. }
  758. hwcfg = match->data;
  759. master = spi_alloc_master(dev, sizeof(struct lantiq_ssc_spi));
  760. if (!master)
  761. return -ENOMEM;
  762. spi = spi_master_get_devdata(master);
  763. spi->master = master;
  764. spi->dev = dev;
  765. spi->hwcfg = hwcfg;
  766. platform_set_drvdata(pdev, spi);
  767. spi->regbase = devm_platform_ioremap_resource(pdev, 0);
  768. if (IS_ERR(spi->regbase)) {
  769. err = PTR_ERR(spi->regbase);
  770. goto err_master_put;
  771. }
  772. err = hwcfg->cfg_irq(pdev, spi);
  773. if (err)
  774. goto err_master_put;
  775. spi->spi_clk = devm_clk_get(dev, "gate");
  776. if (IS_ERR(spi->spi_clk)) {
  777. err = PTR_ERR(spi->spi_clk);
  778. goto err_master_put;
  779. }
  780. err = clk_prepare_enable(spi->spi_clk);
  781. if (err)
  782. goto err_master_put;
  783. /*
  784. * Use the old clk_get_fpi() function on Lantiq platform, till it
  785. * supports common clk.
  786. */
  787. #if defined(CONFIG_LANTIQ) && !defined(CONFIG_COMMON_CLK)
  788. spi->fpi_clk = clk_get_fpi();
  789. #else
  790. spi->fpi_clk = clk_get(dev, "freq");
  791. #endif
  792. if (IS_ERR(spi->fpi_clk)) {
  793. err = PTR_ERR(spi->fpi_clk);
  794. goto err_clk_disable;
  795. }
  796. num_cs = 8;
  797. of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
  798. spi->base_cs = 1;
  799. of_property_read_u32(pdev->dev.of_node, "base-cs", &spi->base_cs);
  800. spin_lock_init(&spi->lock);
  801. spi->bits_per_word = 8;
  802. spi->speed_hz = 0;
  803. master->dev.of_node = pdev->dev.of_node;
  804. master->num_chipselect = num_cs;
  805. master->use_gpio_descriptors = true;
  806. master->setup = lantiq_ssc_setup;
  807. master->set_cs = lantiq_ssc_set_cs;
  808. master->handle_err = lantiq_ssc_handle_err;
  809. master->prepare_message = lantiq_ssc_prepare_message;
  810. master->unprepare_message = lantiq_ssc_unprepare_message;
  811. master->transfer_one = lantiq_ssc_transfer_one;
  812. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH |
  813. SPI_LOOP;
  814. master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 8) |
  815. SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
  816. spi->wq = alloc_ordered_workqueue(dev_name(dev), WQ_MEM_RECLAIM);
  817. if (!spi->wq) {
  818. err = -ENOMEM;
  819. goto err_clk_put;
  820. }
  821. INIT_WORK(&spi->work, lantiq_ssc_bussy_work);
  822. id = lantiq_ssc_readl(spi, LTQ_SPI_ID);
  823. spi->tx_fifo_size = (id >> LTQ_SPI_ID_TXFS_S) & hwcfg->fifo_size_mask;
  824. spi->rx_fifo_size = (id >> LTQ_SPI_ID_RXFS_S) & hwcfg->fifo_size_mask;
  825. supports_dma = (id & LTQ_SPI_ID_CFG_M) >> LTQ_SPI_ID_CFG_S;
  826. revision = id & LTQ_SPI_ID_REV_M;
  827. lantiq_ssc_hw_init(spi);
  828. dev_info(dev,
  829. "Lantiq SSC SPI controller (Rev %i, TXFS %u, RXFS %u, DMA %u)\n",
  830. revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma);
  831. err = devm_spi_register_master(dev, master);
  832. if (err) {
  833. dev_err(dev, "failed to register spi_master\n");
  834. goto err_wq_destroy;
  835. }
  836. return 0;
  837. err_wq_destroy:
  838. destroy_workqueue(spi->wq);
  839. err_clk_put:
  840. clk_put(spi->fpi_clk);
  841. err_clk_disable:
  842. clk_disable_unprepare(spi->spi_clk);
  843. err_master_put:
  844. spi_master_put(master);
  845. return err;
  846. }
  847. static int lantiq_ssc_remove(struct platform_device *pdev)
  848. {
  849. struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev);
  850. lantiq_ssc_writel(spi, 0, LTQ_SPI_IRNEN);
  851. lantiq_ssc_writel(spi, 0, LTQ_SPI_CLC);
  852. rx_fifo_flush(spi);
  853. tx_fifo_flush(spi);
  854. hw_enter_config_mode(spi);
  855. destroy_workqueue(spi->wq);
  856. clk_disable_unprepare(spi->spi_clk);
  857. clk_put(spi->fpi_clk);
  858. return 0;
  859. }
  860. static struct platform_driver lantiq_ssc_driver = {
  861. .probe = lantiq_ssc_probe,
  862. .remove = lantiq_ssc_remove,
  863. .driver = {
  864. .name = "spi-lantiq-ssc",
  865. .of_match_table = lantiq_ssc_match,
  866. },
  867. };
  868. module_platform_driver(lantiq_ssc_driver);
  869. MODULE_DESCRIPTION("Lantiq SSC SPI controller driver");
  870. MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@gmail.com>");
  871. MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
  872. MODULE_LICENSE("GPL");
  873. MODULE_ALIAS("platform:spi-lantiq-ssc");