spi-imx.c 47 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  3. // Copyright (C) 2008 Juergen Beisert
  4. #include <linux/clk.h>
  5. #include <linux/completion.h>
  6. #include <linux/delay.h>
  7. #include <linux/dmaengine.h>
  8. #include <linux/dma-mapping.h>
  9. #include <linux/err.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/io.h>
  12. #include <linux/irq.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/pinctrl/consumer.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/slab.h>
  19. #include <linux/spi/spi.h>
  20. #include <linux/spi/spi_bitbang.h>
  21. #include <linux/types.h>
  22. #include <linux/of.h>
  23. #include <linux/of_device.h>
  24. #include <linux/property.h>
  25. #include <linux/platform_data/dma-imx.h>
  26. #define DRIVER_NAME "spi_imx"
  27. static bool use_dma = true;
  28. module_param(use_dma, bool, 0644);
  29. MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
  30. #define MXC_RPM_TIMEOUT 2000 /* 2000ms */
  31. #define MXC_CSPIRXDATA 0x00
  32. #define MXC_CSPITXDATA 0x04
  33. #define MXC_CSPICTRL 0x08
  34. #define MXC_CSPIINT 0x0c
  35. #define MXC_RESET 0x1c
  36. /* generic defines to abstract from the different register layouts */
  37. #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
  38. #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
  39. #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */
  40. /* The maximum bytes that a sdma BD can transfer. */
  41. #define MAX_SDMA_BD_BYTES (1 << 15)
  42. #define MX51_ECSPI_CTRL_MAX_BURST 512
  43. /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
  44. #define MX53_MAX_TRANSFER_BYTES 512
  45. enum spi_imx_devtype {
  46. IMX1_CSPI,
  47. IMX21_CSPI,
  48. IMX27_CSPI,
  49. IMX31_CSPI,
  50. IMX35_CSPI, /* CSPI on all i.mx except above */
  51. IMX51_ECSPI, /* ECSPI on i.mx51 */
  52. IMX53_ECSPI, /* ECSPI on i.mx53 and later */
  53. };
  54. struct spi_imx_data;
  55. struct spi_imx_devtype_data {
  56. void (*intctrl)(struct spi_imx_data *, int);
  57. int (*prepare_message)(struct spi_imx_data *, struct spi_message *);
  58. int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *);
  59. void (*trigger)(struct spi_imx_data *);
  60. int (*rx_available)(struct spi_imx_data *);
  61. void (*reset)(struct spi_imx_data *);
  62. void (*setup_wml)(struct spi_imx_data *);
  63. void (*disable)(struct spi_imx_data *);
  64. void (*disable_dma)(struct spi_imx_data *);
  65. bool has_dmamode;
  66. bool has_slavemode;
  67. unsigned int fifo_size;
  68. bool dynamic_burst;
  69. enum spi_imx_devtype devtype;
  70. };
  71. struct spi_imx_data {
  72. struct spi_bitbang bitbang;
  73. struct device *dev;
  74. struct completion xfer_done;
  75. void __iomem *base;
  76. unsigned long base_phys;
  77. struct clk *clk_per;
  78. struct clk *clk_ipg;
  79. unsigned long spi_clk;
  80. unsigned int spi_bus_clk;
  81. unsigned int bits_per_word;
  82. unsigned int spi_drctl;
  83. unsigned int count, remainder;
  84. void (*tx)(struct spi_imx_data *);
  85. void (*rx)(struct spi_imx_data *);
  86. void *rx_buf;
  87. const void *tx_buf;
  88. unsigned int txfifo; /* number of words pushed in tx FIFO */
  89. unsigned int dynamic_burst;
  90. /* Slave mode */
  91. bool slave_mode;
  92. bool slave_aborted;
  93. unsigned int slave_burst;
  94. /* DMA */
  95. bool usedma;
  96. u32 wml;
  97. struct completion dma_rx_completion;
  98. struct completion dma_tx_completion;
  99. const struct spi_imx_devtype_data *devtype_data;
  100. };
  101. static inline int is_imx27_cspi(struct spi_imx_data *d)
  102. {
  103. return d->devtype_data->devtype == IMX27_CSPI;
  104. }
  105. static inline int is_imx35_cspi(struct spi_imx_data *d)
  106. {
  107. return d->devtype_data->devtype == IMX35_CSPI;
  108. }
  109. static inline int is_imx51_ecspi(struct spi_imx_data *d)
  110. {
  111. return d->devtype_data->devtype == IMX51_ECSPI;
  112. }
  113. static inline int is_imx53_ecspi(struct spi_imx_data *d)
  114. {
  115. return d->devtype_data->devtype == IMX53_ECSPI;
  116. }
  117. #define MXC_SPI_BUF_RX(type) \
  118. static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
  119. { \
  120. unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
  121. \
  122. if (spi_imx->rx_buf) { \
  123. *(type *)spi_imx->rx_buf = val; \
  124. spi_imx->rx_buf += sizeof(type); \
  125. } \
  126. \
  127. spi_imx->remainder -= sizeof(type); \
  128. }
  129. #define MXC_SPI_BUF_TX(type) \
  130. static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
  131. { \
  132. type val = 0; \
  133. \
  134. if (spi_imx->tx_buf) { \
  135. val = *(type *)spi_imx->tx_buf; \
  136. spi_imx->tx_buf += sizeof(type); \
  137. } \
  138. \
  139. spi_imx->count -= sizeof(type); \
  140. \
  141. writel(val, spi_imx->base + MXC_CSPITXDATA); \
  142. }
  143. MXC_SPI_BUF_RX(u8)
  144. MXC_SPI_BUF_TX(u8)
  145. MXC_SPI_BUF_RX(u16)
  146. MXC_SPI_BUF_TX(u16)
  147. MXC_SPI_BUF_RX(u32)
  148. MXC_SPI_BUF_TX(u32)
  149. /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
  150. * (which is currently not the case in this driver)
  151. */
  152. static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
  153. 256, 384, 512, 768, 1024};
  154. /* MX21, MX27 */
  155. static unsigned int spi_imx_clkdiv_1(unsigned int fin,
  156. unsigned int fspi, unsigned int max, unsigned int *fres)
  157. {
  158. int i;
  159. for (i = 2; i < max; i++)
  160. if (fspi * mxc_clkdivs[i] >= fin)
  161. break;
  162. *fres = fin / mxc_clkdivs[i];
  163. return i;
  164. }
  165. /* MX1, MX31, MX35, MX51 CSPI */
  166. static unsigned int spi_imx_clkdiv_2(unsigned int fin,
  167. unsigned int fspi, unsigned int *fres)
  168. {
  169. int i, div = 4;
  170. for (i = 0; i < 7; i++) {
  171. if (fspi * div >= fin)
  172. goto out;
  173. div <<= 1;
  174. }
  175. out:
  176. *fres = fin / div;
  177. return i;
  178. }
  179. static int spi_imx_bytes_per_word(const int bits_per_word)
  180. {
  181. if (bits_per_word <= 8)
  182. return 1;
  183. else if (bits_per_word <= 16)
  184. return 2;
  185. else
  186. return 4;
  187. }
  188. static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
  189. struct spi_transfer *transfer)
  190. {
  191. struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
  192. if (!use_dma || master->fallback)
  193. return false;
  194. if (!master->dma_rx)
  195. return false;
  196. if (spi_imx->slave_mode)
  197. return false;
  198. if (transfer->len < spi_imx->devtype_data->fifo_size)
  199. return false;
  200. spi_imx->dynamic_burst = 0;
  201. return true;
  202. }
  203. #define MX51_ECSPI_CTRL 0x08
  204. #define MX51_ECSPI_CTRL_ENABLE (1 << 0)
  205. #define MX51_ECSPI_CTRL_XCH (1 << 2)
  206. #define MX51_ECSPI_CTRL_SMC (1 << 3)
  207. #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
  208. #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
  209. #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
  210. #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
  211. #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
  212. #define MX51_ECSPI_CTRL_BL_OFFSET 20
  213. #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
  214. #define MX51_ECSPI_CONFIG 0x0c
  215. #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
  216. #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
  217. #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
  218. #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
  219. #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
  220. #define MX51_ECSPI_INT 0x10
  221. #define MX51_ECSPI_INT_TEEN (1 << 0)
  222. #define MX51_ECSPI_INT_RREN (1 << 3)
  223. #define MX51_ECSPI_INT_RDREN (1 << 4)
  224. #define MX51_ECSPI_DMA 0x14
  225. #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
  226. #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
  227. #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
  228. #define MX51_ECSPI_DMA_TEDEN (1 << 7)
  229. #define MX51_ECSPI_DMA_RXDEN (1 << 23)
  230. #define MX51_ECSPI_DMA_RXTDEN (1 << 31)
  231. #define MX51_ECSPI_STAT 0x18
  232. #define MX51_ECSPI_STAT_RR (1 << 3)
  233. #define MX51_ECSPI_TESTREG 0x20
  234. #define MX51_ECSPI_TESTREG_LBC BIT(31)
  235. static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
  236. {
  237. unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
  238. #ifdef __LITTLE_ENDIAN
  239. unsigned int bytes_per_word;
  240. #endif
  241. if (spi_imx->rx_buf) {
  242. #ifdef __LITTLE_ENDIAN
  243. bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
  244. if (bytes_per_word == 1)
  245. val = cpu_to_be32(val);
  246. else if (bytes_per_word == 2)
  247. val = (val << 16) | (val >> 16);
  248. #endif
  249. *(u32 *)spi_imx->rx_buf = val;
  250. spi_imx->rx_buf += sizeof(u32);
  251. }
  252. spi_imx->remainder -= sizeof(u32);
  253. }
  254. static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
  255. {
  256. int unaligned;
  257. u32 val;
  258. unaligned = spi_imx->remainder % 4;
  259. if (!unaligned) {
  260. spi_imx_buf_rx_swap_u32(spi_imx);
  261. return;
  262. }
  263. if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
  264. spi_imx_buf_rx_u16(spi_imx);
  265. return;
  266. }
  267. val = readl(spi_imx->base + MXC_CSPIRXDATA);
  268. while (unaligned--) {
  269. if (spi_imx->rx_buf) {
  270. *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
  271. spi_imx->rx_buf++;
  272. }
  273. spi_imx->remainder--;
  274. }
  275. }
  276. static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
  277. {
  278. u32 val = 0;
  279. #ifdef __LITTLE_ENDIAN
  280. unsigned int bytes_per_word;
  281. #endif
  282. if (spi_imx->tx_buf) {
  283. val = *(u32 *)spi_imx->tx_buf;
  284. spi_imx->tx_buf += sizeof(u32);
  285. }
  286. spi_imx->count -= sizeof(u32);
  287. #ifdef __LITTLE_ENDIAN
  288. bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
  289. if (bytes_per_word == 1)
  290. val = cpu_to_be32(val);
  291. else if (bytes_per_word == 2)
  292. val = (val << 16) | (val >> 16);
  293. #endif
  294. writel(val, spi_imx->base + MXC_CSPITXDATA);
  295. }
  296. static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
  297. {
  298. int unaligned;
  299. u32 val = 0;
  300. unaligned = spi_imx->count % 4;
  301. if (!unaligned) {
  302. spi_imx_buf_tx_swap_u32(spi_imx);
  303. return;
  304. }
  305. if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
  306. spi_imx_buf_tx_u16(spi_imx);
  307. return;
  308. }
  309. while (unaligned--) {
  310. if (spi_imx->tx_buf) {
  311. val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
  312. spi_imx->tx_buf++;
  313. }
  314. spi_imx->count--;
  315. }
  316. writel(val, spi_imx->base + MXC_CSPITXDATA);
  317. }
  318. static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx)
  319. {
  320. u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
  321. if (spi_imx->rx_buf) {
  322. int n_bytes = spi_imx->slave_burst % sizeof(val);
  323. if (!n_bytes)
  324. n_bytes = sizeof(val);
  325. memcpy(spi_imx->rx_buf,
  326. ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
  327. spi_imx->rx_buf += n_bytes;
  328. spi_imx->slave_burst -= n_bytes;
  329. }
  330. spi_imx->remainder -= sizeof(u32);
  331. }
  332. static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx)
  333. {
  334. u32 val = 0;
  335. int n_bytes = spi_imx->count % sizeof(val);
  336. if (!n_bytes)
  337. n_bytes = sizeof(val);
  338. if (spi_imx->tx_buf) {
  339. memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
  340. spi_imx->tx_buf, n_bytes);
  341. val = cpu_to_be32(val);
  342. spi_imx->tx_buf += n_bytes;
  343. }
  344. spi_imx->count -= n_bytes;
  345. writel(val, spi_imx->base + MXC_CSPITXDATA);
  346. }
  347. /* MX51 eCSPI */
  348. static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
  349. unsigned int fspi, unsigned int *fres)
  350. {
  351. /*
  352. * there are two 4-bit dividers, the pre-divider divides by
  353. * $pre, the post-divider by 2^$post
  354. */
  355. unsigned int pre, post;
  356. unsigned int fin = spi_imx->spi_clk;
  357. if (unlikely(fspi > fin))
  358. return 0;
  359. post = fls(fin) - fls(fspi);
  360. if (fin > fspi << post)
  361. post++;
  362. /* now we have: (fin <= fspi << post) with post being minimal */
  363. post = max(4U, post) - 4;
  364. if (unlikely(post > 0xf)) {
  365. dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
  366. fspi, fin);
  367. return 0xff;
  368. }
  369. pre = DIV_ROUND_UP(fin, fspi << post) - 1;
  370. dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
  371. __func__, fin, fspi, post, pre);
  372. /* Resulting frequency for the SCLK line. */
  373. *fres = (fin / (pre + 1)) >> post;
  374. return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
  375. (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
  376. }
  377. static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
  378. {
  379. unsigned val = 0;
  380. if (enable & MXC_INT_TE)
  381. val |= MX51_ECSPI_INT_TEEN;
  382. if (enable & MXC_INT_RR)
  383. val |= MX51_ECSPI_INT_RREN;
  384. if (enable & MXC_INT_RDR)
  385. val |= MX51_ECSPI_INT_RDREN;
  386. writel(val, spi_imx->base + MX51_ECSPI_INT);
  387. }
  388. static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
  389. {
  390. u32 reg;
  391. reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
  392. reg |= MX51_ECSPI_CTRL_XCH;
  393. writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
  394. }
  395. static void mx51_disable_dma(struct spi_imx_data *spi_imx)
  396. {
  397. writel(0, spi_imx->base + MX51_ECSPI_DMA);
  398. }
  399. static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
  400. {
  401. u32 ctrl;
  402. ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
  403. ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
  404. writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
  405. }
  406. static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
  407. struct spi_message *msg)
  408. {
  409. struct spi_device *spi = msg->spi;
  410. struct spi_transfer *xfer;
  411. u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
  412. u32 min_speed_hz = ~0U;
  413. u32 testreg, delay;
  414. u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
  415. /* set Master or Slave mode */
  416. if (spi_imx->slave_mode)
  417. ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
  418. else
  419. ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
  420. /*
  421. * Enable SPI_RDY handling (falling edge/level triggered).
  422. */
  423. if (spi->mode & SPI_READY)
  424. ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
  425. /* set chip select to use */
  426. ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
  427. /*
  428. * The ctrl register must be written first, with the EN bit set other
  429. * registers must not be written to.
  430. */
  431. writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
  432. testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
  433. if (spi->mode & SPI_LOOP)
  434. testreg |= MX51_ECSPI_TESTREG_LBC;
  435. else
  436. testreg &= ~MX51_ECSPI_TESTREG_LBC;
  437. writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
  438. /*
  439. * eCSPI burst completion by Chip Select signal in Slave mode
  440. * is not functional for imx53 Soc, config SPI burst completed when
  441. * BURST_LENGTH + 1 bits are received
  442. */
  443. if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
  444. cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
  445. else
  446. cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
  447. if (spi->mode & SPI_CPHA)
  448. cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
  449. else
  450. cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
  451. if (spi->mode & SPI_CPOL) {
  452. cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
  453. cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
  454. } else {
  455. cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
  456. cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
  457. }
  458. if (spi->mode & SPI_CS_HIGH)
  459. cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
  460. else
  461. cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
  462. writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
  463. /*
  464. * Wait until the changes in the configuration register CONFIGREG
  465. * propagate into the hardware. It takes exactly one tick of the
  466. * SCLK clock, but we will wait two SCLK clock just to be sure. The
  467. * effect of the delay it takes for the hardware to apply changes
  468. * is noticable if the SCLK clock run very slow. In such a case, if
  469. * the polarity of SCLK should be inverted, the GPIO ChipSelect might
  470. * be asserted before the SCLK polarity changes, which would disrupt
  471. * the SPI communication as the device on the other end would consider
  472. * the change of SCLK polarity as a clock tick already.
  473. *
  474. * Because spi_imx->spi_bus_clk is only set in bitbang prepare_message
  475. * callback, iterate over all the transfers in spi_message, find the
  476. * one with lowest bus frequency, and use that bus frequency for the
  477. * delay calculation. In case all transfers have speed_hz == 0, then
  478. * min_speed_hz is ~0 and the resulting delay is zero.
  479. */
  480. list_for_each_entry(xfer, &msg->transfers, transfer_list) {
  481. if (!xfer->speed_hz)
  482. continue;
  483. min_speed_hz = min(xfer->speed_hz, min_speed_hz);
  484. }
  485. delay = (2 * 1000000) / min_speed_hz;
  486. if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
  487. udelay(delay);
  488. else /* SCLK is _very_ slow */
  489. usleep_range(delay, delay + 10);
  490. return 0;
  491. }
  492. static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
  493. struct spi_device *spi)
  494. {
  495. u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
  496. u32 clk;
  497. /* Clear BL field and set the right value */
  498. ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
  499. if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
  500. ctrl |= (spi_imx->slave_burst * 8 - 1)
  501. << MX51_ECSPI_CTRL_BL_OFFSET;
  502. else
  503. ctrl |= (spi_imx->bits_per_word - 1)
  504. << MX51_ECSPI_CTRL_BL_OFFSET;
  505. /* set clock speed */
  506. ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
  507. 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
  508. ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk);
  509. spi_imx->spi_bus_clk = clk;
  510. if (spi_imx->usedma)
  511. ctrl |= MX51_ECSPI_CTRL_SMC;
  512. writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
  513. return 0;
  514. }
  515. static void mx51_setup_wml(struct spi_imx_data *spi_imx)
  516. {
  517. /*
  518. * Configure the DMA register: setup the watermark
  519. * and enable DMA request.
  520. */
  521. writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
  522. MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
  523. MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
  524. MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
  525. MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
  526. }
  527. static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
  528. {
  529. return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
  530. }
  531. static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
  532. {
  533. /* drain receive buffer */
  534. while (mx51_ecspi_rx_available(spi_imx))
  535. readl(spi_imx->base + MXC_CSPIRXDATA);
  536. }
  537. #define MX31_INTREG_TEEN (1 << 0)
  538. #define MX31_INTREG_RREN (1 << 3)
  539. #define MX31_CSPICTRL_ENABLE (1 << 0)
  540. #define MX31_CSPICTRL_MASTER (1 << 1)
  541. #define MX31_CSPICTRL_XCH (1 << 2)
  542. #define MX31_CSPICTRL_SMC (1 << 3)
  543. #define MX31_CSPICTRL_POL (1 << 4)
  544. #define MX31_CSPICTRL_PHA (1 << 5)
  545. #define MX31_CSPICTRL_SSCTL (1 << 6)
  546. #define MX31_CSPICTRL_SSPOL (1 << 7)
  547. #define MX31_CSPICTRL_BC_SHIFT 8
  548. #define MX35_CSPICTRL_BL_SHIFT 20
  549. #define MX31_CSPICTRL_CS_SHIFT 24
  550. #define MX35_CSPICTRL_CS_SHIFT 12
  551. #define MX31_CSPICTRL_DR_SHIFT 16
  552. #define MX31_CSPI_DMAREG 0x10
  553. #define MX31_DMAREG_RH_DEN (1<<4)
  554. #define MX31_DMAREG_TH_DEN (1<<1)
  555. #define MX31_CSPISTATUS 0x14
  556. #define MX31_STATUS_RR (1 << 3)
  557. #define MX31_CSPI_TESTREG 0x1C
  558. #define MX31_TEST_LBC (1 << 14)
  559. /* These functions also work for the i.MX35, but be aware that
  560. * the i.MX35 has a slightly different register layout for bits
  561. * we do not use here.
  562. */
  563. static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
  564. {
  565. unsigned int val = 0;
  566. if (enable & MXC_INT_TE)
  567. val |= MX31_INTREG_TEEN;
  568. if (enable & MXC_INT_RR)
  569. val |= MX31_INTREG_RREN;
  570. writel(val, spi_imx->base + MXC_CSPIINT);
  571. }
  572. static void mx31_trigger(struct spi_imx_data *spi_imx)
  573. {
  574. unsigned int reg;
  575. reg = readl(spi_imx->base + MXC_CSPICTRL);
  576. reg |= MX31_CSPICTRL_XCH;
  577. writel(reg, spi_imx->base + MXC_CSPICTRL);
  578. }
  579. static int mx31_prepare_message(struct spi_imx_data *spi_imx,
  580. struct spi_message *msg)
  581. {
  582. return 0;
  583. }
  584. static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
  585. struct spi_device *spi)
  586. {
  587. unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
  588. unsigned int clk;
  589. reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
  590. MX31_CSPICTRL_DR_SHIFT;
  591. spi_imx->spi_bus_clk = clk;
  592. if (is_imx35_cspi(spi_imx)) {
  593. reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
  594. reg |= MX31_CSPICTRL_SSCTL;
  595. } else {
  596. reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
  597. }
  598. if (spi->mode & SPI_CPHA)
  599. reg |= MX31_CSPICTRL_PHA;
  600. if (spi->mode & SPI_CPOL)
  601. reg |= MX31_CSPICTRL_POL;
  602. if (spi->mode & SPI_CS_HIGH)
  603. reg |= MX31_CSPICTRL_SSPOL;
  604. if (!spi->cs_gpiod)
  605. reg |= (spi->chip_select) <<
  606. (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
  607. MX31_CSPICTRL_CS_SHIFT);
  608. if (spi_imx->usedma)
  609. reg |= MX31_CSPICTRL_SMC;
  610. writel(reg, spi_imx->base + MXC_CSPICTRL);
  611. reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
  612. if (spi->mode & SPI_LOOP)
  613. reg |= MX31_TEST_LBC;
  614. else
  615. reg &= ~MX31_TEST_LBC;
  616. writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
  617. if (spi_imx->usedma) {
  618. /*
  619. * configure DMA requests when RXFIFO is half full and
  620. * when TXFIFO is half empty
  621. */
  622. writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
  623. spi_imx->base + MX31_CSPI_DMAREG);
  624. }
  625. return 0;
  626. }
  627. static int mx31_rx_available(struct spi_imx_data *spi_imx)
  628. {
  629. return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
  630. }
  631. static void mx31_reset(struct spi_imx_data *spi_imx)
  632. {
  633. /* drain receive buffer */
  634. while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
  635. readl(spi_imx->base + MXC_CSPIRXDATA);
  636. }
  637. #define MX21_INTREG_RR (1 << 4)
  638. #define MX21_INTREG_TEEN (1 << 9)
  639. #define MX21_INTREG_RREN (1 << 13)
  640. #define MX21_CSPICTRL_POL (1 << 5)
  641. #define MX21_CSPICTRL_PHA (1 << 6)
  642. #define MX21_CSPICTRL_SSPOL (1 << 8)
  643. #define MX21_CSPICTRL_XCH (1 << 9)
  644. #define MX21_CSPICTRL_ENABLE (1 << 10)
  645. #define MX21_CSPICTRL_MASTER (1 << 11)
  646. #define MX21_CSPICTRL_DR_SHIFT 14
  647. #define MX21_CSPICTRL_CS_SHIFT 19
  648. static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
  649. {
  650. unsigned int val = 0;
  651. if (enable & MXC_INT_TE)
  652. val |= MX21_INTREG_TEEN;
  653. if (enable & MXC_INT_RR)
  654. val |= MX21_INTREG_RREN;
  655. writel(val, spi_imx->base + MXC_CSPIINT);
  656. }
  657. static void mx21_trigger(struct spi_imx_data *spi_imx)
  658. {
  659. unsigned int reg;
  660. reg = readl(spi_imx->base + MXC_CSPICTRL);
  661. reg |= MX21_CSPICTRL_XCH;
  662. writel(reg, spi_imx->base + MXC_CSPICTRL);
  663. }
  664. static int mx21_prepare_message(struct spi_imx_data *spi_imx,
  665. struct spi_message *msg)
  666. {
  667. return 0;
  668. }
  669. static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
  670. struct spi_device *spi)
  671. {
  672. unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
  673. unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
  674. unsigned int clk;
  675. reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk)
  676. << MX21_CSPICTRL_DR_SHIFT;
  677. spi_imx->spi_bus_clk = clk;
  678. reg |= spi_imx->bits_per_word - 1;
  679. if (spi->mode & SPI_CPHA)
  680. reg |= MX21_CSPICTRL_PHA;
  681. if (spi->mode & SPI_CPOL)
  682. reg |= MX21_CSPICTRL_POL;
  683. if (spi->mode & SPI_CS_HIGH)
  684. reg |= MX21_CSPICTRL_SSPOL;
  685. if (!spi->cs_gpiod)
  686. reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
  687. writel(reg, spi_imx->base + MXC_CSPICTRL);
  688. return 0;
  689. }
  690. static int mx21_rx_available(struct spi_imx_data *spi_imx)
  691. {
  692. return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
  693. }
  694. static void mx21_reset(struct spi_imx_data *spi_imx)
  695. {
  696. writel(1, spi_imx->base + MXC_RESET);
  697. }
  698. #define MX1_INTREG_RR (1 << 3)
  699. #define MX1_INTREG_TEEN (1 << 8)
  700. #define MX1_INTREG_RREN (1 << 11)
  701. #define MX1_CSPICTRL_POL (1 << 4)
  702. #define MX1_CSPICTRL_PHA (1 << 5)
  703. #define MX1_CSPICTRL_XCH (1 << 8)
  704. #define MX1_CSPICTRL_ENABLE (1 << 9)
  705. #define MX1_CSPICTRL_MASTER (1 << 10)
  706. #define MX1_CSPICTRL_DR_SHIFT 13
  707. static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
  708. {
  709. unsigned int val = 0;
  710. if (enable & MXC_INT_TE)
  711. val |= MX1_INTREG_TEEN;
  712. if (enable & MXC_INT_RR)
  713. val |= MX1_INTREG_RREN;
  714. writel(val, spi_imx->base + MXC_CSPIINT);
  715. }
  716. static void mx1_trigger(struct spi_imx_data *spi_imx)
  717. {
  718. unsigned int reg;
  719. reg = readl(spi_imx->base + MXC_CSPICTRL);
  720. reg |= MX1_CSPICTRL_XCH;
  721. writel(reg, spi_imx->base + MXC_CSPICTRL);
  722. }
  723. static int mx1_prepare_message(struct spi_imx_data *spi_imx,
  724. struct spi_message *msg)
  725. {
  726. return 0;
  727. }
  728. static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
  729. struct spi_device *spi)
  730. {
  731. unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
  732. unsigned int clk;
  733. reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
  734. MX1_CSPICTRL_DR_SHIFT;
  735. spi_imx->spi_bus_clk = clk;
  736. reg |= spi_imx->bits_per_word - 1;
  737. if (spi->mode & SPI_CPHA)
  738. reg |= MX1_CSPICTRL_PHA;
  739. if (spi->mode & SPI_CPOL)
  740. reg |= MX1_CSPICTRL_POL;
  741. writel(reg, spi_imx->base + MXC_CSPICTRL);
  742. return 0;
  743. }
  744. static int mx1_rx_available(struct spi_imx_data *spi_imx)
  745. {
  746. return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
  747. }
  748. static void mx1_reset(struct spi_imx_data *spi_imx)
  749. {
  750. writel(1, spi_imx->base + MXC_RESET);
  751. }
  752. static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
  753. .intctrl = mx1_intctrl,
  754. .prepare_message = mx1_prepare_message,
  755. .prepare_transfer = mx1_prepare_transfer,
  756. .trigger = mx1_trigger,
  757. .rx_available = mx1_rx_available,
  758. .reset = mx1_reset,
  759. .fifo_size = 8,
  760. .has_dmamode = false,
  761. .dynamic_burst = false,
  762. .has_slavemode = false,
  763. .devtype = IMX1_CSPI,
  764. };
  765. static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
  766. .intctrl = mx21_intctrl,
  767. .prepare_message = mx21_prepare_message,
  768. .prepare_transfer = mx21_prepare_transfer,
  769. .trigger = mx21_trigger,
  770. .rx_available = mx21_rx_available,
  771. .reset = mx21_reset,
  772. .fifo_size = 8,
  773. .has_dmamode = false,
  774. .dynamic_burst = false,
  775. .has_slavemode = false,
  776. .devtype = IMX21_CSPI,
  777. };
  778. static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
  779. /* i.mx27 cspi shares the functions with i.mx21 one */
  780. .intctrl = mx21_intctrl,
  781. .prepare_message = mx21_prepare_message,
  782. .prepare_transfer = mx21_prepare_transfer,
  783. .trigger = mx21_trigger,
  784. .rx_available = mx21_rx_available,
  785. .reset = mx21_reset,
  786. .fifo_size = 8,
  787. .has_dmamode = false,
  788. .dynamic_burst = false,
  789. .has_slavemode = false,
  790. .devtype = IMX27_CSPI,
  791. };
  792. static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
  793. .intctrl = mx31_intctrl,
  794. .prepare_message = mx31_prepare_message,
  795. .prepare_transfer = mx31_prepare_transfer,
  796. .trigger = mx31_trigger,
  797. .rx_available = mx31_rx_available,
  798. .reset = mx31_reset,
  799. .fifo_size = 8,
  800. .has_dmamode = false,
  801. .dynamic_burst = false,
  802. .has_slavemode = false,
  803. .devtype = IMX31_CSPI,
  804. };
  805. static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
  806. /* i.mx35 and later cspi shares the functions with i.mx31 one */
  807. .intctrl = mx31_intctrl,
  808. .prepare_message = mx31_prepare_message,
  809. .prepare_transfer = mx31_prepare_transfer,
  810. .trigger = mx31_trigger,
  811. .rx_available = mx31_rx_available,
  812. .reset = mx31_reset,
  813. .fifo_size = 8,
  814. .has_dmamode = true,
  815. .dynamic_burst = false,
  816. .has_slavemode = false,
  817. .devtype = IMX35_CSPI,
  818. };
  819. static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
  820. .intctrl = mx51_ecspi_intctrl,
  821. .prepare_message = mx51_ecspi_prepare_message,
  822. .prepare_transfer = mx51_ecspi_prepare_transfer,
  823. .trigger = mx51_ecspi_trigger,
  824. .rx_available = mx51_ecspi_rx_available,
  825. .reset = mx51_ecspi_reset,
  826. .setup_wml = mx51_setup_wml,
  827. .disable_dma = mx51_disable_dma,
  828. .fifo_size = 64,
  829. .has_dmamode = true,
  830. .dynamic_burst = true,
  831. .has_slavemode = true,
  832. .disable = mx51_ecspi_disable,
  833. .devtype = IMX51_ECSPI,
  834. };
  835. static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
  836. .intctrl = mx51_ecspi_intctrl,
  837. .prepare_message = mx51_ecspi_prepare_message,
  838. .prepare_transfer = mx51_ecspi_prepare_transfer,
  839. .trigger = mx51_ecspi_trigger,
  840. .rx_available = mx51_ecspi_rx_available,
  841. .disable_dma = mx51_disable_dma,
  842. .reset = mx51_ecspi_reset,
  843. .fifo_size = 64,
  844. .has_dmamode = true,
  845. .has_slavemode = true,
  846. .disable = mx51_ecspi_disable,
  847. .devtype = IMX53_ECSPI,
  848. };
  849. static const struct platform_device_id spi_imx_devtype[] = {
  850. {
  851. .name = "imx1-cspi",
  852. .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
  853. }, {
  854. .name = "imx21-cspi",
  855. .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
  856. }, {
  857. .name = "imx27-cspi",
  858. .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
  859. }, {
  860. .name = "imx31-cspi",
  861. .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
  862. }, {
  863. .name = "imx35-cspi",
  864. .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
  865. }, {
  866. .name = "imx51-ecspi",
  867. .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
  868. }, {
  869. .name = "imx53-ecspi",
  870. .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
  871. }, {
  872. /* sentinel */
  873. }
  874. };
  875. static const struct of_device_id spi_imx_dt_ids[] = {
  876. { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
  877. { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
  878. { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
  879. { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
  880. { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
  881. { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
  882. { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
  883. { /* sentinel */ }
  884. };
  885. MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
  886. static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
  887. {
  888. u32 ctrl;
  889. ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
  890. ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
  891. ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
  892. writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
  893. }
  894. static void spi_imx_push(struct spi_imx_data *spi_imx)
  895. {
  896. unsigned int burst_len, fifo_words;
  897. if (spi_imx->dynamic_burst)
  898. fifo_words = 4;
  899. else
  900. fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word);
  901. /*
  902. * Reload the FIFO when the remaining bytes to be transferred in the
  903. * current burst is 0. This only applies when bits_per_word is a
  904. * multiple of 8.
  905. */
  906. if (!spi_imx->remainder) {
  907. if (spi_imx->dynamic_burst) {
  908. /* We need to deal unaligned data first */
  909. burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;
  910. if (!burst_len)
  911. burst_len = MX51_ECSPI_CTRL_MAX_BURST;
  912. spi_imx_set_burst_len(spi_imx, burst_len * 8);
  913. spi_imx->remainder = burst_len;
  914. } else {
  915. spi_imx->remainder = fifo_words;
  916. }
  917. }
  918. while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
  919. if (!spi_imx->count)
  920. break;
  921. if (spi_imx->dynamic_burst &&
  922. spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder,
  923. fifo_words))
  924. break;
  925. spi_imx->tx(spi_imx);
  926. spi_imx->txfifo++;
  927. }
  928. if (!spi_imx->slave_mode)
  929. spi_imx->devtype_data->trigger(spi_imx);
  930. }
  931. static irqreturn_t spi_imx_isr(int irq, void *dev_id)
  932. {
  933. struct spi_imx_data *spi_imx = dev_id;
  934. while (spi_imx->txfifo &&
  935. spi_imx->devtype_data->rx_available(spi_imx)) {
  936. spi_imx->rx(spi_imx);
  937. spi_imx->txfifo--;
  938. }
  939. if (spi_imx->count) {
  940. spi_imx_push(spi_imx);
  941. return IRQ_HANDLED;
  942. }
  943. if (spi_imx->txfifo) {
  944. /* No data left to push, but still waiting for rx data,
  945. * enable receive data available interrupt.
  946. */
  947. spi_imx->devtype_data->intctrl(
  948. spi_imx, MXC_INT_RR);
  949. return IRQ_HANDLED;
  950. }
  951. spi_imx->devtype_data->intctrl(spi_imx, 0);
  952. complete(&spi_imx->xfer_done);
  953. return IRQ_HANDLED;
  954. }
  955. static int spi_imx_dma_configure(struct spi_master *master)
  956. {
  957. int ret;
  958. enum dma_slave_buswidth buswidth;
  959. struct dma_slave_config rx = {}, tx = {};
  960. struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
  961. switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
  962. case 4:
  963. buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
  964. break;
  965. case 2:
  966. buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
  967. break;
  968. case 1:
  969. buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
  970. break;
  971. default:
  972. return -EINVAL;
  973. }
  974. tx.direction = DMA_MEM_TO_DEV;
  975. tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
  976. tx.dst_addr_width = buswidth;
  977. tx.dst_maxburst = spi_imx->wml;
  978. ret = dmaengine_slave_config(master->dma_tx, &tx);
  979. if (ret) {
  980. dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
  981. return ret;
  982. }
  983. rx.direction = DMA_DEV_TO_MEM;
  984. rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
  985. rx.src_addr_width = buswidth;
  986. rx.src_maxburst = spi_imx->wml;
  987. ret = dmaengine_slave_config(master->dma_rx, &rx);
  988. if (ret) {
  989. dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
  990. return ret;
  991. }
  992. return 0;
  993. }
  994. static int spi_imx_setupxfer(struct spi_device *spi,
  995. struct spi_transfer *t)
  996. {
  997. struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
  998. if (!t)
  999. return 0;
  1000. if (!t->speed_hz) {
  1001. if (!spi->max_speed_hz) {
  1002. dev_err(&spi->dev, "no speed_hz provided!\n");
  1003. return -EINVAL;
  1004. }
  1005. dev_dbg(&spi->dev, "using spi->max_speed_hz!\n");
  1006. spi_imx->spi_bus_clk = spi->max_speed_hz;
  1007. } else
  1008. spi_imx->spi_bus_clk = t->speed_hz;
  1009. spi_imx->bits_per_word = t->bits_per_word;
  1010. /*
  1011. * Initialize the functions for transfer. To transfer non byte-aligned
  1012. * words, we have to use multiple word-size bursts, we can't use
  1013. * dynamic_burst in that case.
  1014. */
  1015. if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode &&
  1016. (spi_imx->bits_per_word == 8 ||
  1017. spi_imx->bits_per_word == 16 ||
  1018. spi_imx->bits_per_word == 32)) {
  1019. spi_imx->rx = spi_imx_buf_rx_swap;
  1020. spi_imx->tx = spi_imx_buf_tx_swap;
  1021. spi_imx->dynamic_burst = 1;
  1022. } else {
  1023. if (spi_imx->bits_per_word <= 8) {
  1024. spi_imx->rx = spi_imx_buf_rx_u8;
  1025. spi_imx->tx = spi_imx_buf_tx_u8;
  1026. } else if (spi_imx->bits_per_word <= 16) {
  1027. spi_imx->rx = spi_imx_buf_rx_u16;
  1028. spi_imx->tx = spi_imx_buf_tx_u16;
  1029. } else {
  1030. spi_imx->rx = spi_imx_buf_rx_u32;
  1031. spi_imx->tx = spi_imx_buf_tx_u32;
  1032. }
  1033. spi_imx->dynamic_burst = 0;
  1034. }
  1035. if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
  1036. spi_imx->usedma = true;
  1037. else
  1038. spi_imx->usedma = false;
  1039. if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
  1040. spi_imx->rx = mx53_ecspi_rx_slave;
  1041. spi_imx->tx = mx53_ecspi_tx_slave;
  1042. spi_imx->slave_burst = t->len;
  1043. }
  1044. spi_imx->devtype_data->prepare_transfer(spi_imx, spi);
  1045. return 0;
  1046. }
  1047. static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
  1048. {
  1049. struct spi_master *master = spi_imx->bitbang.master;
  1050. if (master->dma_rx) {
  1051. dma_release_channel(master->dma_rx);
  1052. master->dma_rx = NULL;
  1053. }
  1054. if (master->dma_tx) {
  1055. dma_release_channel(master->dma_tx);
  1056. master->dma_tx = NULL;
  1057. }
  1058. }
  1059. static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
  1060. struct spi_master *master)
  1061. {
  1062. int ret;
  1063. /* use pio mode for i.mx6dl chip TKT238285 */
  1064. if (of_machine_is_compatible("fsl,imx6dl"))
  1065. return 0;
  1066. spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
  1067. /* Prepare for TX DMA: */
  1068. master->dma_tx = dma_request_chan(dev, "tx");
  1069. if (IS_ERR(master->dma_tx)) {
  1070. ret = PTR_ERR(master->dma_tx);
  1071. dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
  1072. master->dma_tx = NULL;
  1073. goto err;
  1074. }
  1075. /* Prepare for RX : */
  1076. master->dma_rx = dma_request_chan(dev, "rx");
  1077. if (IS_ERR(master->dma_rx)) {
  1078. ret = PTR_ERR(master->dma_rx);
  1079. dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
  1080. master->dma_rx = NULL;
  1081. goto err;
  1082. }
  1083. init_completion(&spi_imx->dma_rx_completion);
  1084. init_completion(&spi_imx->dma_tx_completion);
  1085. master->can_dma = spi_imx_can_dma;
  1086. master->max_dma_len = MAX_SDMA_BD_BYTES;
  1087. spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
  1088. SPI_MASTER_MUST_TX;
  1089. return 0;
  1090. err:
  1091. spi_imx_sdma_exit(spi_imx);
  1092. return ret;
  1093. }
  1094. static void spi_imx_dma_rx_callback(void *cookie)
  1095. {
  1096. struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
  1097. complete(&spi_imx->dma_rx_completion);
  1098. }
  1099. static void spi_imx_dma_tx_callback(void *cookie)
  1100. {
  1101. struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
  1102. complete(&spi_imx->dma_tx_completion);
  1103. }
  1104. static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
  1105. {
  1106. unsigned long timeout = 0;
  1107. /* Time with actual data transfer and CS change delay related to HW */
  1108. timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
  1109. /* Add extra second for scheduler related activities */
  1110. timeout += 1;
  1111. /* Double calculated timeout */
  1112. return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
  1113. }
  1114. static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
  1115. struct spi_transfer *transfer)
  1116. {
  1117. struct dma_async_tx_descriptor *desc_tx, *desc_rx;
  1118. unsigned long transfer_timeout;
  1119. unsigned long timeout;
  1120. struct spi_master *master = spi_imx->bitbang.master;
  1121. struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
  1122. struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
  1123. unsigned int bytes_per_word, i;
  1124. int ret;
  1125. /* Get the right burst length from the last sg to ensure no tail data */
  1126. bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
  1127. for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
  1128. if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
  1129. break;
  1130. }
  1131. /* Use 1 as wml in case no available burst length got */
  1132. if (i == 0)
  1133. i = 1;
  1134. spi_imx->wml = i;
  1135. ret = spi_imx_dma_configure(master);
  1136. if (ret)
  1137. goto dma_failure_no_start;
  1138. if (!spi_imx->devtype_data->setup_wml) {
  1139. dev_err(spi_imx->dev, "No setup_wml()?\n");
  1140. ret = -EINVAL;
  1141. goto dma_failure_no_start;
  1142. }
  1143. spi_imx->devtype_data->setup_wml(spi_imx);
  1144. /*
  1145. * The TX DMA setup starts the transfer, so make sure RX is configured
  1146. * before TX.
  1147. */
  1148. desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
  1149. rx->sgl, rx->nents, DMA_DEV_TO_MEM,
  1150. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  1151. if (!desc_rx) {
  1152. ret = -EINVAL;
  1153. goto dma_failure_no_start;
  1154. }
  1155. desc_rx->callback = spi_imx_dma_rx_callback;
  1156. desc_rx->callback_param = (void *)spi_imx;
  1157. dmaengine_submit(desc_rx);
  1158. reinit_completion(&spi_imx->dma_rx_completion);
  1159. dma_async_issue_pending(master->dma_rx);
  1160. desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
  1161. tx->sgl, tx->nents, DMA_MEM_TO_DEV,
  1162. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  1163. if (!desc_tx) {
  1164. dmaengine_terminate_all(master->dma_tx);
  1165. dmaengine_terminate_all(master->dma_rx);
  1166. return -EINVAL;
  1167. }
  1168. desc_tx->callback = spi_imx_dma_tx_callback;
  1169. desc_tx->callback_param = (void *)spi_imx;
  1170. dmaengine_submit(desc_tx);
  1171. reinit_completion(&spi_imx->dma_tx_completion);
  1172. dma_async_issue_pending(master->dma_tx);
  1173. transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
  1174. /* Wait SDMA to finish the data transfer.*/
  1175. timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
  1176. transfer_timeout);
  1177. if (!timeout) {
  1178. dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
  1179. dmaengine_terminate_all(master->dma_tx);
  1180. dmaengine_terminate_all(master->dma_rx);
  1181. return -ETIMEDOUT;
  1182. }
  1183. timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
  1184. transfer_timeout);
  1185. if (!timeout) {
  1186. dev_err(&master->dev, "I/O Error in DMA RX\n");
  1187. spi_imx->devtype_data->reset(spi_imx);
  1188. dmaengine_terminate_all(master->dma_rx);
  1189. return -ETIMEDOUT;
  1190. }
  1191. return transfer->len;
  1192. /* fallback to pio */
  1193. dma_failure_no_start:
  1194. transfer->error |= SPI_TRANS_FAIL_NO_START;
  1195. return ret;
  1196. }
  1197. static int spi_imx_pio_transfer(struct spi_device *spi,
  1198. struct spi_transfer *transfer)
  1199. {
  1200. struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
  1201. unsigned long transfer_timeout;
  1202. unsigned long timeout;
  1203. spi_imx->tx_buf = transfer->tx_buf;
  1204. spi_imx->rx_buf = transfer->rx_buf;
  1205. spi_imx->count = transfer->len;
  1206. spi_imx->txfifo = 0;
  1207. spi_imx->remainder = 0;
  1208. reinit_completion(&spi_imx->xfer_done);
  1209. spi_imx_push(spi_imx);
  1210. spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
  1211. transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
  1212. timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
  1213. transfer_timeout);
  1214. if (!timeout) {
  1215. dev_err(&spi->dev, "I/O Error in PIO\n");
  1216. spi_imx->devtype_data->reset(spi_imx);
  1217. return -ETIMEDOUT;
  1218. }
  1219. return transfer->len;
  1220. }
  1221. static int spi_imx_pio_transfer_slave(struct spi_device *spi,
  1222. struct spi_transfer *transfer)
  1223. {
  1224. struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
  1225. int ret = transfer->len;
  1226. if (is_imx53_ecspi(spi_imx) &&
  1227. transfer->len > MX53_MAX_TRANSFER_BYTES) {
  1228. dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
  1229. MX53_MAX_TRANSFER_BYTES);
  1230. return -EMSGSIZE;
  1231. }
  1232. spi_imx->tx_buf = transfer->tx_buf;
  1233. spi_imx->rx_buf = transfer->rx_buf;
  1234. spi_imx->count = transfer->len;
  1235. spi_imx->txfifo = 0;
  1236. spi_imx->remainder = 0;
  1237. reinit_completion(&spi_imx->xfer_done);
  1238. spi_imx->slave_aborted = false;
  1239. spi_imx_push(spi_imx);
  1240. spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
  1241. if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
  1242. spi_imx->slave_aborted) {
  1243. dev_dbg(&spi->dev, "interrupted\n");
  1244. ret = -EINTR;
  1245. }
  1246. /* ecspi has a HW issue when works in Slave mode,
  1247. * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
  1248. * ECSPI_TXDATA keeps shift out the last word data,
  1249. * so we have to disable ECSPI when in slave mode after the
  1250. * transfer completes
  1251. */
  1252. if (spi_imx->devtype_data->disable)
  1253. spi_imx->devtype_data->disable(spi_imx);
  1254. return ret;
  1255. }
  1256. static int spi_imx_transfer(struct spi_device *spi,
  1257. struct spi_transfer *transfer)
  1258. {
  1259. struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
  1260. transfer->effective_speed_hz = spi_imx->spi_bus_clk;
  1261. /* flush rxfifo before transfer */
  1262. while (spi_imx->devtype_data->rx_available(spi_imx))
  1263. readl(spi_imx->base + MXC_CSPIRXDATA);
  1264. if (spi_imx->slave_mode)
  1265. return spi_imx_pio_transfer_slave(spi, transfer);
  1266. if (spi_imx->usedma)
  1267. return spi_imx_dma_transfer(spi_imx, transfer);
  1268. return spi_imx_pio_transfer(spi, transfer);
  1269. }
  1270. static int spi_imx_setup(struct spi_device *spi)
  1271. {
  1272. dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
  1273. spi->mode, spi->bits_per_word, spi->max_speed_hz);
  1274. return 0;
  1275. }
  1276. static void spi_imx_cleanup(struct spi_device *spi)
  1277. {
  1278. }
  1279. static int
  1280. spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
  1281. {
  1282. struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
  1283. int ret;
  1284. ret = pm_runtime_get_sync(spi_imx->dev);
  1285. if (ret < 0) {
  1286. pm_runtime_put_noidle(spi_imx->dev);
  1287. dev_err(spi_imx->dev, "failed to enable clock\n");
  1288. return ret;
  1289. }
  1290. ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
  1291. if (ret) {
  1292. pm_runtime_mark_last_busy(spi_imx->dev);
  1293. pm_runtime_put_autosuspend(spi_imx->dev);
  1294. }
  1295. return ret;
  1296. }
  1297. static int
  1298. spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
  1299. {
  1300. struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
  1301. pm_runtime_mark_last_busy(spi_imx->dev);
  1302. pm_runtime_put_autosuspend(spi_imx->dev);
  1303. return 0;
  1304. }
  1305. static int spi_imx_slave_abort(struct spi_master *master)
  1306. {
  1307. struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
  1308. spi_imx->slave_aborted = true;
  1309. complete(&spi_imx->xfer_done);
  1310. return 0;
  1311. }
  1312. static int spi_imx_probe(struct platform_device *pdev)
  1313. {
  1314. struct device_node *np = pdev->dev.of_node;
  1315. const struct of_device_id *of_id =
  1316. of_match_device(spi_imx_dt_ids, &pdev->dev);
  1317. struct spi_master *master;
  1318. struct spi_imx_data *spi_imx;
  1319. struct resource *res;
  1320. int ret, irq, spi_drctl;
  1321. const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data :
  1322. (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
  1323. bool slave_mode;
  1324. u32 val;
  1325. slave_mode = devtype_data->has_slavemode &&
  1326. of_property_read_bool(np, "spi-slave");
  1327. if (slave_mode)
  1328. master = spi_alloc_slave(&pdev->dev,
  1329. sizeof(struct spi_imx_data));
  1330. else
  1331. master = spi_alloc_master(&pdev->dev,
  1332. sizeof(struct spi_imx_data));
  1333. if (!master)
  1334. return -ENOMEM;
  1335. ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
  1336. if ((ret < 0) || (spi_drctl >= 0x3)) {
  1337. /* '11' is reserved */
  1338. spi_drctl = 0;
  1339. }
  1340. platform_set_drvdata(pdev, master);
  1341. master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
  1342. master->bus_num = np ? -1 : pdev->id;
  1343. master->use_gpio_descriptors = true;
  1344. spi_imx = spi_master_get_devdata(master);
  1345. spi_imx->bitbang.master = master;
  1346. spi_imx->dev = &pdev->dev;
  1347. spi_imx->slave_mode = slave_mode;
  1348. spi_imx->devtype_data = devtype_data;
  1349. /*
  1350. * Get number of chip selects from device properties. This can be
  1351. * coming from device tree or boardfiles, if it is not defined,
  1352. * a default value of 3 chip selects will be used, as all the legacy
  1353. * board files have <= 3 chip selects.
  1354. */
  1355. if (!device_property_read_u32(&pdev->dev, "num-cs", &val))
  1356. master->num_chipselect = val;
  1357. else
  1358. master->num_chipselect = 3;
  1359. spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
  1360. spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
  1361. spi_imx->bitbang.master->setup = spi_imx_setup;
  1362. spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
  1363. spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
  1364. spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
  1365. spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort;
  1366. spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
  1367. | SPI_NO_CS;
  1368. if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
  1369. is_imx53_ecspi(spi_imx))
  1370. spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
  1371. spi_imx->spi_drctl = spi_drctl;
  1372. init_completion(&spi_imx->xfer_done);
  1373. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1374. spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
  1375. if (IS_ERR(spi_imx->base)) {
  1376. ret = PTR_ERR(spi_imx->base);
  1377. goto out_master_put;
  1378. }
  1379. spi_imx->base_phys = res->start;
  1380. irq = platform_get_irq(pdev, 0);
  1381. if (irq < 0) {
  1382. ret = irq;
  1383. goto out_master_put;
  1384. }
  1385. ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
  1386. dev_name(&pdev->dev), spi_imx);
  1387. if (ret) {
  1388. dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
  1389. goto out_master_put;
  1390. }
  1391. spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
  1392. if (IS_ERR(spi_imx->clk_ipg)) {
  1393. ret = PTR_ERR(spi_imx->clk_ipg);
  1394. goto out_master_put;
  1395. }
  1396. spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
  1397. if (IS_ERR(spi_imx->clk_per)) {
  1398. ret = PTR_ERR(spi_imx->clk_per);
  1399. goto out_master_put;
  1400. }
  1401. ret = clk_prepare_enable(spi_imx->clk_per);
  1402. if (ret)
  1403. goto out_master_put;
  1404. ret = clk_prepare_enable(spi_imx->clk_ipg);
  1405. if (ret)
  1406. goto out_put_per;
  1407. pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT);
  1408. pm_runtime_use_autosuspend(spi_imx->dev);
  1409. pm_runtime_get_noresume(spi_imx->dev);
  1410. pm_runtime_set_active(spi_imx->dev);
  1411. pm_runtime_enable(spi_imx->dev);
  1412. spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
  1413. /*
  1414. * Only validated on i.mx35 and i.mx6 now, can remove the constraint
  1415. * if validated on other chips.
  1416. */
  1417. if (spi_imx->devtype_data->has_dmamode) {
  1418. ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
  1419. if (ret == -EPROBE_DEFER)
  1420. goto out_runtime_pm_put;
  1421. if (ret < 0)
  1422. dev_dbg(&pdev->dev, "dma setup error %d, use pio\n",
  1423. ret);
  1424. }
  1425. spi_imx->devtype_data->reset(spi_imx);
  1426. spi_imx->devtype_data->intctrl(spi_imx, 0);
  1427. master->dev.of_node = pdev->dev.of_node;
  1428. ret = spi_bitbang_start(&spi_imx->bitbang);
  1429. if (ret) {
  1430. dev_err_probe(&pdev->dev, ret, "bitbang start failed\n");
  1431. goto out_bitbang_start;
  1432. }
  1433. pm_runtime_mark_last_busy(spi_imx->dev);
  1434. pm_runtime_put_autosuspend(spi_imx->dev);
  1435. return ret;
  1436. out_bitbang_start:
  1437. if (spi_imx->devtype_data->has_dmamode)
  1438. spi_imx_sdma_exit(spi_imx);
  1439. out_runtime_pm_put:
  1440. pm_runtime_dont_use_autosuspend(spi_imx->dev);
  1441. pm_runtime_set_suspended(&pdev->dev);
  1442. pm_runtime_disable(spi_imx->dev);
  1443. clk_disable_unprepare(spi_imx->clk_ipg);
  1444. out_put_per:
  1445. clk_disable_unprepare(spi_imx->clk_per);
  1446. out_master_put:
  1447. spi_master_put(master);
  1448. return ret;
  1449. }
  1450. static int spi_imx_remove(struct platform_device *pdev)
  1451. {
  1452. struct spi_master *master = platform_get_drvdata(pdev);
  1453. struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
  1454. int ret;
  1455. spi_bitbang_stop(&spi_imx->bitbang);
  1456. ret = pm_runtime_get_sync(spi_imx->dev);
  1457. if (ret < 0) {
  1458. pm_runtime_put_noidle(spi_imx->dev);
  1459. dev_err(spi_imx->dev, "failed to enable clock\n");
  1460. return ret;
  1461. }
  1462. writel(0, spi_imx->base + MXC_CSPICTRL);
  1463. pm_runtime_dont_use_autosuspend(spi_imx->dev);
  1464. pm_runtime_put_sync(spi_imx->dev);
  1465. pm_runtime_disable(spi_imx->dev);
  1466. spi_imx_sdma_exit(spi_imx);
  1467. spi_master_put(master);
  1468. return 0;
  1469. }
  1470. static int __maybe_unused spi_imx_runtime_resume(struct device *dev)
  1471. {
  1472. struct spi_master *master = dev_get_drvdata(dev);
  1473. struct spi_imx_data *spi_imx;
  1474. int ret;
  1475. spi_imx = spi_master_get_devdata(master);
  1476. ret = clk_prepare_enable(spi_imx->clk_per);
  1477. if (ret)
  1478. return ret;
  1479. ret = clk_prepare_enable(spi_imx->clk_ipg);
  1480. if (ret) {
  1481. clk_disable_unprepare(spi_imx->clk_per);
  1482. return ret;
  1483. }
  1484. return 0;
  1485. }
  1486. static int __maybe_unused spi_imx_runtime_suspend(struct device *dev)
  1487. {
  1488. struct spi_master *master = dev_get_drvdata(dev);
  1489. struct spi_imx_data *spi_imx;
  1490. spi_imx = spi_master_get_devdata(master);
  1491. clk_disable_unprepare(spi_imx->clk_per);
  1492. clk_disable_unprepare(spi_imx->clk_ipg);
  1493. return 0;
  1494. }
  1495. static int __maybe_unused spi_imx_suspend(struct device *dev)
  1496. {
  1497. pinctrl_pm_select_sleep_state(dev);
  1498. return 0;
  1499. }
  1500. static int __maybe_unused spi_imx_resume(struct device *dev)
  1501. {
  1502. pinctrl_pm_select_default_state(dev);
  1503. return 0;
  1504. }
  1505. static const struct dev_pm_ops imx_spi_pm = {
  1506. SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend,
  1507. spi_imx_runtime_resume, NULL)
  1508. SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume)
  1509. };
  1510. static struct platform_driver spi_imx_driver = {
  1511. .driver = {
  1512. .name = DRIVER_NAME,
  1513. .of_match_table = spi_imx_dt_ids,
  1514. .pm = &imx_spi_pm,
  1515. },
  1516. .id_table = spi_imx_devtype,
  1517. .probe = spi_imx_probe,
  1518. .remove = spi_imx_remove,
  1519. };
  1520. module_platform_driver(spi_imx_driver);
  1521. MODULE_DESCRIPTION("SPI Controller driver");
  1522. MODULE_AUTHOR("Sascha Hauer, Pengutronix");
  1523. MODULE_LICENSE("GPL");
  1524. MODULE_ALIAS("platform:" DRIVER_NAME);