spi-hisi-sfc-v3xx.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. //
  3. // HiSilicon SPI NOR V3XX Flash Controller Driver for hi16xx chipsets
  4. //
  5. // Copyright (c) 2019 HiSilicon Technologies Co., Ltd.
  6. // Author: John Garry <john.garry@huawei.com>
  7. #include <linux/acpi.h>
  8. #include <linux/bitops.h>
  9. #include <linux/completion.h>
  10. #include <linux/dmi.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/iopoll.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/slab.h>
  16. #include <linux/spi/spi.h>
  17. #include <linux/spi/spi-mem.h>
  18. #define HISI_SFC_V3XX_VERSION (0x1f8)
  19. #define HISI_SFC_V3XX_RAW_INT_STAT (0x120)
  20. #define HISI_SFC_V3XX_INT_STAT (0x124)
  21. #define HISI_SFC_V3XX_INT_MASK (0x128)
  22. #define HISI_SFC_V3XX_INT_CLR (0x12c)
  23. #define HISI_SFC_V3XX_CMD_CFG (0x300)
  24. #define HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF 9
  25. #define HISI_SFC_V3XX_CMD_CFG_RW_MSK BIT(8)
  26. #define HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK BIT(7)
  27. #define HISI_SFC_V3XX_CMD_CFG_DUMMY_CNT_OFF 4
  28. #define HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK BIT(3)
  29. #define HISI_SFC_V3XX_CMD_CFG_CS_SEL_OFF 1
  30. #define HISI_SFC_V3XX_CMD_CFG_START_MSK BIT(0)
  31. #define HISI_SFC_V3XX_CMD_INS (0x308)
  32. #define HISI_SFC_V3XX_CMD_ADDR (0x30c)
  33. #define HISI_SFC_V3XX_CMD_DATABUF0 (0x400)
  34. /* Common definition of interrupt bit masks */
  35. #define HISI_SFC_V3XX_INT_MASK_ALL (0x1ff) /* all the masks */
  36. #define HISI_SFC_V3XX_INT_MASK_CPLT BIT(0) /* command execution complete */
  37. #define HISI_SFC_V3XX_INT_MASK_PP_ERR BIT(2) /* page progrom error */
  38. #define HISI_SFC_V3XX_INT_MASK_IACCES BIT(5) /* error visiting inaccessible/
  39. * protected address
  40. */
  41. /* IO Mode definition in HISI_SFC_V3XX_CMD_CFG */
  42. #define HISI_SFC_V3XX_STD (0 << 17)
  43. #define HISI_SFC_V3XX_DIDO (1 << 17)
  44. #define HISI_SFC_V3XX_DIO (2 << 17)
  45. #define HISI_SFC_V3XX_FULL_DIO (3 << 17)
  46. #define HISI_SFC_V3XX_QIQO (5 << 17)
  47. #define HISI_SFC_V3XX_QIO (6 << 17)
  48. #define HISI_SFC_V3XX_FULL_QIO (7 << 17)
  49. /*
  50. * The IO modes lookup table. hisi_sfc_v3xx_io_modes[(z - 1) / 2][y / 2][x / 2]
  51. * stands for x-y-z mode, as described in SFDP terminology. -EIO indicates
  52. * an invalid mode.
  53. */
  54. static const int hisi_sfc_v3xx_io_modes[2][3][3] = {
  55. {
  56. { HISI_SFC_V3XX_DIDO, HISI_SFC_V3XX_DIDO, HISI_SFC_V3XX_DIDO },
  57. { HISI_SFC_V3XX_DIO, HISI_SFC_V3XX_FULL_DIO, -EIO },
  58. { -EIO, -EIO, -EIO },
  59. },
  60. {
  61. { HISI_SFC_V3XX_QIQO, HISI_SFC_V3XX_QIQO, HISI_SFC_V3XX_QIQO },
  62. { -EIO, -EIO, -EIO },
  63. { HISI_SFC_V3XX_QIO, -EIO, HISI_SFC_V3XX_FULL_QIO },
  64. },
  65. };
  66. struct hisi_sfc_v3xx_host {
  67. struct device *dev;
  68. void __iomem *regbase;
  69. int max_cmd_dword;
  70. struct completion *completion;
  71. int irq;
  72. };
  73. static void hisi_sfc_v3xx_disable_int(struct hisi_sfc_v3xx_host *host)
  74. {
  75. writel(0, host->regbase + HISI_SFC_V3XX_INT_MASK);
  76. }
  77. static void hisi_sfc_v3xx_enable_int(struct hisi_sfc_v3xx_host *host)
  78. {
  79. writel(HISI_SFC_V3XX_INT_MASK_ALL, host->regbase + HISI_SFC_V3XX_INT_MASK);
  80. }
  81. static void hisi_sfc_v3xx_clear_int(struct hisi_sfc_v3xx_host *host)
  82. {
  83. writel(HISI_SFC_V3XX_INT_MASK_ALL, host->regbase + HISI_SFC_V3XX_INT_CLR);
  84. }
  85. /*
  86. * The interrupt status register indicates whether an error occurs
  87. * after per operation. Check it, and clear the interrupts for
  88. * next time judgement.
  89. */
  90. static int hisi_sfc_v3xx_handle_completion(struct hisi_sfc_v3xx_host *host)
  91. {
  92. u32 reg;
  93. reg = readl(host->regbase + HISI_SFC_V3XX_RAW_INT_STAT);
  94. hisi_sfc_v3xx_clear_int(host);
  95. if (reg & HISI_SFC_V3XX_INT_MASK_IACCES) {
  96. dev_err(host->dev, "fail to access protected address\n");
  97. return -EIO;
  98. }
  99. if (reg & HISI_SFC_V3XX_INT_MASK_PP_ERR) {
  100. dev_err(host->dev, "page program operation failed\n");
  101. return -EIO;
  102. }
  103. /*
  104. * The other bits of the interrupt registers is not currently
  105. * used and probably not be triggered in this driver. When it
  106. * happens, we regard it as an unsupported error here.
  107. */
  108. if (!(reg & HISI_SFC_V3XX_INT_MASK_CPLT)) {
  109. dev_err(host->dev, "unsupported error occurred, status=0x%x\n", reg);
  110. return -EIO;
  111. }
  112. return 0;
  113. }
  114. #define HISI_SFC_V3XX_WAIT_TIMEOUT_US 1000000
  115. #define HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US 10
  116. static int hisi_sfc_v3xx_wait_cmd_idle(struct hisi_sfc_v3xx_host *host)
  117. {
  118. u32 reg;
  119. return readl_poll_timeout(host->regbase + HISI_SFC_V3XX_CMD_CFG, reg,
  120. !(reg & HISI_SFC_V3XX_CMD_CFG_START_MSK),
  121. HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US,
  122. HISI_SFC_V3XX_WAIT_TIMEOUT_US);
  123. }
  124. static int hisi_sfc_v3xx_adjust_op_size(struct spi_mem *mem,
  125. struct spi_mem_op *op)
  126. {
  127. struct spi_device *spi = mem->spi;
  128. struct hisi_sfc_v3xx_host *host;
  129. uintptr_t addr = (uintptr_t)op->data.buf.in;
  130. int max_byte_count;
  131. host = spi_controller_get_devdata(spi->master);
  132. max_byte_count = host->max_cmd_dword * 4;
  133. if (!IS_ALIGNED(addr, 4) && op->data.nbytes >= 4)
  134. op->data.nbytes = 4 - (addr % 4);
  135. else if (op->data.nbytes > max_byte_count)
  136. op->data.nbytes = max_byte_count;
  137. return 0;
  138. }
  139. /*
  140. * The controller only supports Standard SPI mode, Duall mode and
  141. * Quad mode. Double sanitize the ops here to avoid OOB access.
  142. */
  143. static bool hisi_sfc_v3xx_supports_op(struct spi_mem *mem,
  144. const struct spi_mem_op *op)
  145. {
  146. if (op->data.buswidth > 4 || op->dummy.buswidth > 4 ||
  147. op->addr.buswidth > 4 || op->cmd.buswidth > 4)
  148. return false;
  149. return spi_mem_default_supports_op(mem, op);
  150. }
  151. /*
  152. * memcpy_{to,from}io doesn't gurantee 32b accesses - which we require for the
  153. * DATABUF registers -so use __io{read,write}32_copy when possible. For
  154. * trailing bytes, copy them byte-by-byte from the DATABUF register, as we
  155. * can't clobber outside the source/dest buffer.
  156. *
  157. * For efficient data read/write, we try to put any start 32b unaligned data
  158. * into a separate transaction in hisi_sfc_v3xx_adjust_op_size().
  159. */
  160. static void hisi_sfc_v3xx_read_databuf(struct hisi_sfc_v3xx_host *host,
  161. u8 *to, unsigned int len)
  162. {
  163. void __iomem *from;
  164. int i;
  165. from = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0;
  166. if (IS_ALIGNED((uintptr_t)to, 4)) {
  167. int words = len / 4;
  168. __ioread32_copy(to, from, words);
  169. len -= words * 4;
  170. if (len) {
  171. u32 val;
  172. to += words * 4;
  173. from += words * 4;
  174. val = __raw_readl(from);
  175. for (i = 0; i < len; i++, val >>= 8, to++)
  176. *to = (u8)val;
  177. }
  178. } else {
  179. for (i = 0; i < DIV_ROUND_UP(len, 4); i++, from += 4) {
  180. u32 val = __raw_readl(from);
  181. int j;
  182. for (j = 0; j < 4 && (j + (i * 4) < len);
  183. to++, val >>= 8, j++)
  184. *to = (u8)val;
  185. }
  186. }
  187. }
  188. static void hisi_sfc_v3xx_write_databuf(struct hisi_sfc_v3xx_host *host,
  189. const u8 *from, unsigned int len)
  190. {
  191. void __iomem *to;
  192. int i;
  193. to = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0;
  194. if (IS_ALIGNED((uintptr_t)from, 4)) {
  195. int words = len / 4;
  196. __iowrite32_copy(to, from, words);
  197. len -= words * 4;
  198. if (len) {
  199. u32 val = 0;
  200. to += words * 4;
  201. from += words * 4;
  202. for (i = 0; i < len; i++, from++)
  203. val |= *from << i * 8;
  204. __raw_writel(val, to);
  205. }
  206. } else {
  207. for (i = 0; i < DIV_ROUND_UP(len, 4); i++, to += 4) {
  208. u32 val = 0;
  209. int j;
  210. for (j = 0; j < 4 && (j + (i * 4) < len);
  211. from++, j++)
  212. val |= *from << j * 8;
  213. __raw_writel(val, to);
  214. }
  215. }
  216. }
  217. static int hisi_sfc_v3xx_start_bus(struct hisi_sfc_v3xx_host *host,
  218. const struct spi_mem_op *op,
  219. u8 chip_select)
  220. {
  221. int len = op->data.nbytes, buswidth_mode;
  222. u32 config = 0;
  223. if (op->addr.nbytes)
  224. config |= HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK;
  225. if (op->data.buswidth == 0 || op->data.buswidth == 1) {
  226. buswidth_mode = HISI_SFC_V3XX_STD;
  227. } else {
  228. int data_idx, addr_idx, cmd_idx;
  229. data_idx = (op->data.buswidth - 1) / 2;
  230. addr_idx = op->addr.buswidth / 2;
  231. cmd_idx = op->cmd.buswidth / 2;
  232. buswidth_mode = hisi_sfc_v3xx_io_modes[data_idx][addr_idx][cmd_idx];
  233. }
  234. if (buswidth_mode < 0)
  235. return buswidth_mode;
  236. config |= buswidth_mode;
  237. if (op->data.dir != SPI_MEM_NO_DATA) {
  238. config |= (len - 1) << HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF;
  239. config |= HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK;
  240. }
  241. if (op->data.dir == SPI_MEM_DATA_IN)
  242. config |= HISI_SFC_V3XX_CMD_CFG_RW_MSK;
  243. config |= op->dummy.nbytes << HISI_SFC_V3XX_CMD_CFG_DUMMY_CNT_OFF |
  244. chip_select << HISI_SFC_V3XX_CMD_CFG_CS_SEL_OFF |
  245. HISI_SFC_V3XX_CMD_CFG_START_MSK;
  246. writel(op->addr.val, host->regbase + HISI_SFC_V3XX_CMD_ADDR);
  247. writel(op->cmd.opcode, host->regbase + HISI_SFC_V3XX_CMD_INS);
  248. writel(config, host->regbase + HISI_SFC_V3XX_CMD_CFG);
  249. return 0;
  250. }
  251. static int hisi_sfc_v3xx_generic_exec_op(struct hisi_sfc_v3xx_host *host,
  252. const struct spi_mem_op *op,
  253. u8 chip_select)
  254. {
  255. DECLARE_COMPLETION_ONSTACK(done);
  256. int ret;
  257. if (host->irq) {
  258. host->completion = &done;
  259. hisi_sfc_v3xx_enable_int(host);
  260. }
  261. if (op->data.dir == SPI_MEM_DATA_OUT)
  262. hisi_sfc_v3xx_write_databuf(host, op->data.buf.out, op->data.nbytes);
  263. ret = hisi_sfc_v3xx_start_bus(host, op, chip_select);
  264. if (ret)
  265. return ret;
  266. if (host->irq) {
  267. ret = wait_for_completion_timeout(host->completion,
  268. usecs_to_jiffies(HISI_SFC_V3XX_WAIT_TIMEOUT_US));
  269. if (!ret)
  270. ret = -ETIMEDOUT;
  271. else
  272. ret = 0;
  273. hisi_sfc_v3xx_disable_int(host);
  274. host->completion = NULL;
  275. } else {
  276. ret = hisi_sfc_v3xx_wait_cmd_idle(host);
  277. }
  278. if (hisi_sfc_v3xx_handle_completion(host) || ret)
  279. return -EIO;
  280. if (op->data.dir == SPI_MEM_DATA_IN)
  281. hisi_sfc_v3xx_read_databuf(host, op->data.buf.in, op->data.nbytes);
  282. return 0;
  283. }
  284. static int hisi_sfc_v3xx_exec_op(struct spi_mem *mem,
  285. const struct spi_mem_op *op)
  286. {
  287. struct hisi_sfc_v3xx_host *host;
  288. struct spi_device *spi = mem->spi;
  289. u8 chip_select = spi->chip_select;
  290. host = spi_controller_get_devdata(spi->master);
  291. return hisi_sfc_v3xx_generic_exec_op(host, op, chip_select);
  292. }
  293. static const struct spi_controller_mem_ops hisi_sfc_v3xx_mem_ops = {
  294. .adjust_op_size = hisi_sfc_v3xx_adjust_op_size,
  295. .supports_op = hisi_sfc_v3xx_supports_op,
  296. .exec_op = hisi_sfc_v3xx_exec_op,
  297. };
  298. static irqreturn_t hisi_sfc_v3xx_isr(int irq, void *data)
  299. {
  300. struct hisi_sfc_v3xx_host *host = data;
  301. hisi_sfc_v3xx_disable_int(host);
  302. complete(host->completion);
  303. return IRQ_HANDLED;
  304. }
  305. static int hisi_sfc_v3xx_buswidth_override_bits;
  306. /*
  307. * ACPI FW does not allow us to currently set the device buswidth, so quirk it
  308. * depending on the board.
  309. */
  310. static int __init hisi_sfc_v3xx_dmi_quirk(const struct dmi_system_id *d)
  311. {
  312. hisi_sfc_v3xx_buswidth_override_bits = SPI_RX_QUAD | SPI_TX_QUAD;
  313. return 0;
  314. }
  315. static const struct dmi_system_id hisi_sfc_v3xx_dmi_quirk_table[] = {
  316. {
  317. .callback = hisi_sfc_v3xx_dmi_quirk,
  318. .matches = {
  319. DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
  320. DMI_MATCH(DMI_PRODUCT_NAME, "D06"),
  321. },
  322. },
  323. {
  324. .callback = hisi_sfc_v3xx_dmi_quirk,
  325. .matches = {
  326. DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
  327. DMI_MATCH(DMI_PRODUCT_NAME, "TaiShan 2280 V2"),
  328. },
  329. },
  330. {
  331. .callback = hisi_sfc_v3xx_dmi_quirk,
  332. .matches = {
  333. DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
  334. DMI_MATCH(DMI_PRODUCT_NAME, "TaiShan 200 (Model 2280)"),
  335. },
  336. },
  337. {}
  338. };
  339. static int hisi_sfc_v3xx_probe(struct platform_device *pdev)
  340. {
  341. struct device *dev = &pdev->dev;
  342. struct hisi_sfc_v3xx_host *host;
  343. struct spi_controller *ctlr;
  344. u32 version;
  345. int ret;
  346. ctlr = spi_alloc_master(&pdev->dev, sizeof(*host));
  347. if (!ctlr)
  348. return -ENOMEM;
  349. ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
  350. SPI_TX_DUAL | SPI_TX_QUAD;
  351. ctlr->buswidth_override_bits = hisi_sfc_v3xx_buswidth_override_bits;
  352. host = spi_controller_get_devdata(ctlr);
  353. host->dev = dev;
  354. platform_set_drvdata(pdev, host);
  355. host->regbase = devm_platform_ioremap_resource(pdev, 0);
  356. if (IS_ERR(host->regbase)) {
  357. ret = PTR_ERR(host->regbase);
  358. goto err_put_master;
  359. }
  360. host->irq = platform_get_irq_optional(pdev, 0);
  361. if (host->irq == -EPROBE_DEFER) {
  362. ret = -EPROBE_DEFER;
  363. goto err_put_master;
  364. }
  365. hisi_sfc_v3xx_disable_int(host);
  366. if (host->irq > 0) {
  367. ret = devm_request_irq(dev, host->irq, hisi_sfc_v3xx_isr, 0,
  368. "hisi-sfc-v3xx", host);
  369. if (ret) {
  370. dev_err(dev, "failed to request irq%d, ret = %d\n", host->irq, ret);
  371. host->irq = 0;
  372. }
  373. } else {
  374. host->irq = 0;
  375. }
  376. ctlr->bus_num = -1;
  377. ctlr->num_chipselect = 1;
  378. ctlr->mem_ops = &hisi_sfc_v3xx_mem_ops;
  379. version = readl(host->regbase + HISI_SFC_V3XX_VERSION);
  380. switch (version) {
  381. case 0x351:
  382. host->max_cmd_dword = 64;
  383. break;
  384. default:
  385. host->max_cmd_dword = 16;
  386. break;
  387. }
  388. ret = devm_spi_register_controller(dev, ctlr);
  389. if (ret)
  390. goto err_put_master;
  391. dev_info(&pdev->dev, "hw version 0x%x, %s mode.\n",
  392. version, host->irq ? "irq" : "polling");
  393. return 0;
  394. err_put_master:
  395. spi_master_put(ctlr);
  396. return ret;
  397. }
  398. #if IS_ENABLED(CONFIG_ACPI)
  399. static const struct acpi_device_id hisi_sfc_v3xx_acpi_ids[] = {
  400. {"HISI0341", 0},
  401. {}
  402. };
  403. MODULE_DEVICE_TABLE(acpi, hisi_sfc_v3xx_acpi_ids);
  404. #endif
  405. static struct platform_driver hisi_sfc_v3xx_spi_driver = {
  406. .driver = {
  407. .name = "hisi-sfc-v3xx",
  408. .acpi_match_table = ACPI_PTR(hisi_sfc_v3xx_acpi_ids),
  409. },
  410. .probe = hisi_sfc_v3xx_probe,
  411. };
  412. static int __init hisi_sfc_v3xx_spi_init(void)
  413. {
  414. dmi_check_system(hisi_sfc_v3xx_dmi_quirk_table);
  415. return platform_driver_register(&hisi_sfc_v3xx_spi_driver);
  416. }
  417. static void __exit hisi_sfc_v3xx_spi_exit(void)
  418. {
  419. platform_driver_unregister(&hisi_sfc_v3xx_spi_driver);
  420. }
  421. module_init(hisi_sfc_v3xx_spi_init);
  422. module_exit(hisi_sfc_v3xx_spi_exit);
  423. MODULE_LICENSE("GPL");
  424. MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
  425. MODULE_DESCRIPTION("HiSilicon SPI NOR V3XX Flash Controller Driver for hi16xx chipsets");