spi-fsl-spi.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Freescale SPI controller driver.
  4. *
  5. * Maintainer: Kumar Gala
  6. *
  7. * Copyright (C) 2006 Polycom, Inc.
  8. * Copyright 2010 Freescale Semiconductor, Inc.
  9. *
  10. * CPM SPI and QE buffer descriptors mode support:
  11. * Copyright (c) 2009 MontaVista Software, Inc.
  12. * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  13. *
  14. * GRLIB support:
  15. * Copyright (c) 2012 Aeroflex Gaisler AB.
  16. * Author: Andreas Larsson <andreas@gaisler.com>
  17. */
  18. #include <linux/delay.h>
  19. #include <linux/dma-mapping.h>
  20. #include <linux/fsl_devices.h>
  21. #include <linux/gpio/consumer.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/irq.h>
  24. #include <linux/kernel.h>
  25. #include <linux/mm.h>
  26. #include <linux/module.h>
  27. #include <linux/mutex.h>
  28. #include <linux/of.h>
  29. #include <linux/of_address.h>
  30. #include <linux/of_irq.h>
  31. #include <linux/of_platform.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/spi/spi.h>
  34. #include <linux/spi/spi_bitbang.h>
  35. #include <linux/types.h>
  36. #ifdef CONFIG_FSL_SOC
  37. #include <sysdev/fsl_soc.h>
  38. #endif
  39. /* Specific to the MPC8306/MPC8309 */
  40. #define IMMR_SPI_CS_OFFSET 0x14c
  41. #define SPI_BOOT_SEL_BIT 0x80000000
  42. #include "spi-fsl-lib.h"
  43. #include "spi-fsl-cpm.h"
  44. #include "spi-fsl-spi.h"
  45. #define TYPE_FSL 0
  46. #define TYPE_GRLIB 1
  47. struct fsl_spi_match_data {
  48. int type;
  49. };
  50. static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
  51. .type = TYPE_FSL,
  52. };
  53. static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
  54. .type = TYPE_GRLIB,
  55. };
  56. static const struct of_device_id of_fsl_spi_match[] = {
  57. {
  58. .compatible = "fsl,spi",
  59. .data = &of_fsl_spi_fsl_config,
  60. },
  61. {
  62. .compatible = "aeroflexgaisler,spictrl",
  63. .data = &of_fsl_spi_grlib_config,
  64. },
  65. {}
  66. };
  67. MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
  68. static int fsl_spi_get_type(struct device *dev)
  69. {
  70. const struct of_device_id *match;
  71. if (dev->of_node) {
  72. match = of_match_node(of_fsl_spi_match, dev->of_node);
  73. if (match && match->data)
  74. return ((struct fsl_spi_match_data *)match->data)->type;
  75. }
  76. return TYPE_FSL;
  77. }
  78. static void fsl_spi_change_mode(struct spi_device *spi)
  79. {
  80. struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
  81. struct spi_mpc8xxx_cs *cs = spi->controller_state;
  82. struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
  83. __be32 __iomem *mode = &reg_base->mode;
  84. unsigned long flags;
  85. if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
  86. return;
  87. /* Turn off IRQs locally to minimize time that SPI is disabled. */
  88. local_irq_save(flags);
  89. /* Turn off SPI unit prior changing mode */
  90. mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
  91. /* When in CPM mode, we need to reinit tx and rx. */
  92. if (mspi->flags & SPI_CPM_MODE) {
  93. fsl_spi_cpm_reinit_txrx(mspi);
  94. }
  95. mpc8xxx_spi_write_reg(mode, cs->hw_mode);
  96. local_irq_restore(flags);
  97. }
  98. static void fsl_spi_chipselect(struct spi_device *spi, int value)
  99. {
  100. struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
  101. struct fsl_spi_platform_data *pdata;
  102. struct spi_mpc8xxx_cs *cs = spi->controller_state;
  103. pdata = spi->dev.parent->parent->platform_data;
  104. if (value == BITBANG_CS_INACTIVE) {
  105. if (pdata->cs_control)
  106. pdata->cs_control(spi, false);
  107. }
  108. if (value == BITBANG_CS_ACTIVE) {
  109. mpc8xxx_spi->rx_shift = cs->rx_shift;
  110. mpc8xxx_spi->tx_shift = cs->tx_shift;
  111. mpc8xxx_spi->get_rx = cs->get_rx;
  112. mpc8xxx_spi->get_tx = cs->get_tx;
  113. fsl_spi_change_mode(spi);
  114. if (pdata->cs_control)
  115. pdata->cs_control(spi, true);
  116. }
  117. }
  118. static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
  119. int bits_per_word, int msb_first)
  120. {
  121. *rx_shift = 0;
  122. *tx_shift = 0;
  123. if (msb_first) {
  124. if (bits_per_word <= 8) {
  125. *rx_shift = 16;
  126. *tx_shift = 24;
  127. } else if (bits_per_word <= 16) {
  128. *rx_shift = 16;
  129. *tx_shift = 16;
  130. }
  131. } else {
  132. if (bits_per_word <= 8)
  133. *rx_shift = 8;
  134. }
  135. }
  136. static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
  137. int bits_per_word, int msb_first)
  138. {
  139. *rx_shift = 0;
  140. *tx_shift = 0;
  141. if (bits_per_word <= 16) {
  142. if (msb_first) {
  143. *rx_shift = 16; /* LSB in bit 16 */
  144. *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
  145. } else {
  146. *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
  147. }
  148. }
  149. }
  150. static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
  151. struct spi_device *spi,
  152. struct mpc8xxx_spi *mpc8xxx_spi,
  153. int bits_per_word)
  154. {
  155. cs->rx_shift = 0;
  156. cs->tx_shift = 0;
  157. if (bits_per_word <= 8) {
  158. cs->get_rx = mpc8xxx_spi_rx_buf_u8;
  159. cs->get_tx = mpc8xxx_spi_tx_buf_u8;
  160. } else if (bits_per_word <= 16) {
  161. cs->get_rx = mpc8xxx_spi_rx_buf_u16;
  162. cs->get_tx = mpc8xxx_spi_tx_buf_u16;
  163. } else if (bits_per_word <= 32) {
  164. cs->get_rx = mpc8xxx_spi_rx_buf_u32;
  165. cs->get_tx = mpc8xxx_spi_tx_buf_u32;
  166. } else
  167. return -EINVAL;
  168. if (mpc8xxx_spi->set_shifts)
  169. mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
  170. bits_per_word,
  171. !(spi->mode & SPI_LSB_FIRST));
  172. mpc8xxx_spi->rx_shift = cs->rx_shift;
  173. mpc8xxx_spi->tx_shift = cs->tx_shift;
  174. mpc8xxx_spi->get_rx = cs->get_rx;
  175. mpc8xxx_spi->get_tx = cs->get_tx;
  176. return bits_per_word;
  177. }
  178. static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
  179. struct spi_device *spi,
  180. int bits_per_word)
  181. {
  182. /* QE uses Little Endian for words > 8
  183. * so transform all words > 8 into 8 bits
  184. * Unfortnatly that doesn't work for LSB so
  185. * reject these for now */
  186. /* Note: 32 bits word, LSB works iff
  187. * tfcr/rfcr is set to CPMFCR_GBL */
  188. if (spi->mode & SPI_LSB_FIRST &&
  189. bits_per_word > 8)
  190. return -EINVAL;
  191. if (bits_per_word > 8)
  192. return 8; /* pretend its 8 bits */
  193. return bits_per_word;
  194. }
  195. static int fsl_spi_setup_transfer(struct spi_device *spi,
  196. struct spi_transfer *t)
  197. {
  198. struct mpc8xxx_spi *mpc8xxx_spi;
  199. int bits_per_word = 0;
  200. u8 pm;
  201. u32 hz = 0;
  202. struct spi_mpc8xxx_cs *cs = spi->controller_state;
  203. mpc8xxx_spi = spi_master_get_devdata(spi->master);
  204. if (t) {
  205. bits_per_word = t->bits_per_word;
  206. hz = t->speed_hz;
  207. }
  208. /* spi_transfer level calls that work per-word */
  209. if (!bits_per_word)
  210. bits_per_word = spi->bits_per_word;
  211. if (!hz)
  212. hz = spi->max_speed_hz;
  213. if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
  214. bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
  215. mpc8xxx_spi,
  216. bits_per_word);
  217. else if (mpc8xxx_spi->flags & SPI_QE)
  218. bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
  219. bits_per_word);
  220. if (bits_per_word < 0)
  221. return bits_per_word;
  222. if (bits_per_word == 32)
  223. bits_per_word = 0;
  224. else
  225. bits_per_word = bits_per_word - 1;
  226. /* mask out bits we are going to set */
  227. cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
  228. | SPMODE_PM(0xF));
  229. cs->hw_mode |= SPMODE_LEN(bits_per_word);
  230. if ((mpc8xxx_spi->spibrg / hz) > 64) {
  231. cs->hw_mode |= SPMODE_DIV16;
  232. pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
  233. WARN_ONCE(pm > 16,
  234. "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n",
  235. dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);
  236. if (pm > 16)
  237. pm = 16;
  238. } else {
  239. pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
  240. }
  241. if (pm)
  242. pm--;
  243. cs->hw_mode |= SPMODE_PM(pm);
  244. fsl_spi_change_mode(spi);
  245. return 0;
  246. }
  247. static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
  248. struct spi_transfer *t, unsigned int len)
  249. {
  250. u32 word;
  251. struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
  252. mspi->count = len;
  253. /* enable rx ints */
  254. mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
  255. /* transmit word */
  256. word = mspi->get_tx(mspi);
  257. mpc8xxx_spi_write_reg(&reg_base->transmit, word);
  258. return 0;
  259. }
  260. static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
  261. bool is_dma_mapped)
  262. {
  263. struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
  264. struct fsl_spi_reg __iomem *reg_base;
  265. unsigned int len = t->len;
  266. u8 bits_per_word;
  267. int ret;
  268. reg_base = mpc8xxx_spi->reg_base;
  269. bits_per_word = spi->bits_per_word;
  270. if (t->bits_per_word)
  271. bits_per_word = t->bits_per_word;
  272. if (bits_per_word > 8) {
  273. /* invalid length? */
  274. if (len & 1)
  275. return -EINVAL;
  276. len /= 2;
  277. }
  278. if (bits_per_word > 16) {
  279. /* invalid length? */
  280. if (len & 1)
  281. return -EINVAL;
  282. len /= 2;
  283. }
  284. mpc8xxx_spi->tx = t->tx_buf;
  285. mpc8xxx_spi->rx = t->rx_buf;
  286. reinit_completion(&mpc8xxx_spi->done);
  287. if (mpc8xxx_spi->flags & SPI_CPM_MODE)
  288. ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
  289. else
  290. ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
  291. if (ret)
  292. return ret;
  293. wait_for_completion(&mpc8xxx_spi->done);
  294. /* disable rx ints */
  295. mpc8xxx_spi_write_reg(&reg_base->mask, 0);
  296. if (mpc8xxx_spi->flags & SPI_CPM_MODE)
  297. fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
  298. return mpc8xxx_spi->count;
  299. }
  300. static int fsl_spi_do_one_msg(struct spi_master *master,
  301. struct spi_message *m)
  302. {
  303. struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
  304. struct spi_device *spi = m->spi;
  305. struct spi_transfer *t, *first;
  306. unsigned int cs_change;
  307. const int nsecs = 50;
  308. int status, last_bpw;
  309. /*
  310. * In CPU mode, optimize large byte transfers to use larger
  311. * bits_per_word values to reduce number of interrupts taken.
  312. */
  313. if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
  314. list_for_each_entry(t, &m->transfers, transfer_list) {
  315. if (t->len < 256 || t->bits_per_word != 8)
  316. continue;
  317. if ((t->len & 3) == 0)
  318. t->bits_per_word = 32;
  319. else if ((t->len & 1) == 0)
  320. t->bits_per_word = 16;
  321. }
  322. }
  323. /* Don't allow changes if CS is active */
  324. cs_change = 1;
  325. list_for_each_entry(t, &m->transfers, transfer_list) {
  326. if (cs_change)
  327. first = t;
  328. cs_change = t->cs_change;
  329. if (first->speed_hz != t->speed_hz) {
  330. dev_err(&spi->dev,
  331. "speed_hz cannot change while CS is active\n");
  332. return -EINVAL;
  333. }
  334. }
  335. last_bpw = -1;
  336. cs_change = 1;
  337. status = -EINVAL;
  338. list_for_each_entry(t, &m->transfers, transfer_list) {
  339. if (cs_change || last_bpw != t->bits_per_word)
  340. status = fsl_spi_setup_transfer(spi, t);
  341. if (status < 0)
  342. break;
  343. last_bpw = t->bits_per_word;
  344. if (cs_change) {
  345. fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
  346. ndelay(nsecs);
  347. }
  348. cs_change = t->cs_change;
  349. if (t->len)
  350. status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
  351. if (status) {
  352. status = -EMSGSIZE;
  353. break;
  354. }
  355. m->actual_length += t->len;
  356. spi_transfer_delay_exec(t);
  357. if (cs_change) {
  358. ndelay(nsecs);
  359. fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
  360. ndelay(nsecs);
  361. }
  362. }
  363. m->status = status;
  364. if (status || !cs_change) {
  365. ndelay(nsecs);
  366. fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
  367. }
  368. fsl_spi_setup_transfer(spi, NULL);
  369. spi_finalize_current_message(master);
  370. return 0;
  371. }
  372. static int fsl_spi_setup(struct spi_device *spi)
  373. {
  374. struct mpc8xxx_spi *mpc8xxx_spi;
  375. struct fsl_spi_reg __iomem *reg_base;
  376. bool initial_setup = false;
  377. int retval;
  378. u32 hw_mode;
  379. struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
  380. if (!spi->max_speed_hz)
  381. return -EINVAL;
  382. if (!cs) {
  383. cs = kzalloc(sizeof(*cs), GFP_KERNEL);
  384. if (!cs)
  385. return -ENOMEM;
  386. spi_set_ctldata(spi, cs);
  387. initial_setup = true;
  388. }
  389. mpc8xxx_spi = spi_master_get_devdata(spi->master);
  390. reg_base = mpc8xxx_spi->reg_base;
  391. hw_mode = cs->hw_mode; /* Save original settings */
  392. cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
  393. /* mask out bits we are going to set */
  394. cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
  395. | SPMODE_REV | SPMODE_LOOP);
  396. if (spi->mode & SPI_CPHA)
  397. cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
  398. if (spi->mode & SPI_CPOL)
  399. cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
  400. if (!(spi->mode & SPI_LSB_FIRST))
  401. cs->hw_mode |= SPMODE_REV;
  402. if (spi->mode & SPI_LOOP)
  403. cs->hw_mode |= SPMODE_LOOP;
  404. retval = fsl_spi_setup_transfer(spi, NULL);
  405. if (retval < 0) {
  406. cs->hw_mode = hw_mode; /* Restore settings */
  407. if (initial_setup)
  408. kfree(cs);
  409. return retval;
  410. }
  411. /* Initialize chipselect - might be active for SPI_CS_HIGH mode */
  412. fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
  413. return 0;
  414. }
  415. static void fsl_spi_cleanup(struct spi_device *spi)
  416. {
  417. struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
  418. kfree(cs);
  419. spi_set_ctldata(spi, NULL);
  420. }
  421. static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
  422. {
  423. struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
  424. /* We need handle RX first */
  425. if (events & SPIE_NE) {
  426. u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
  427. if (mspi->rx)
  428. mspi->get_rx(rx_data, mspi);
  429. }
  430. if ((events & SPIE_NF) == 0)
  431. /* spin until TX is done */
  432. while (((events =
  433. mpc8xxx_spi_read_reg(&reg_base->event)) &
  434. SPIE_NF) == 0)
  435. cpu_relax();
  436. /* Clear the events */
  437. mpc8xxx_spi_write_reg(&reg_base->event, events);
  438. mspi->count -= 1;
  439. if (mspi->count) {
  440. u32 word = mspi->get_tx(mspi);
  441. mpc8xxx_spi_write_reg(&reg_base->transmit, word);
  442. } else {
  443. complete(&mspi->done);
  444. }
  445. }
  446. static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
  447. {
  448. struct mpc8xxx_spi *mspi = context_data;
  449. irqreturn_t ret = IRQ_NONE;
  450. u32 events;
  451. struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
  452. /* Get interrupt events(tx/rx) */
  453. events = mpc8xxx_spi_read_reg(&reg_base->event);
  454. if (events)
  455. ret = IRQ_HANDLED;
  456. dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
  457. if (mspi->flags & SPI_CPM_MODE)
  458. fsl_spi_cpm_irq(mspi, events);
  459. else
  460. fsl_spi_cpu_irq(mspi, events);
  461. return ret;
  462. }
  463. static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
  464. {
  465. struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
  466. struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
  467. u32 slvsel;
  468. u16 cs = spi->chip_select;
  469. if (spi->cs_gpiod) {
  470. gpiod_set_value(spi->cs_gpiod, on);
  471. } else if (cs < mpc8xxx_spi->native_chipselects) {
  472. slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
  473. slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
  474. mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
  475. }
  476. }
  477. static void fsl_spi_grlib_probe(struct device *dev)
  478. {
  479. struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
  480. struct spi_master *master = dev_get_drvdata(dev);
  481. struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
  482. struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
  483. int mbits;
  484. u32 capabilities;
  485. capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
  486. mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
  487. mbits = SPCAP_MAXWLEN(capabilities);
  488. if (mbits)
  489. mpc8xxx_spi->max_bits_per_word = mbits + 1;
  490. mpc8xxx_spi->native_chipselects = 0;
  491. if (SPCAP_SSEN(capabilities)) {
  492. mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
  493. mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
  494. }
  495. master->num_chipselect = mpc8xxx_spi->native_chipselects;
  496. pdata->cs_control = fsl_spi_grlib_cs_control;
  497. }
  498. static struct spi_master *fsl_spi_probe(struct device *dev,
  499. struct resource *mem, unsigned int irq)
  500. {
  501. struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
  502. struct spi_master *master;
  503. struct mpc8xxx_spi *mpc8xxx_spi;
  504. struct fsl_spi_reg __iomem *reg_base;
  505. u32 regval;
  506. int ret = 0;
  507. master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
  508. if (master == NULL) {
  509. ret = -ENOMEM;
  510. goto err;
  511. }
  512. dev_set_drvdata(dev, master);
  513. mpc8xxx_spi_probe(dev, mem, irq);
  514. master->setup = fsl_spi_setup;
  515. master->cleanup = fsl_spi_cleanup;
  516. master->transfer_one_message = fsl_spi_do_one_msg;
  517. master->use_gpio_descriptors = true;
  518. mpc8xxx_spi = spi_master_get_devdata(master);
  519. mpc8xxx_spi->max_bits_per_word = 32;
  520. mpc8xxx_spi->type = fsl_spi_get_type(dev);
  521. ret = fsl_spi_cpm_init(mpc8xxx_spi);
  522. if (ret)
  523. goto err_cpm_init;
  524. mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
  525. if (IS_ERR(mpc8xxx_spi->reg_base)) {
  526. ret = PTR_ERR(mpc8xxx_spi->reg_base);
  527. goto err_probe;
  528. }
  529. if (mpc8xxx_spi->type == TYPE_GRLIB)
  530. fsl_spi_grlib_probe(dev);
  531. master->bits_per_word_mask =
  532. (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
  533. SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
  534. if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
  535. mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
  536. if (mpc8xxx_spi->set_shifts)
  537. /* 8 bits per word and MSB first */
  538. mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
  539. &mpc8xxx_spi->tx_shift, 8, 1);
  540. /* Register for SPI Interrupt */
  541. ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
  542. 0, "fsl_spi", mpc8xxx_spi);
  543. if (ret != 0)
  544. goto err_probe;
  545. reg_base = mpc8xxx_spi->reg_base;
  546. /* SPI controller initializations */
  547. mpc8xxx_spi_write_reg(&reg_base->mode, 0);
  548. mpc8xxx_spi_write_reg(&reg_base->mask, 0);
  549. mpc8xxx_spi_write_reg(&reg_base->command, 0);
  550. mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
  551. /* Enable SPI interface */
  552. regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
  553. if (mpc8xxx_spi->max_bits_per_word < 8) {
  554. regval &= ~SPMODE_LEN(0xF);
  555. regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
  556. }
  557. if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
  558. regval |= SPMODE_OP;
  559. mpc8xxx_spi_write_reg(&reg_base->mode, regval);
  560. ret = devm_spi_register_master(dev, master);
  561. if (ret < 0)
  562. goto err_probe;
  563. dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
  564. mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
  565. return master;
  566. err_probe:
  567. fsl_spi_cpm_free(mpc8xxx_spi);
  568. err_cpm_init:
  569. spi_master_put(master);
  570. err:
  571. return ERR_PTR(ret);
  572. }
  573. static void fsl_spi_cs_control(struct spi_device *spi, bool on)
  574. {
  575. if (spi->cs_gpiod) {
  576. gpiod_set_value(spi->cs_gpiod, on);
  577. } else {
  578. struct device *dev = spi->dev.parent->parent;
  579. struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
  580. struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
  581. if (WARN_ON_ONCE(!pinfo->immr_spi_cs))
  582. return;
  583. iowrite32be(on ? 0 : SPI_BOOT_SEL_BIT, pinfo->immr_spi_cs);
  584. }
  585. }
  586. static int of_fsl_spi_probe(struct platform_device *ofdev)
  587. {
  588. struct device *dev = &ofdev->dev;
  589. struct device_node *np = ofdev->dev.of_node;
  590. struct spi_master *master;
  591. struct resource mem;
  592. int irq, type;
  593. int ret;
  594. bool spisel_boot = false;
  595. #if IS_ENABLED(CONFIG_FSL_SOC)
  596. struct mpc8xxx_spi_probe_info *pinfo = NULL;
  597. #endif
  598. ret = of_mpc8xxx_spi_probe(ofdev);
  599. if (ret)
  600. return ret;
  601. type = fsl_spi_get_type(&ofdev->dev);
  602. if (type == TYPE_FSL) {
  603. struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
  604. #if IS_ENABLED(CONFIG_FSL_SOC)
  605. pinfo = to_of_pinfo(pdata);
  606. spisel_boot = of_property_read_bool(np, "fsl,spisel_boot");
  607. if (spisel_boot) {
  608. pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4);
  609. if (!pinfo->immr_spi_cs)
  610. return -ENOMEM;
  611. }
  612. #endif
  613. /*
  614. * Handle the case where we have one hardwired (always selected)
  615. * device on the first "chipselect". Else we let the core code
  616. * handle any GPIOs or native chip selects and assign the
  617. * appropriate callback for dealing with the CS lines. This isn't
  618. * supported on the GRLIB variant.
  619. */
  620. ret = gpiod_count(dev, "cs");
  621. if (ret < 0)
  622. ret = 0;
  623. if (ret == 0 && !spisel_boot) {
  624. pdata->max_chipselect = 1;
  625. } else {
  626. pdata->max_chipselect = ret + spisel_boot;
  627. pdata->cs_control = fsl_spi_cs_control;
  628. }
  629. }
  630. ret = of_address_to_resource(np, 0, &mem);
  631. if (ret)
  632. goto unmap_out;
  633. irq = platform_get_irq(ofdev, 0);
  634. if (irq < 0) {
  635. ret = irq;
  636. goto unmap_out;
  637. }
  638. master = fsl_spi_probe(dev, &mem, irq);
  639. return PTR_ERR_OR_ZERO(master);
  640. unmap_out:
  641. #if IS_ENABLED(CONFIG_FSL_SOC)
  642. if (spisel_boot)
  643. iounmap(pinfo->immr_spi_cs);
  644. #endif
  645. return ret;
  646. }
  647. static int of_fsl_spi_remove(struct platform_device *ofdev)
  648. {
  649. struct spi_master *master = platform_get_drvdata(ofdev);
  650. struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
  651. fsl_spi_cpm_free(mpc8xxx_spi);
  652. return 0;
  653. }
  654. static struct platform_driver of_fsl_spi_driver = {
  655. .driver = {
  656. .name = "fsl_spi",
  657. .of_match_table = of_fsl_spi_match,
  658. },
  659. .probe = of_fsl_spi_probe,
  660. .remove = of_fsl_spi_remove,
  661. };
  662. #ifdef CONFIG_MPC832x_RDB
  663. /*
  664. * XXX XXX XXX
  665. * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
  666. * only. The driver should go away soon, since newer MPC8323E-RDB's device
  667. * tree can work with OpenFirmware driver. But for now we support old trees
  668. * as well.
  669. */
  670. static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
  671. {
  672. struct resource *mem;
  673. int irq;
  674. struct spi_master *master;
  675. if (!dev_get_platdata(&pdev->dev))
  676. return -EINVAL;
  677. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  678. if (!mem)
  679. return -EINVAL;
  680. irq = platform_get_irq(pdev, 0);
  681. if (irq <= 0)
  682. return -EINVAL;
  683. master = fsl_spi_probe(&pdev->dev, mem, irq);
  684. return PTR_ERR_OR_ZERO(master);
  685. }
  686. static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
  687. {
  688. struct spi_master *master = platform_get_drvdata(pdev);
  689. struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
  690. fsl_spi_cpm_free(mpc8xxx_spi);
  691. return 0;
  692. }
  693. MODULE_ALIAS("platform:mpc8xxx_spi");
  694. static struct platform_driver mpc8xxx_spi_driver = {
  695. .probe = plat_mpc8xxx_spi_probe,
  696. .remove = plat_mpc8xxx_spi_remove,
  697. .driver = {
  698. .name = "mpc8xxx_spi",
  699. },
  700. };
  701. static bool legacy_driver_failed;
  702. static void __init legacy_driver_register(void)
  703. {
  704. legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
  705. }
  706. static void __exit legacy_driver_unregister(void)
  707. {
  708. if (legacy_driver_failed)
  709. return;
  710. platform_driver_unregister(&mpc8xxx_spi_driver);
  711. }
  712. #else
  713. static void __init legacy_driver_register(void) {}
  714. static void __exit legacy_driver_unregister(void) {}
  715. #endif /* CONFIG_MPC832x_RDB */
  716. static int __init fsl_spi_init(void)
  717. {
  718. legacy_driver_register();
  719. return platform_driver_register(&of_fsl_spi_driver);
  720. }
  721. module_init(fsl_spi_init);
  722. static void __exit fsl_spi_exit(void)
  723. {
  724. platform_driver_unregister(&of_fsl_spi_driver);
  725. legacy_driver_unregister();
  726. }
  727. module_exit(fsl_spi_exit);
  728. MODULE_AUTHOR("Kumar Gala");
  729. MODULE_DESCRIPTION("Simple Freescale SPI Driver");
  730. MODULE_LICENSE("GPL");